1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::RGD_WORD2 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct M0UMR {
47 bits: u8,
48}
49impl M0UMR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = r" Value of the field"]
57pub struct M0SMR {
58 bits: u8,
59}
60impl M0SMR {
61 #[doc = r" Value of the field as raw bits"]
62 #[inline]
63 pub fn bits(&self) -> u8 {
64 self.bits
65 }
66}
67#[doc = r" Value of the field"]
68pub struct M0PER {
69 bits: bool,
70}
71impl M0PER {
72 #[doc = r" Value of the field as raw bits"]
73 #[inline]
74 pub fn bit(&self) -> bool {
75 self.bits
76 }
77 #[doc = r" Returns `true` if the bit is clear (0)"]
78 #[inline]
79 pub fn bit_is_clear(&self) -> bool {
80 !self.bit()
81 }
82 #[doc = r" Returns `true` if the bit is set (1)"]
83 #[inline]
84 pub fn bit_is_set(&self) -> bool {
85 self.bit()
86 }
87}
88#[doc = r" Value of the field"]
89pub struct M1UMR {
90 bits: u8,
91}
92impl M1UMR {
93 #[doc = r" Value of the field as raw bits"]
94 #[inline]
95 pub fn bits(&self) -> u8 {
96 self.bits
97 }
98}
99#[doc = r" Value of the field"]
100pub struct M1SMR {
101 bits: u8,
102}
103impl M1SMR {
104 #[doc = r" Value of the field as raw bits"]
105 #[inline]
106 pub fn bits(&self) -> u8 {
107 self.bits
108 }
109}
110#[doc = r" Value of the field"]
111pub struct M1PER {
112 bits: bool,
113}
114impl M1PER {
115 #[doc = r" Value of the field as raw bits"]
116 #[inline]
117 pub fn bit(&self) -> bool {
118 self.bits
119 }
120 #[doc = r" Returns `true` if the bit is clear (0)"]
121 #[inline]
122 pub fn bit_is_clear(&self) -> bool {
123 !self.bit()
124 }
125 #[doc = r" Returns `true` if the bit is set (1)"]
126 #[inline]
127 pub fn bit_is_set(&self) -> bool {
128 self.bit()
129 }
130}
131#[doc = r" Value of the field"]
132pub struct M2UMR {
133 bits: u8,
134}
135impl M2UMR {
136 #[doc = r" Value of the field as raw bits"]
137 #[inline]
138 pub fn bits(&self) -> u8 {
139 self.bits
140 }
141}
142#[doc = r" Value of the field"]
143pub struct M2SMR {
144 bits: u8,
145}
146impl M2SMR {
147 #[doc = r" Value of the field as raw bits"]
148 #[inline]
149 pub fn bits(&self) -> u8 {
150 self.bits
151 }
152}
153#[doc = r" Value of the field"]
154pub struct M2PER {
155 bits: bool,
156}
157impl M2PER {
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 self.bits
162 }
163 #[doc = r" Returns `true` if the bit is clear (0)"]
164 #[inline]
165 pub fn bit_is_clear(&self) -> bool {
166 !self.bit()
167 }
168 #[doc = r" Returns `true` if the bit is set (1)"]
169 #[inline]
170 pub fn bit_is_set(&self) -> bool {
171 self.bit()
172 }
173}
174#[doc = "Possible values of the field `M3UM`"]
175#[derive(Clone, Copy, Debug, PartialEq)]
176pub enum M3UMR {
177 #[doc = "An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed."]
178 _0,
179 #[doc = "Allows the given access type to occur"]
180 _1,
181 #[doc = r" Reserved"]
182 _Reserved(u8),
183}
184impl M3UMR {
185 #[doc = r" Value of the field as raw bits"]
186 #[inline]
187 pub fn bits(&self) -> u8 {
188 match *self {
189 M3UMR::_0 => 0,
190 M3UMR::_1 => 1,
191 M3UMR::_Reserved(bits) => bits,
192 }
193 }
194 #[allow(missing_docs)]
195 #[doc(hidden)]
196 #[inline]
197 pub fn _from(value: u8) -> M3UMR {
198 match value {
199 0 => M3UMR::_0,
200 1 => M3UMR::_1,
201 i => M3UMR::_Reserved(i),
202 }
203 }
204 #[doc = "Checks if the value of the field is `_0`"]
205 #[inline]
206 pub fn is_0(&self) -> bool {
207 *self == M3UMR::_0
208 }
209 #[doc = "Checks if the value of the field is `_1`"]
210 #[inline]
211 pub fn is_1(&self) -> bool {
212 *self == M3UMR::_1
213 }
214}
215#[doc = "Possible values of the field `M3SM`"]
216#[derive(Clone, Copy, Debug, PartialEq)]
217pub enum M3SMR {
218 #[doc = "r/w/x; read, write and execute allowed"]
219 _00,
220 #[doc = "r/x; read and execute allowed, but no write"]
221 _01,
222 #[doc = "r/w; read and write allowed, but no execute"]
223 _10,
224 #[doc = "Same as User mode defined in M3UM"]
225 _11,
226}
227impl M3SMR {
228 #[doc = r" Value of the field as raw bits"]
229 #[inline]
230 pub fn bits(&self) -> u8 {
231 match *self {
232 M3SMR::_00 => 0,
233 M3SMR::_01 => 1,
234 M3SMR::_10 => 2,
235 M3SMR::_11 => 3,
236 }
237 }
238 #[allow(missing_docs)]
239 #[doc(hidden)]
240 #[inline]
241 pub fn _from(value: u8) -> M3SMR {
242 match value {
243 0 => M3SMR::_00,
244 1 => M3SMR::_01,
245 2 => M3SMR::_10,
246 3 => M3SMR::_11,
247 _ => unreachable!(),
248 }
249 }
250 #[doc = "Checks if the value of the field is `_00`"]
251 #[inline]
252 pub fn is_00(&self) -> bool {
253 *self == M3SMR::_00
254 }
255 #[doc = "Checks if the value of the field is `_01`"]
256 #[inline]
257 pub fn is_01(&self) -> bool {
258 *self == M3SMR::_01
259 }
260 #[doc = "Checks if the value of the field is `_10`"]
261 #[inline]
262 pub fn is_10(&self) -> bool {
263 *self == M3SMR::_10
264 }
265 #[doc = "Checks if the value of the field is `_11`"]
266 #[inline]
267 pub fn is_11(&self) -> bool {
268 *self == M3SMR::_11
269 }
270}
271#[doc = "Possible values of the field `M3PE`"]
272#[derive(Clone, Copy, Debug, PartialEq)]
273pub enum M3PER {
274 #[doc = "Do not include the process identifier in the evaluation"]
275 _0,
276 #[doc = "Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation"]
277 _1,
278}
279impl M3PER {
280 #[doc = r" Returns `true` if the bit is clear (0)"]
281 #[inline]
282 pub fn bit_is_clear(&self) -> bool {
283 !self.bit()
284 }
285 #[doc = r" Returns `true` if the bit is set (1)"]
286 #[inline]
287 pub fn bit_is_set(&self) -> bool {
288 self.bit()
289 }
290 #[doc = r" Value of the field as raw bits"]
291 #[inline]
292 pub fn bit(&self) -> bool {
293 match *self {
294 M3PER::_0 => false,
295 M3PER::_1 => true,
296 }
297 }
298 #[allow(missing_docs)]
299 #[doc(hidden)]
300 #[inline]
301 pub fn _from(value: bool) -> M3PER {
302 match value {
303 false => M3PER::_0,
304 true => M3PER::_1,
305 }
306 }
307 #[doc = "Checks if the value of the field is `_0`"]
308 #[inline]
309 pub fn is_0(&self) -> bool {
310 *self == M3PER::_0
311 }
312 #[doc = "Checks if the value of the field is `_1`"]
313 #[inline]
314 pub fn is_1(&self) -> bool {
315 *self == M3PER::_1
316 }
317}
318#[doc = "Possible values of the field `M4WE`"]
319#[derive(Clone, Copy, Debug, PartialEq)]
320pub enum M4WER {
321 #[doc = "Bus master 4 writes terminate with an access error and the write is not performed"]
322 _0,
323 #[doc = "Bus master 4 writes allowed"]
324 _1,
325}
326impl M4WER {
327 #[doc = r" Returns `true` if the bit is clear (0)"]
328 #[inline]
329 pub fn bit_is_clear(&self) -> bool {
330 !self.bit()
331 }
332 #[doc = r" Returns `true` if the bit is set (1)"]
333 #[inline]
334 pub fn bit_is_set(&self) -> bool {
335 self.bit()
336 }
337 #[doc = r" Value of the field as raw bits"]
338 #[inline]
339 pub fn bit(&self) -> bool {
340 match *self {
341 M4WER::_0 => false,
342 M4WER::_1 => true,
343 }
344 }
345 #[allow(missing_docs)]
346 #[doc(hidden)]
347 #[inline]
348 pub fn _from(value: bool) -> M4WER {
349 match value {
350 false => M4WER::_0,
351 true => M4WER::_1,
352 }
353 }
354 #[doc = "Checks if the value of the field is `_0`"]
355 #[inline]
356 pub fn is_0(&self) -> bool {
357 *self == M4WER::_0
358 }
359 #[doc = "Checks if the value of the field is `_1`"]
360 #[inline]
361 pub fn is_1(&self) -> bool {
362 *self == M4WER::_1
363 }
364}
365#[doc = "Possible values of the field `M4RE`"]
366#[derive(Clone, Copy, Debug, PartialEq)]
367pub enum M4RER {
368 #[doc = "Bus master 4 reads terminate with an access error and the read is not performed"]
369 _0,
370 #[doc = "Bus master 4 reads allowed"]
371 _1,
372}
373impl M4RER {
374 #[doc = r" Returns `true` if the bit is clear (0)"]
375 #[inline]
376 pub fn bit_is_clear(&self) -> bool {
377 !self.bit()
378 }
379 #[doc = r" Returns `true` if the bit is set (1)"]
380 #[inline]
381 pub fn bit_is_set(&self) -> bool {
382 self.bit()
383 }
384 #[doc = r" Value of the field as raw bits"]
385 #[inline]
386 pub fn bit(&self) -> bool {
387 match *self {
388 M4RER::_0 => false,
389 M4RER::_1 => true,
390 }
391 }
392 #[allow(missing_docs)]
393 #[doc(hidden)]
394 #[inline]
395 pub fn _from(value: bool) -> M4RER {
396 match value {
397 false => M4RER::_0,
398 true => M4RER::_1,
399 }
400 }
401 #[doc = "Checks if the value of the field is `_0`"]
402 #[inline]
403 pub fn is_0(&self) -> bool {
404 *self == M4RER::_0
405 }
406 #[doc = "Checks if the value of the field is `_1`"]
407 #[inline]
408 pub fn is_1(&self) -> bool {
409 *self == M4RER::_1
410 }
411}
412#[doc = "Possible values of the field `M5WE`"]
413#[derive(Clone, Copy, Debug, PartialEq)]
414pub enum M5WER {
415 #[doc = "Bus master 5 writes terminate with an access error and the write is not performed"]
416 _0,
417 #[doc = "Bus master 5 writes allowed"]
418 _1,
419}
420impl M5WER {
421 #[doc = r" Returns `true` if the bit is clear (0)"]
422 #[inline]
423 pub fn bit_is_clear(&self) -> bool {
424 !self.bit()
425 }
426 #[doc = r" Returns `true` if the bit is set (1)"]
427 #[inline]
428 pub fn bit_is_set(&self) -> bool {
429 self.bit()
430 }
431 #[doc = r" Value of the field as raw bits"]
432 #[inline]
433 pub fn bit(&self) -> bool {
434 match *self {
435 M5WER::_0 => false,
436 M5WER::_1 => true,
437 }
438 }
439 #[allow(missing_docs)]
440 #[doc(hidden)]
441 #[inline]
442 pub fn _from(value: bool) -> M5WER {
443 match value {
444 false => M5WER::_0,
445 true => M5WER::_1,
446 }
447 }
448 #[doc = "Checks if the value of the field is `_0`"]
449 #[inline]
450 pub fn is_0(&self) -> bool {
451 *self == M5WER::_0
452 }
453 #[doc = "Checks if the value of the field is `_1`"]
454 #[inline]
455 pub fn is_1(&self) -> bool {
456 *self == M5WER::_1
457 }
458}
459#[doc = "Possible values of the field `M5RE`"]
460#[derive(Clone, Copy, Debug, PartialEq)]
461pub enum M5RER {
462 #[doc = "Bus master 5 reads terminate with an access error and the read is not performed"]
463 _0,
464 #[doc = "Bus master 5 reads allowed"]
465 _1,
466}
467impl M5RER {
468 #[doc = r" Returns `true` if the bit is clear (0)"]
469 #[inline]
470 pub fn bit_is_clear(&self) -> bool {
471 !self.bit()
472 }
473 #[doc = r" Returns `true` if the bit is set (1)"]
474 #[inline]
475 pub fn bit_is_set(&self) -> bool {
476 self.bit()
477 }
478 #[doc = r" Value of the field as raw bits"]
479 #[inline]
480 pub fn bit(&self) -> bool {
481 match *self {
482 M5RER::_0 => false,
483 M5RER::_1 => true,
484 }
485 }
486 #[allow(missing_docs)]
487 #[doc(hidden)]
488 #[inline]
489 pub fn _from(value: bool) -> M5RER {
490 match value {
491 false => M5RER::_0,
492 true => M5RER::_1,
493 }
494 }
495 #[doc = "Checks if the value of the field is `_0`"]
496 #[inline]
497 pub fn is_0(&self) -> bool {
498 *self == M5RER::_0
499 }
500 #[doc = "Checks if the value of the field is `_1`"]
501 #[inline]
502 pub fn is_1(&self) -> bool {
503 *self == M5RER::_1
504 }
505}
506#[doc = "Possible values of the field `M6WE`"]
507#[derive(Clone, Copy, Debug, PartialEq)]
508pub enum M6WER {
509 #[doc = "Bus master 6 writes terminate with an access error and the write is not performed"]
510 _0,
511 #[doc = "Bus master 6 writes allowed"]
512 _1,
513}
514impl M6WER {
515 #[doc = r" Returns `true` if the bit is clear (0)"]
516 #[inline]
517 pub fn bit_is_clear(&self) -> bool {
518 !self.bit()
519 }
520 #[doc = r" Returns `true` if the bit is set (1)"]
521 #[inline]
522 pub fn bit_is_set(&self) -> bool {
523 self.bit()
524 }
525 #[doc = r" Value of the field as raw bits"]
526 #[inline]
527 pub fn bit(&self) -> bool {
528 match *self {
529 M6WER::_0 => false,
530 M6WER::_1 => true,
531 }
532 }
533 #[allow(missing_docs)]
534 #[doc(hidden)]
535 #[inline]
536 pub fn _from(value: bool) -> M6WER {
537 match value {
538 false => M6WER::_0,
539 true => M6WER::_1,
540 }
541 }
542 #[doc = "Checks if the value of the field is `_0`"]
543 #[inline]
544 pub fn is_0(&self) -> bool {
545 *self == M6WER::_0
546 }
547 #[doc = "Checks if the value of the field is `_1`"]
548 #[inline]
549 pub fn is_1(&self) -> bool {
550 *self == M6WER::_1
551 }
552}
553#[doc = "Possible values of the field `M6RE`"]
554#[derive(Clone, Copy, Debug, PartialEq)]
555pub enum M6RER {
556 #[doc = "Bus master 6 reads terminate with an access error and the read is not performed"]
557 _0,
558 #[doc = "Bus master 6 reads allowed"]
559 _1,
560}
561impl M6RER {
562 #[doc = r" Returns `true` if the bit is clear (0)"]
563 #[inline]
564 pub fn bit_is_clear(&self) -> bool {
565 !self.bit()
566 }
567 #[doc = r" Returns `true` if the bit is set (1)"]
568 #[inline]
569 pub fn bit_is_set(&self) -> bool {
570 self.bit()
571 }
572 #[doc = r" Value of the field as raw bits"]
573 #[inline]
574 pub fn bit(&self) -> bool {
575 match *self {
576 M6RER::_0 => false,
577 M6RER::_1 => true,
578 }
579 }
580 #[allow(missing_docs)]
581 #[doc(hidden)]
582 #[inline]
583 pub fn _from(value: bool) -> M6RER {
584 match value {
585 false => M6RER::_0,
586 true => M6RER::_1,
587 }
588 }
589 #[doc = "Checks if the value of the field is `_0`"]
590 #[inline]
591 pub fn is_0(&self) -> bool {
592 *self == M6RER::_0
593 }
594 #[doc = "Checks if the value of the field is `_1`"]
595 #[inline]
596 pub fn is_1(&self) -> bool {
597 *self == M6RER::_1
598 }
599}
600#[doc = "Possible values of the field `M7WE`"]
601#[derive(Clone, Copy, Debug, PartialEq)]
602pub enum M7WER {
603 #[doc = "Bus master 7 writes terminate with an access error and the write is not performed"]
604 _0,
605 #[doc = "Bus master 7 writes allowed"]
606 _1,
607}
608impl M7WER {
609 #[doc = r" Returns `true` if the bit is clear (0)"]
610 #[inline]
611 pub fn bit_is_clear(&self) -> bool {
612 !self.bit()
613 }
614 #[doc = r" Returns `true` if the bit is set (1)"]
615 #[inline]
616 pub fn bit_is_set(&self) -> bool {
617 self.bit()
618 }
619 #[doc = r" Value of the field as raw bits"]
620 #[inline]
621 pub fn bit(&self) -> bool {
622 match *self {
623 M7WER::_0 => false,
624 M7WER::_1 => true,
625 }
626 }
627 #[allow(missing_docs)]
628 #[doc(hidden)]
629 #[inline]
630 pub fn _from(value: bool) -> M7WER {
631 match value {
632 false => M7WER::_0,
633 true => M7WER::_1,
634 }
635 }
636 #[doc = "Checks if the value of the field is `_0`"]
637 #[inline]
638 pub fn is_0(&self) -> bool {
639 *self == M7WER::_0
640 }
641 #[doc = "Checks if the value of the field is `_1`"]
642 #[inline]
643 pub fn is_1(&self) -> bool {
644 *self == M7WER::_1
645 }
646}
647#[doc = "Possible values of the field `M7RE`"]
648#[derive(Clone, Copy, Debug, PartialEq)]
649pub enum M7RER {
650 #[doc = "Bus master 7 reads terminate with an access error and the read is not performed"]
651 _0,
652 #[doc = "Bus master 7 reads allowed"]
653 _1,
654}
655impl M7RER {
656 #[doc = r" Returns `true` if the bit is clear (0)"]
657 #[inline]
658 pub fn bit_is_clear(&self) -> bool {
659 !self.bit()
660 }
661 #[doc = r" Returns `true` if the bit is set (1)"]
662 #[inline]
663 pub fn bit_is_set(&self) -> bool {
664 self.bit()
665 }
666 #[doc = r" Value of the field as raw bits"]
667 #[inline]
668 pub fn bit(&self) -> bool {
669 match *self {
670 M7RER::_0 => false,
671 M7RER::_1 => true,
672 }
673 }
674 #[allow(missing_docs)]
675 #[doc(hidden)]
676 #[inline]
677 pub fn _from(value: bool) -> M7RER {
678 match value {
679 false => M7RER::_0,
680 true => M7RER::_1,
681 }
682 }
683 #[doc = "Checks if the value of the field is `_0`"]
684 #[inline]
685 pub fn is_0(&self) -> bool {
686 *self == M7RER::_0
687 }
688 #[doc = "Checks if the value of the field is `_1`"]
689 #[inline]
690 pub fn is_1(&self) -> bool {
691 *self == M7RER::_1
692 }
693}
694#[doc = r" Proxy"]
695pub struct _M0UMW<'a> {
696 w: &'a mut W,
697}
698impl<'a> _M0UMW<'a> {
699 #[doc = r" Writes raw bits to the field"]
700 #[inline]
701 pub unsafe fn bits(self, value: u8) -> &'a mut W {
702 const MASK: u8 = 7;
703 const OFFSET: u8 = 0;
704 self.w.bits &= !((MASK as u32) << OFFSET);
705 self.w.bits |= ((value & MASK) as u32) << OFFSET;
706 self.w
707 }
708}
709#[doc = r" Proxy"]
710pub struct _M0SMW<'a> {
711 w: &'a mut W,
712}
713impl<'a> _M0SMW<'a> {
714 #[doc = r" Writes raw bits to the field"]
715 #[inline]
716 pub unsafe fn bits(self, value: u8) -> &'a mut W {
717 const MASK: u8 = 3;
718 const OFFSET: u8 = 3;
719 self.w.bits &= !((MASK as u32) << OFFSET);
720 self.w.bits |= ((value & MASK) as u32) << OFFSET;
721 self.w
722 }
723}
724#[doc = r" Proxy"]
725pub struct _M0PEW<'a> {
726 w: &'a mut W,
727}
728impl<'a> _M0PEW<'a> {
729 #[doc = r" Sets the field bit"]
730 pub fn set_bit(self) -> &'a mut W {
731 self.bit(true)
732 }
733 #[doc = r" Clears the field bit"]
734 pub fn clear_bit(self) -> &'a mut W {
735 self.bit(false)
736 }
737 #[doc = r" Writes raw bits to the field"]
738 #[inline]
739 pub fn bit(self, value: bool) -> &'a mut W {
740 const MASK: bool = true;
741 const OFFSET: u8 = 5;
742 self.w.bits &= !((MASK as u32) << OFFSET);
743 self.w.bits |= ((value & MASK) as u32) << OFFSET;
744 self.w
745 }
746}
747#[doc = r" Proxy"]
748pub struct _M1UMW<'a> {
749 w: &'a mut W,
750}
751impl<'a> _M1UMW<'a> {
752 #[doc = r" Writes raw bits to the field"]
753 #[inline]
754 pub unsafe fn bits(self, value: u8) -> &'a mut W {
755 const MASK: u8 = 7;
756 const OFFSET: u8 = 6;
757 self.w.bits &= !((MASK as u32) << OFFSET);
758 self.w.bits |= ((value & MASK) as u32) << OFFSET;
759 self.w
760 }
761}
762#[doc = r" Proxy"]
763pub struct _M1SMW<'a> {
764 w: &'a mut W,
765}
766impl<'a> _M1SMW<'a> {
767 #[doc = r" Writes raw bits to the field"]
768 #[inline]
769 pub unsafe fn bits(self, value: u8) -> &'a mut W {
770 const MASK: u8 = 3;
771 const OFFSET: u8 = 9;
772 self.w.bits &= !((MASK as u32) << OFFSET);
773 self.w.bits |= ((value & MASK) as u32) << OFFSET;
774 self.w
775 }
776}
777#[doc = r" Proxy"]
778pub struct _M1PEW<'a> {
779 w: &'a mut W,
780}
781impl<'a> _M1PEW<'a> {
782 #[doc = r" Sets the field bit"]
783 pub fn set_bit(self) -> &'a mut W {
784 self.bit(true)
785 }
786 #[doc = r" Clears the field bit"]
787 pub fn clear_bit(self) -> &'a mut W {
788 self.bit(false)
789 }
790 #[doc = r" Writes raw bits to the field"]
791 #[inline]
792 pub fn bit(self, value: bool) -> &'a mut W {
793 const MASK: bool = true;
794 const OFFSET: u8 = 11;
795 self.w.bits &= !((MASK as u32) << OFFSET);
796 self.w.bits |= ((value & MASK) as u32) << OFFSET;
797 self.w
798 }
799}
800#[doc = r" Proxy"]
801pub struct _M2UMW<'a> {
802 w: &'a mut W,
803}
804impl<'a> _M2UMW<'a> {
805 #[doc = r" Writes raw bits to the field"]
806 #[inline]
807 pub unsafe fn bits(self, value: u8) -> &'a mut W {
808 const MASK: u8 = 7;
809 const OFFSET: u8 = 12;
810 self.w.bits &= !((MASK as u32) << OFFSET);
811 self.w.bits |= ((value & MASK) as u32) << OFFSET;
812 self.w
813 }
814}
815#[doc = r" Proxy"]
816pub struct _M2SMW<'a> {
817 w: &'a mut W,
818}
819impl<'a> _M2SMW<'a> {
820 #[doc = r" Writes raw bits to the field"]
821 #[inline]
822 pub unsafe fn bits(self, value: u8) -> &'a mut W {
823 const MASK: u8 = 3;
824 const OFFSET: u8 = 15;
825 self.w.bits &= !((MASK as u32) << OFFSET);
826 self.w.bits |= ((value & MASK) as u32) << OFFSET;
827 self.w
828 }
829}
830#[doc = r" Proxy"]
831pub struct _M2PEW<'a> {
832 w: &'a mut W,
833}
834impl<'a> _M2PEW<'a> {
835 #[doc = r" Sets the field bit"]
836 pub fn set_bit(self) -> &'a mut W {
837 self.bit(true)
838 }
839 #[doc = r" Clears the field bit"]
840 pub fn clear_bit(self) -> &'a mut W {
841 self.bit(false)
842 }
843 #[doc = r" Writes raw bits to the field"]
844 #[inline]
845 pub fn bit(self, value: bool) -> &'a mut W {
846 const MASK: bool = true;
847 const OFFSET: u8 = 17;
848 self.w.bits &= !((MASK as u32) << OFFSET);
849 self.w.bits |= ((value & MASK) as u32) << OFFSET;
850 self.w
851 }
852}
853#[doc = "Values that can be written to the field `M3UM`"]
854pub enum M3UMW {
855 #[doc = "An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed."]
856 _0,
857 #[doc = "Allows the given access type to occur"]
858 _1,
859}
860impl M3UMW {
861 #[allow(missing_docs)]
862 #[doc(hidden)]
863 #[inline]
864 pub fn _bits(&self) -> u8 {
865 match *self {
866 M3UMW::_0 => 0,
867 M3UMW::_1 => 1,
868 }
869 }
870}
871#[doc = r" Proxy"]
872pub struct _M3UMW<'a> {
873 w: &'a mut W,
874}
875impl<'a> _M3UMW<'a> {
876 #[doc = r" Writes `variant` to the field"]
877 #[inline]
878 pub fn variant(self, variant: M3UMW) -> &'a mut W {
879 unsafe { self.bits(variant._bits()) }
880 }
881 #[doc = "An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed."]
882 #[inline]
883 pub fn _0(self) -> &'a mut W {
884 self.variant(M3UMW::_0)
885 }
886 #[doc = "Allows the given access type to occur"]
887 #[inline]
888 pub fn _1(self) -> &'a mut W {
889 self.variant(M3UMW::_1)
890 }
891 #[doc = r" Writes raw bits to the field"]
892 #[inline]
893 pub unsafe fn bits(self, value: u8) -> &'a mut W {
894 const MASK: u8 = 7;
895 const OFFSET: u8 = 18;
896 self.w.bits &= !((MASK as u32) << OFFSET);
897 self.w.bits |= ((value & MASK) as u32) << OFFSET;
898 self.w
899 }
900}
901#[doc = "Values that can be written to the field `M3SM`"]
902pub enum M3SMW {
903 #[doc = "r/w/x; read, write and execute allowed"]
904 _00,
905 #[doc = "r/x; read and execute allowed, but no write"]
906 _01,
907 #[doc = "r/w; read and write allowed, but no execute"]
908 _10,
909 #[doc = "Same as User mode defined in M3UM"]
910 _11,
911}
912impl M3SMW {
913 #[allow(missing_docs)]
914 #[doc(hidden)]
915 #[inline]
916 pub fn _bits(&self) -> u8 {
917 match *self {
918 M3SMW::_00 => 0,
919 M3SMW::_01 => 1,
920 M3SMW::_10 => 2,
921 M3SMW::_11 => 3,
922 }
923 }
924}
925#[doc = r" Proxy"]
926pub struct _M3SMW<'a> {
927 w: &'a mut W,
928}
929impl<'a> _M3SMW<'a> {
930 #[doc = r" Writes `variant` to the field"]
931 #[inline]
932 pub fn variant(self, variant: M3SMW) -> &'a mut W {
933 {
934 self.bits(variant._bits())
935 }
936 }
937 #[doc = "r/w/x; read, write and execute allowed"]
938 #[inline]
939 pub fn _00(self) -> &'a mut W {
940 self.variant(M3SMW::_00)
941 }
942 #[doc = "r/x; read and execute allowed, but no write"]
943 #[inline]
944 pub fn _01(self) -> &'a mut W {
945 self.variant(M3SMW::_01)
946 }
947 #[doc = "r/w; read and write allowed, but no execute"]
948 #[inline]
949 pub fn _10(self) -> &'a mut W {
950 self.variant(M3SMW::_10)
951 }
952 #[doc = "Same as User mode defined in M3UM"]
953 #[inline]
954 pub fn _11(self) -> &'a mut W {
955 self.variant(M3SMW::_11)
956 }
957 #[doc = r" Writes raw bits to the field"]
958 #[inline]
959 pub fn bits(self, value: u8) -> &'a mut W {
960 const MASK: u8 = 3;
961 const OFFSET: u8 = 21;
962 self.w.bits &= !((MASK as u32) << OFFSET);
963 self.w.bits |= ((value & MASK) as u32) << OFFSET;
964 self.w
965 }
966}
967#[doc = "Values that can be written to the field `M3PE`"]
968pub enum M3PEW {
969 #[doc = "Do not include the process identifier in the evaluation"]
970 _0,
971 #[doc = "Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation"]
972 _1,
973}
974impl M3PEW {
975 #[allow(missing_docs)]
976 #[doc(hidden)]
977 #[inline]
978 pub fn _bits(&self) -> bool {
979 match *self {
980 M3PEW::_0 => false,
981 M3PEW::_1 => true,
982 }
983 }
984}
985#[doc = r" Proxy"]
986pub struct _M3PEW<'a> {
987 w: &'a mut W,
988}
989impl<'a> _M3PEW<'a> {
990 #[doc = r" Writes `variant` to the field"]
991 #[inline]
992 pub fn variant(self, variant: M3PEW) -> &'a mut W {
993 {
994 self.bit(variant._bits())
995 }
996 }
997 #[doc = "Do not include the process identifier in the evaluation"]
998 #[inline]
999 pub fn _0(self) -> &'a mut W {
1000 self.variant(M3PEW::_0)
1001 }
1002 #[doc = "Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation"]
1003 #[inline]
1004 pub fn _1(self) -> &'a mut W {
1005 self.variant(M3PEW::_1)
1006 }
1007 #[doc = r" Sets the field bit"]
1008 pub fn set_bit(self) -> &'a mut W {
1009 self.bit(true)
1010 }
1011 #[doc = r" Clears the field bit"]
1012 pub fn clear_bit(self) -> &'a mut W {
1013 self.bit(false)
1014 }
1015 #[doc = r" Writes raw bits to the field"]
1016 #[inline]
1017 pub fn bit(self, value: bool) -> &'a mut W {
1018 const MASK: bool = true;
1019 const OFFSET: u8 = 23;
1020 self.w.bits &= !((MASK as u32) << OFFSET);
1021 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1022 self.w
1023 }
1024}
1025#[doc = "Values that can be written to the field `M4WE`"]
1026pub enum M4WEW {
1027 #[doc = "Bus master 4 writes terminate with an access error and the write is not performed"]
1028 _0,
1029 #[doc = "Bus master 4 writes allowed"]
1030 _1,
1031}
1032impl M4WEW {
1033 #[allow(missing_docs)]
1034 #[doc(hidden)]
1035 #[inline]
1036 pub fn _bits(&self) -> bool {
1037 match *self {
1038 M4WEW::_0 => false,
1039 M4WEW::_1 => true,
1040 }
1041 }
1042}
1043#[doc = r" Proxy"]
1044pub struct _M4WEW<'a> {
1045 w: &'a mut W,
1046}
1047impl<'a> _M4WEW<'a> {
1048 #[doc = r" Writes `variant` to the field"]
1049 #[inline]
1050 pub fn variant(self, variant: M4WEW) -> &'a mut W {
1051 {
1052 self.bit(variant._bits())
1053 }
1054 }
1055 #[doc = "Bus master 4 writes terminate with an access error and the write is not performed"]
1056 #[inline]
1057 pub fn _0(self) -> &'a mut W {
1058 self.variant(M4WEW::_0)
1059 }
1060 #[doc = "Bus master 4 writes allowed"]
1061 #[inline]
1062 pub fn _1(self) -> &'a mut W {
1063 self.variant(M4WEW::_1)
1064 }
1065 #[doc = r" Sets the field bit"]
1066 pub fn set_bit(self) -> &'a mut W {
1067 self.bit(true)
1068 }
1069 #[doc = r" Clears the field bit"]
1070 pub fn clear_bit(self) -> &'a mut W {
1071 self.bit(false)
1072 }
1073 #[doc = r" Writes raw bits to the field"]
1074 #[inline]
1075 pub fn bit(self, value: bool) -> &'a mut W {
1076 const MASK: bool = true;
1077 const OFFSET: u8 = 24;
1078 self.w.bits &= !((MASK as u32) << OFFSET);
1079 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1080 self.w
1081 }
1082}
1083#[doc = "Values that can be written to the field `M4RE`"]
1084pub enum M4REW {
1085 #[doc = "Bus master 4 reads terminate with an access error and the read is not performed"]
1086 _0,
1087 #[doc = "Bus master 4 reads allowed"]
1088 _1,
1089}
1090impl M4REW {
1091 #[allow(missing_docs)]
1092 #[doc(hidden)]
1093 #[inline]
1094 pub fn _bits(&self) -> bool {
1095 match *self {
1096 M4REW::_0 => false,
1097 M4REW::_1 => true,
1098 }
1099 }
1100}
1101#[doc = r" Proxy"]
1102pub struct _M4REW<'a> {
1103 w: &'a mut W,
1104}
1105impl<'a> _M4REW<'a> {
1106 #[doc = r" Writes `variant` to the field"]
1107 #[inline]
1108 pub fn variant(self, variant: M4REW) -> &'a mut W {
1109 {
1110 self.bit(variant._bits())
1111 }
1112 }
1113 #[doc = "Bus master 4 reads terminate with an access error and the read is not performed"]
1114 #[inline]
1115 pub fn _0(self) -> &'a mut W {
1116 self.variant(M4REW::_0)
1117 }
1118 #[doc = "Bus master 4 reads allowed"]
1119 #[inline]
1120 pub fn _1(self) -> &'a mut W {
1121 self.variant(M4REW::_1)
1122 }
1123 #[doc = r" Sets the field bit"]
1124 pub fn set_bit(self) -> &'a mut W {
1125 self.bit(true)
1126 }
1127 #[doc = r" Clears the field bit"]
1128 pub fn clear_bit(self) -> &'a mut W {
1129 self.bit(false)
1130 }
1131 #[doc = r" Writes raw bits to the field"]
1132 #[inline]
1133 pub fn bit(self, value: bool) -> &'a mut W {
1134 const MASK: bool = true;
1135 const OFFSET: u8 = 25;
1136 self.w.bits &= !((MASK as u32) << OFFSET);
1137 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1138 self.w
1139 }
1140}
1141#[doc = "Values that can be written to the field `M5WE`"]
1142pub enum M5WEW {
1143 #[doc = "Bus master 5 writes terminate with an access error and the write is not performed"]
1144 _0,
1145 #[doc = "Bus master 5 writes allowed"]
1146 _1,
1147}
1148impl M5WEW {
1149 #[allow(missing_docs)]
1150 #[doc(hidden)]
1151 #[inline]
1152 pub fn _bits(&self) -> bool {
1153 match *self {
1154 M5WEW::_0 => false,
1155 M5WEW::_1 => true,
1156 }
1157 }
1158}
1159#[doc = r" Proxy"]
1160pub struct _M5WEW<'a> {
1161 w: &'a mut W,
1162}
1163impl<'a> _M5WEW<'a> {
1164 #[doc = r" Writes `variant` to the field"]
1165 #[inline]
1166 pub fn variant(self, variant: M5WEW) -> &'a mut W {
1167 {
1168 self.bit(variant._bits())
1169 }
1170 }
1171 #[doc = "Bus master 5 writes terminate with an access error and the write is not performed"]
1172 #[inline]
1173 pub fn _0(self) -> &'a mut W {
1174 self.variant(M5WEW::_0)
1175 }
1176 #[doc = "Bus master 5 writes allowed"]
1177 #[inline]
1178 pub fn _1(self) -> &'a mut W {
1179 self.variant(M5WEW::_1)
1180 }
1181 #[doc = r" Sets the field bit"]
1182 pub fn set_bit(self) -> &'a mut W {
1183 self.bit(true)
1184 }
1185 #[doc = r" Clears the field bit"]
1186 pub fn clear_bit(self) -> &'a mut W {
1187 self.bit(false)
1188 }
1189 #[doc = r" Writes raw bits to the field"]
1190 #[inline]
1191 pub fn bit(self, value: bool) -> &'a mut W {
1192 const MASK: bool = true;
1193 const OFFSET: u8 = 26;
1194 self.w.bits &= !((MASK as u32) << OFFSET);
1195 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1196 self.w
1197 }
1198}
1199#[doc = "Values that can be written to the field `M5RE`"]
1200pub enum M5REW {
1201 #[doc = "Bus master 5 reads terminate with an access error and the read is not performed"]
1202 _0,
1203 #[doc = "Bus master 5 reads allowed"]
1204 _1,
1205}
1206impl M5REW {
1207 #[allow(missing_docs)]
1208 #[doc(hidden)]
1209 #[inline]
1210 pub fn _bits(&self) -> bool {
1211 match *self {
1212 M5REW::_0 => false,
1213 M5REW::_1 => true,
1214 }
1215 }
1216}
1217#[doc = r" Proxy"]
1218pub struct _M5REW<'a> {
1219 w: &'a mut W,
1220}
1221impl<'a> _M5REW<'a> {
1222 #[doc = r" Writes `variant` to the field"]
1223 #[inline]
1224 pub fn variant(self, variant: M5REW) -> &'a mut W {
1225 {
1226 self.bit(variant._bits())
1227 }
1228 }
1229 #[doc = "Bus master 5 reads terminate with an access error and the read is not performed"]
1230 #[inline]
1231 pub fn _0(self) -> &'a mut W {
1232 self.variant(M5REW::_0)
1233 }
1234 #[doc = "Bus master 5 reads allowed"]
1235 #[inline]
1236 pub fn _1(self) -> &'a mut W {
1237 self.variant(M5REW::_1)
1238 }
1239 #[doc = r" Sets the field bit"]
1240 pub fn set_bit(self) -> &'a mut W {
1241 self.bit(true)
1242 }
1243 #[doc = r" Clears the field bit"]
1244 pub fn clear_bit(self) -> &'a mut W {
1245 self.bit(false)
1246 }
1247 #[doc = r" Writes raw bits to the field"]
1248 #[inline]
1249 pub fn bit(self, value: bool) -> &'a mut W {
1250 const MASK: bool = true;
1251 const OFFSET: u8 = 27;
1252 self.w.bits &= !((MASK as u32) << OFFSET);
1253 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1254 self.w
1255 }
1256}
1257#[doc = "Values that can be written to the field `M6WE`"]
1258pub enum M6WEW {
1259 #[doc = "Bus master 6 writes terminate with an access error and the write is not performed"]
1260 _0,
1261 #[doc = "Bus master 6 writes allowed"]
1262 _1,
1263}
1264impl M6WEW {
1265 #[allow(missing_docs)]
1266 #[doc(hidden)]
1267 #[inline]
1268 pub fn _bits(&self) -> bool {
1269 match *self {
1270 M6WEW::_0 => false,
1271 M6WEW::_1 => true,
1272 }
1273 }
1274}
1275#[doc = r" Proxy"]
1276pub struct _M6WEW<'a> {
1277 w: &'a mut W,
1278}
1279impl<'a> _M6WEW<'a> {
1280 #[doc = r" Writes `variant` to the field"]
1281 #[inline]
1282 pub fn variant(self, variant: M6WEW) -> &'a mut W {
1283 {
1284 self.bit(variant._bits())
1285 }
1286 }
1287 #[doc = "Bus master 6 writes terminate with an access error and the write is not performed"]
1288 #[inline]
1289 pub fn _0(self) -> &'a mut W {
1290 self.variant(M6WEW::_0)
1291 }
1292 #[doc = "Bus master 6 writes allowed"]
1293 #[inline]
1294 pub fn _1(self) -> &'a mut W {
1295 self.variant(M6WEW::_1)
1296 }
1297 #[doc = r" Sets the field bit"]
1298 pub fn set_bit(self) -> &'a mut W {
1299 self.bit(true)
1300 }
1301 #[doc = r" Clears the field bit"]
1302 pub fn clear_bit(self) -> &'a mut W {
1303 self.bit(false)
1304 }
1305 #[doc = r" Writes raw bits to the field"]
1306 #[inline]
1307 pub fn bit(self, value: bool) -> &'a mut W {
1308 const MASK: bool = true;
1309 const OFFSET: u8 = 28;
1310 self.w.bits &= !((MASK as u32) << OFFSET);
1311 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1312 self.w
1313 }
1314}
1315#[doc = "Values that can be written to the field `M6RE`"]
1316pub enum M6REW {
1317 #[doc = "Bus master 6 reads terminate with an access error and the read is not performed"]
1318 _0,
1319 #[doc = "Bus master 6 reads allowed"]
1320 _1,
1321}
1322impl M6REW {
1323 #[allow(missing_docs)]
1324 #[doc(hidden)]
1325 #[inline]
1326 pub fn _bits(&self) -> bool {
1327 match *self {
1328 M6REW::_0 => false,
1329 M6REW::_1 => true,
1330 }
1331 }
1332}
1333#[doc = r" Proxy"]
1334pub struct _M6REW<'a> {
1335 w: &'a mut W,
1336}
1337impl<'a> _M6REW<'a> {
1338 #[doc = r" Writes `variant` to the field"]
1339 #[inline]
1340 pub fn variant(self, variant: M6REW) -> &'a mut W {
1341 {
1342 self.bit(variant._bits())
1343 }
1344 }
1345 #[doc = "Bus master 6 reads terminate with an access error and the read is not performed"]
1346 #[inline]
1347 pub fn _0(self) -> &'a mut W {
1348 self.variant(M6REW::_0)
1349 }
1350 #[doc = "Bus master 6 reads allowed"]
1351 #[inline]
1352 pub fn _1(self) -> &'a mut W {
1353 self.variant(M6REW::_1)
1354 }
1355 #[doc = r" Sets the field bit"]
1356 pub fn set_bit(self) -> &'a mut W {
1357 self.bit(true)
1358 }
1359 #[doc = r" Clears the field bit"]
1360 pub fn clear_bit(self) -> &'a mut W {
1361 self.bit(false)
1362 }
1363 #[doc = r" Writes raw bits to the field"]
1364 #[inline]
1365 pub fn bit(self, value: bool) -> &'a mut W {
1366 const MASK: bool = true;
1367 const OFFSET: u8 = 29;
1368 self.w.bits &= !((MASK as u32) << OFFSET);
1369 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1370 self.w
1371 }
1372}
1373#[doc = "Values that can be written to the field `M7WE`"]
1374pub enum M7WEW {
1375 #[doc = "Bus master 7 writes terminate with an access error and the write is not performed"]
1376 _0,
1377 #[doc = "Bus master 7 writes allowed"]
1378 _1,
1379}
1380impl M7WEW {
1381 #[allow(missing_docs)]
1382 #[doc(hidden)]
1383 #[inline]
1384 pub fn _bits(&self) -> bool {
1385 match *self {
1386 M7WEW::_0 => false,
1387 M7WEW::_1 => true,
1388 }
1389 }
1390}
1391#[doc = r" Proxy"]
1392pub struct _M7WEW<'a> {
1393 w: &'a mut W,
1394}
1395impl<'a> _M7WEW<'a> {
1396 #[doc = r" Writes `variant` to the field"]
1397 #[inline]
1398 pub fn variant(self, variant: M7WEW) -> &'a mut W {
1399 {
1400 self.bit(variant._bits())
1401 }
1402 }
1403 #[doc = "Bus master 7 writes terminate with an access error and the write is not performed"]
1404 #[inline]
1405 pub fn _0(self) -> &'a mut W {
1406 self.variant(M7WEW::_0)
1407 }
1408 #[doc = "Bus master 7 writes allowed"]
1409 #[inline]
1410 pub fn _1(self) -> &'a mut W {
1411 self.variant(M7WEW::_1)
1412 }
1413 #[doc = r" Sets the field bit"]
1414 pub fn set_bit(self) -> &'a mut W {
1415 self.bit(true)
1416 }
1417 #[doc = r" Clears the field bit"]
1418 pub fn clear_bit(self) -> &'a mut W {
1419 self.bit(false)
1420 }
1421 #[doc = r" Writes raw bits to the field"]
1422 #[inline]
1423 pub fn bit(self, value: bool) -> &'a mut W {
1424 const MASK: bool = true;
1425 const OFFSET: u8 = 30;
1426 self.w.bits &= !((MASK as u32) << OFFSET);
1427 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1428 self.w
1429 }
1430}
1431#[doc = "Values that can be written to the field `M7RE`"]
1432pub enum M7REW {
1433 #[doc = "Bus master 7 reads terminate with an access error and the read is not performed"]
1434 _0,
1435 #[doc = "Bus master 7 reads allowed"]
1436 _1,
1437}
1438impl M7REW {
1439 #[allow(missing_docs)]
1440 #[doc(hidden)]
1441 #[inline]
1442 pub fn _bits(&self) -> bool {
1443 match *self {
1444 M7REW::_0 => false,
1445 M7REW::_1 => true,
1446 }
1447 }
1448}
1449#[doc = r" Proxy"]
1450pub struct _M7REW<'a> {
1451 w: &'a mut W,
1452}
1453impl<'a> _M7REW<'a> {
1454 #[doc = r" Writes `variant` to the field"]
1455 #[inline]
1456 pub fn variant(self, variant: M7REW) -> &'a mut W {
1457 {
1458 self.bit(variant._bits())
1459 }
1460 }
1461 #[doc = "Bus master 7 reads terminate with an access error and the read is not performed"]
1462 #[inline]
1463 pub fn _0(self) -> &'a mut W {
1464 self.variant(M7REW::_0)
1465 }
1466 #[doc = "Bus master 7 reads allowed"]
1467 #[inline]
1468 pub fn _1(self) -> &'a mut W {
1469 self.variant(M7REW::_1)
1470 }
1471 #[doc = r" Sets the field bit"]
1472 pub fn set_bit(self) -> &'a mut W {
1473 self.bit(true)
1474 }
1475 #[doc = r" Clears the field bit"]
1476 pub fn clear_bit(self) -> &'a mut W {
1477 self.bit(false)
1478 }
1479 #[doc = r" Writes raw bits to the field"]
1480 #[inline]
1481 pub fn bit(self, value: bool) -> &'a mut W {
1482 const MASK: bool = true;
1483 const OFFSET: u8 = 31;
1484 self.w.bits &= !((MASK as u32) << OFFSET);
1485 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1486 self.w
1487 }
1488}
1489impl R {
1490 #[doc = r" Value of the register as raw bits"]
1491 #[inline]
1492 pub fn bits(&self) -> u32 {
1493 self.bits
1494 }
1495 #[doc = "Bits 0:2 - Bus Master 0 User Mode Access Control"]
1496 #[inline]
1497 pub fn m0um(&self) -> M0UMR {
1498 let bits = {
1499 const MASK: u8 = 7;
1500 const OFFSET: u8 = 0;
1501 ((self.bits >> OFFSET) & MASK as u32) as u8
1502 };
1503 M0UMR { bits }
1504 }
1505 #[doc = "Bits 3:4 - Bus Master 0 Supervisor Mode Access Control"]
1506 #[inline]
1507 pub fn m0sm(&self) -> M0SMR {
1508 let bits = {
1509 const MASK: u8 = 3;
1510 const OFFSET: u8 = 3;
1511 ((self.bits >> OFFSET) & MASK as u32) as u8
1512 };
1513 M0SMR { bits }
1514 }
1515 #[doc = "Bit 5 - Bus Master 0 Process Identifier enable"]
1516 #[inline]
1517 pub fn m0pe(&self) -> M0PER {
1518 let bits = {
1519 const MASK: bool = true;
1520 const OFFSET: u8 = 5;
1521 ((self.bits >> OFFSET) & MASK as u32) != 0
1522 };
1523 M0PER { bits }
1524 }
1525 #[doc = "Bits 6:8 - Bus Master 1 User Mode Access Control"]
1526 #[inline]
1527 pub fn m1um(&self) -> M1UMR {
1528 let bits = {
1529 const MASK: u8 = 7;
1530 const OFFSET: u8 = 6;
1531 ((self.bits >> OFFSET) & MASK as u32) as u8
1532 };
1533 M1UMR { bits }
1534 }
1535 #[doc = "Bits 9:10 - Bus Master 1 Supervisor Mode Access Control"]
1536 #[inline]
1537 pub fn m1sm(&self) -> M1SMR {
1538 let bits = {
1539 const MASK: u8 = 3;
1540 const OFFSET: u8 = 9;
1541 ((self.bits >> OFFSET) & MASK as u32) as u8
1542 };
1543 M1SMR { bits }
1544 }
1545 #[doc = "Bit 11 - Bus Master 1 Process Identifier enable"]
1546 #[inline]
1547 pub fn m1pe(&self) -> M1PER {
1548 let bits = {
1549 const MASK: bool = true;
1550 const OFFSET: u8 = 11;
1551 ((self.bits >> OFFSET) & MASK as u32) != 0
1552 };
1553 M1PER { bits }
1554 }
1555 #[doc = "Bits 12:14 - Bus Master 2 User Mode Access control"]
1556 #[inline]
1557 pub fn m2um(&self) -> M2UMR {
1558 let bits = {
1559 const MASK: u8 = 7;
1560 const OFFSET: u8 = 12;
1561 ((self.bits >> OFFSET) & MASK as u32) as u8
1562 };
1563 M2UMR { bits }
1564 }
1565 #[doc = "Bits 15:16 - Bus Master 2 Supervisor Mode Access Control"]
1566 #[inline]
1567 pub fn m2sm(&self) -> M2SMR {
1568 let bits = {
1569 const MASK: u8 = 3;
1570 const OFFSET: u8 = 15;
1571 ((self.bits >> OFFSET) & MASK as u32) as u8
1572 };
1573 M2SMR { bits }
1574 }
1575 #[doc = "Bit 17 - Bus Master 2 Process Identifier Enable"]
1576 #[inline]
1577 pub fn m2pe(&self) -> M2PER {
1578 let bits = {
1579 const MASK: bool = true;
1580 const OFFSET: u8 = 17;
1581 ((self.bits >> OFFSET) & MASK as u32) != 0
1582 };
1583 M2PER { bits }
1584 }
1585 #[doc = "Bits 18:20 - Bus Master 3 User Mode Access Control"]
1586 #[inline]
1587 pub fn m3um(&self) -> M3UMR {
1588 M3UMR::_from({
1589 const MASK: u8 = 7;
1590 const OFFSET: u8 = 18;
1591 ((self.bits >> OFFSET) & MASK as u32) as u8
1592 })
1593 }
1594 #[doc = "Bits 21:22 - Bus Master 3 Supervisor Mode Access Control"]
1595 #[inline]
1596 pub fn m3sm(&self) -> M3SMR {
1597 M3SMR::_from({
1598 const MASK: u8 = 3;
1599 const OFFSET: u8 = 21;
1600 ((self.bits >> OFFSET) & MASK as u32) as u8
1601 })
1602 }
1603 #[doc = "Bit 23 - Bus Master 3 Process Identifier Enable"]
1604 #[inline]
1605 pub fn m3pe(&self) -> M3PER {
1606 M3PER::_from({
1607 const MASK: bool = true;
1608 const OFFSET: u8 = 23;
1609 ((self.bits >> OFFSET) & MASK as u32) != 0
1610 })
1611 }
1612 #[doc = "Bit 24 - Bus Master 4 Write Enable"]
1613 #[inline]
1614 pub fn m4we(&self) -> M4WER {
1615 M4WER::_from({
1616 const MASK: bool = true;
1617 const OFFSET: u8 = 24;
1618 ((self.bits >> OFFSET) & MASK as u32) != 0
1619 })
1620 }
1621 #[doc = "Bit 25 - Bus Master 4 Read Enable"]
1622 #[inline]
1623 pub fn m4re(&self) -> M4RER {
1624 M4RER::_from({
1625 const MASK: bool = true;
1626 const OFFSET: u8 = 25;
1627 ((self.bits >> OFFSET) & MASK as u32) != 0
1628 })
1629 }
1630 #[doc = "Bit 26 - Bus Master 5 Write Enable"]
1631 #[inline]
1632 pub fn m5we(&self) -> M5WER {
1633 M5WER::_from({
1634 const MASK: bool = true;
1635 const OFFSET: u8 = 26;
1636 ((self.bits >> OFFSET) & MASK as u32) != 0
1637 })
1638 }
1639 #[doc = "Bit 27 - Bus Master 5 Read Enable"]
1640 #[inline]
1641 pub fn m5re(&self) -> M5RER {
1642 M5RER::_from({
1643 const MASK: bool = true;
1644 const OFFSET: u8 = 27;
1645 ((self.bits >> OFFSET) & MASK as u32) != 0
1646 })
1647 }
1648 #[doc = "Bit 28 - Bus Master 6 Write Enable"]
1649 #[inline]
1650 pub fn m6we(&self) -> M6WER {
1651 M6WER::_from({
1652 const MASK: bool = true;
1653 const OFFSET: u8 = 28;
1654 ((self.bits >> OFFSET) & MASK as u32) != 0
1655 })
1656 }
1657 #[doc = "Bit 29 - Bus Master 6 Read Enable"]
1658 #[inline]
1659 pub fn m6re(&self) -> M6RER {
1660 M6RER::_from({
1661 const MASK: bool = true;
1662 const OFFSET: u8 = 29;
1663 ((self.bits >> OFFSET) & MASK as u32) != 0
1664 })
1665 }
1666 #[doc = "Bit 30 - Bus Master 7 Write Enable"]
1667 #[inline]
1668 pub fn m7we(&self) -> M7WER {
1669 M7WER::_from({
1670 const MASK: bool = true;
1671 const OFFSET: u8 = 30;
1672 ((self.bits >> OFFSET) & MASK as u32) != 0
1673 })
1674 }
1675 #[doc = "Bit 31 - Bus Master 7 Read Enable"]
1676 #[inline]
1677 pub fn m7re(&self) -> M7RER {
1678 M7RER::_from({
1679 const MASK: bool = true;
1680 const OFFSET: u8 = 31;
1681 ((self.bits >> OFFSET) & MASK as u32) != 0
1682 })
1683 }
1684}
1685impl W {
1686 #[doc = r" Reset value of the register"]
1687 #[inline]
1688 pub fn reset_value() -> W {
1689 W { bits: 6420447 }
1690 }
1691 #[doc = r" Writes raw bits to the register"]
1692 #[inline]
1693 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1694 self.bits = bits;
1695 self
1696 }
1697 #[doc = "Bits 0:2 - Bus Master 0 User Mode Access Control"]
1698 #[inline]
1699 pub fn m0um(&mut self) -> _M0UMW {
1700 _M0UMW { w: self }
1701 }
1702 #[doc = "Bits 3:4 - Bus Master 0 Supervisor Mode Access Control"]
1703 #[inline]
1704 pub fn m0sm(&mut self) -> _M0SMW {
1705 _M0SMW { w: self }
1706 }
1707 #[doc = "Bit 5 - Bus Master 0 Process Identifier enable"]
1708 #[inline]
1709 pub fn m0pe(&mut self) -> _M0PEW {
1710 _M0PEW { w: self }
1711 }
1712 #[doc = "Bits 6:8 - Bus Master 1 User Mode Access Control"]
1713 #[inline]
1714 pub fn m1um(&mut self) -> _M1UMW {
1715 _M1UMW { w: self }
1716 }
1717 #[doc = "Bits 9:10 - Bus Master 1 Supervisor Mode Access Control"]
1718 #[inline]
1719 pub fn m1sm(&mut self) -> _M1SMW {
1720 _M1SMW { w: self }
1721 }
1722 #[doc = "Bit 11 - Bus Master 1 Process Identifier enable"]
1723 #[inline]
1724 pub fn m1pe(&mut self) -> _M1PEW {
1725 _M1PEW { w: self }
1726 }
1727 #[doc = "Bits 12:14 - Bus Master 2 User Mode Access control"]
1728 #[inline]
1729 pub fn m2um(&mut self) -> _M2UMW {
1730 _M2UMW { w: self }
1731 }
1732 #[doc = "Bits 15:16 - Bus Master 2 Supervisor Mode Access Control"]
1733 #[inline]
1734 pub fn m2sm(&mut self) -> _M2SMW {
1735 _M2SMW { w: self }
1736 }
1737 #[doc = "Bit 17 - Bus Master 2 Process Identifier Enable"]
1738 #[inline]
1739 pub fn m2pe(&mut self) -> _M2PEW {
1740 _M2PEW { w: self }
1741 }
1742 #[doc = "Bits 18:20 - Bus Master 3 User Mode Access Control"]
1743 #[inline]
1744 pub fn m3um(&mut self) -> _M3UMW {
1745 _M3UMW { w: self }
1746 }
1747 #[doc = "Bits 21:22 - Bus Master 3 Supervisor Mode Access Control"]
1748 #[inline]
1749 pub fn m3sm(&mut self) -> _M3SMW {
1750 _M3SMW { w: self }
1751 }
1752 #[doc = "Bit 23 - Bus Master 3 Process Identifier Enable"]
1753 #[inline]
1754 pub fn m3pe(&mut self) -> _M3PEW {
1755 _M3PEW { w: self }
1756 }
1757 #[doc = "Bit 24 - Bus Master 4 Write Enable"]
1758 #[inline]
1759 pub fn m4we(&mut self) -> _M4WEW {
1760 _M4WEW { w: self }
1761 }
1762 #[doc = "Bit 25 - Bus Master 4 Read Enable"]
1763 #[inline]
1764 pub fn m4re(&mut self) -> _M4REW {
1765 _M4REW { w: self }
1766 }
1767 #[doc = "Bit 26 - Bus Master 5 Write Enable"]
1768 #[inline]
1769 pub fn m5we(&mut self) -> _M5WEW {
1770 _M5WEW { w: self }
1771 }
1772 #[doc = "Bit 27 - Bus Master 5 Read Enable"]
1773 #[inline]
1774 pub fn m5re(&mut self) -> _M5REW {
1775 _M5REW { w: self }
1776 }
1777 #[doc = "Bit 28 - Bus Master 6 Write Enable"]
1778 #[inline]
1779 pub fn m6we(&mut self) -> _M6WEW {
1780 _M6WEW { w: self }
1781 }
1782 #[doc = "Bit 29 - Bus Master 6 Read Enable"]
1783 #[inline]
1784 pub fn m6re(&mut self) -> _M6REW {
1785 _M6REW { w: self }
1786 }
1787 #[doc = "Bit 30 - Bus Master 7 Write Enable"]
1788 #[inline]
1789 pub fn m7we(&mut self) -> _M7WEW {
1790 _M7WEW { w: self }
1791 }
1792 #[doc = "Bit 31 - Bus Master 7 Read Enable"]
1793 #[inline]
1794 pub fn m7re(&mut self) -> _M7REW {
1795 _M7REW { w: self }
1796 }
1797}