1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::SOPT8 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `FTM0SYNCBIT`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum FTM0SYNCBITR {
48 #[doc = "No effect"]
49 _0,
50 #[doc = "Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert."]
51 _1,
52}
53impl FTM0SYNCBITR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 FTM0SYNCBITR::_0 => false,
69 FTM0SYNCBITR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> FTM0SYNCBITR {
76 match value {
77 false => FTM0SYNCBITR::_0,
78 true => FTM0SYNCBITR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == FTM0SYNCBITR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == FTM0SYNCBITR::_1
90 }
91}
92#[doc = "Possible values of the field `FTM1SYNCBIT`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum FTM1SYNCBITR {
95 #[doc = "No effect."]
96 _0,
97 #[doc = "Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert."]
98 _1,
99}
100impl FTM1SYNCBITR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 FTM1SYNCBITR::_0 => false,
116 FTM1SYNCBITR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> FTM1SYNCBITR {
123 match value {
124 false => FTM1SYNCBITR::_0,
125 true => FTM1SYNCBITR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == FTM1SYNCBITR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == FTM1SYNCBITR::_1
137 }
138}
139#[doc = "Possible values of the field `FTM2SYNCBIT`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum FTM2SYNCBITR {
142 #[doc = "No effect."]
143 _0,
144 #[doc = "Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert."]
145 _1,
146}
147impl FTM2SYNCBITR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 FTM2SYNCBITR::_0 => false,
163 FTM2SYNCBITR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> FTM2SYNCBITR {
170 match value {
171 false => FTM2SYNCBITR::_0,
172 true => FTM2SYNCBITR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == FTM2SYNCBITR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == FTM2SYNCBITR::_1
184 }
185}
186#[doc = "Possible values of the field `FTM3SYNCBIT`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum FTM3SYNCBITR {
189 #[doc = "No effect."]
190 _0,
191 #[doc = "Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert."]
192 _1,
193}
194impl FTM3SYNCBITR {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 FTM3SYNCBITR::_0 => false,
210 FTM3SYNCBITR::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> FTM3SYNCBITR {
217 match value {
218 false => FTM3SYNCBITR::_0,
219 true => FTM3SYNCBITR::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == FTM3SYNCBITR::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == FTM3SYNCBITR::_1
231 }
232}
233#[doc = "Possible values of the field `FTM0OCH0SRC`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum FTM0OCH0SRCR {
236 #[doc = "FTM0_CH0 pin is output of FTM0 channel 0 output"]
237 _0,
238 #[doc = "FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output"]
239 _1,
240}
241impl FTM0OCH0SRCR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 FTM0OCH0SRCR::_0 => false,
257 FTM0OCH0SRCR::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> FTM0OCH0SRCR {
264 match value {
265 false => FTM0OCH0SRCR::_0,
266 true => FTM0OCH0SRCR::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == FTM0OCH0SRCR::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == FTM0OCH0SRCR::_1
278 }
279}
280#[doc = "Possible values of the field `FTM0OCH1SRC`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum FTM0OCH1SRCR {
283 #[doc = "FTM0_CH1 pin is output of FTM0 channel 1 output"]
284 _0,
285 #[doc = "FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output"]
286 _1,
287}
288impl FTM0OCH1SRCR {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 FTM0OCH1SRCR::_0 => false,
304 FTM0OCH1SRCR::_1 => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> FTM0OCH1SRCR {
311 match value {
312 false => FTM0OCH1SRCR::_0,
313 true => FTM0OCH1SRCR::_1,
314 }
315 }
316 #[doc = "Checks if the value of the field is `_0`"]
317 #[inline]
318 pub fn is_0(&self) -> bool {
319 *self == FTM0OCH1SRCR::_0
320 }
321 #[doc = "Checks if the value of the field is `_1`"]
322 #[inline]
323 pub fn is_1(&self) -> bool {
324 *self == FTM0OCH1SRCR::_1
325 }
326}
327#[doc = "Possible values of the field `FTM0OCH2SRC`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum FTM0OCH2SRCR {
330 #[doc = "FTM0_CH2 pin is output of FTM0 channel 2 output"]
331 _0,
332 #[doc = "FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output"]
333 _1,
334}
335impl FTM0OCH2SRCR {
336 #[doc = r" Returns `true` if the bit is clear (0)"]
337 #[inline]
338 pub fn bit_is_clear(&self) -> bool {
339 !self.bit()
340 }
341 #[doc = r" Returns `true` if the bit is set (1)"]
342 #[inline]
343 pub fn bit_is_set(&self) -> bool {
344 self.bit()
345 }
346 #[doc = r" Value of the field as raw bits"]
347 #[inline]
348 pub fn bit(&self) -> bool {
349 match *self {
350 FTM0OCH2SRCR::_0 => false,
351 FTM0OCH2SRCR::_1 => true,
352 }
353 }
354 #[allow(missing_docs)]
355 #[doc(hidden)]
356 #[inline]
357 pub fn _from(value: bool) -> FTM0OCH2SRCR {
358 match value {
359 false => FTM0OCH2SRCR::_0,
360 true => FTM0OCH2SRCR::_1,
361 }
362 }
363 #[doc = "Checks if the value of the field is `_0`"]
364 #[inline]
365 pub fn is_0(&self) -> bool {
366 *self == FTM0OCH2SRCR::_0
367 }
368 #[doc = "Checks if the value of the field is `_1`"]
369 #[inline]
370 pub fn is_1(&self) -> bool {
371 *self == FTM0OCH2SRCR::_1
372 }
373}
374#[doc = "Possible values of the field `FTM0OCH3SRC`"]
375#[derive(Clone, Copy, Debug, PartialEq)]
376pub enum FTM0OCH3SRCR {
377 #[doc = "FTM0_CH3 pin is output of FTM0 channel 3 output"]
378 _0,
379 #[doc = "FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output"]
380 _1,
381}
382impl FTM0OCH3SRCR {
383 #[doc = r" Returns `true` if the bit is clear (0)"]
384 #[inline]
385 pub fn bit_is_clear(&self) -> bool {
386 !self.bit()
387 }
388 #[doc = r" Returns `true` if the bit is set (1)"]
389 #[inline]
390 pub fn bit_is_set(&self) -> bool {
391 self.bit()
392 }
393 #[doc = r" Value of the field as raw bits"]
394 #[inline]
395 pub fn bit(&self) -> bool {
396 match *self {
397 FTM0OCH3SRCR::_0 => false,
398 FTM0OCH3SRCR::_1 => true,
399 }
400 }
401 #[allow(missing_docs)]
402 #[doc(hidden)]
403 #[inline]
404 pub fn _from(value: bool) -> FTM0OCH3SRCR {
405 match value {
406 false => FTM0OCH3SRCR::_0,
407 true => FTM0OCH3SRCR::_1,
408 }
409 }
410 #[doc = "Checks if the value of the field is `_0`"]
411 #[inline]
412 pub fn is_0(&self) -> bool {
413 *self == FTM0OCH3SRCR::_0
414 }
415 #[doc = "Checks if the value of the field is `_1`"]
416 #[inline]
417 pub fn is_1(&self) -> bool {
418 *self == FTM0OCH3SRCR::_1
419 }
420}
421#[doc = "Possible values of the field `FTM0OCH4SRC`"]
422#[derive(Clone, Copy, Debug, PartialEq)]
423pub enum FTM0OCH4SRCR {
424 #[doc = "FTM0_CH4 pin is output of FTM0 channel 4 output"]
425 _0,
426 #[doc = "FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output"]
427 _1,
428}
429impl FTM0OCH4SRCR {
430 #[doc = r" Returns `true` if the bit is clear (0)"]
431 #[inline]
432 pub fn bit_is_clear(&self) -> bool {
433 !self.bit()
434 }
435 #[doc = r" Returns `true` if the bit is set (1)"]
436 #[inline]
437 pub fn bit_is_set(&self) -> bool {
438 self.bit()
439 }
440 #[doc = r" Value of the field as raw bits"]
441 #[inline]
442 pub fn bit(&self) -> bool {
443 match *self {
444 FTM0OCH4SRCR::_0 => false,
445 FTM0OCH4SRCR::_1 => true,
446 }
447 }
448 #[allow(missing_docs)]
449 #[doc(hidden)]
450 #[inline]
451 pub fn _from(value: bool) -> FTM0OCH4SRCR {
452 match value {
453 false => FTM0OCH4SRCR::_0,
454 true => FTM0OCH4SRCR::_1,
455 }
456 }
457 #[doc = "Checks if the value of the field is `_0`"]
458 #[inline]
459 pub fn is_0(&self) -> bool {
460 *self == FTM0OCH4SRCR::_0
461 }
462 #[doc = "Checks if the value of the field is `_1`"]
463 #[inline]
464 pub fn is_1(&self) -> bool {
465 *self == FTM0OCH4SRCR::_1
466 }
467}
468#[doc = "Possible values of the field `FTM0OCH5SRC`"]
469#[derive(Clone, Copy, Debug, PartialEq)]
470pub enum FTM0OCH5SRCR {
471 #[doc = "FTM0_CH5 pin is output of FTM0 channel 5 output"]
472 _0,
473 #[doc = "FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output"]
474 _1,
475}
476impl FTM0OCH5SRCR {
477 #[doc = r" Returns `true` if the bit is clear (0)"]
478 #[inline]
479 pub fn bit_is_clear(&self) -> bool {
480 !self.bit()
481 }
482 #[doc = r" Returns `true` if the bit is set (1)"]
483 #[inline]
484 pub fn bit_is_set(&self) -> bool {
485 self.bit()
486 }
487 #[doc = r" Value of the field as raw bits"]
488 #[inline]
489 pub fn bit(&self) -> bool {
490 match *self {
491 FTM0OCH5SRCR::_0 => false,
492 FTM0OCH5SRCR::_1 => true,
493 }
494 }
495 #[allow(missing_docs)]
496 #[doc(hidden)]
497 #[inline]
498 pub fn _from(value: bool) -> FTM0OCH5SRCR {
499 match value {
500 false => FTM0OCH5SRCR::_0,
501 true => FTM0OCH5SRCR::_1,
502 }
503 }
504 #[doc = "Checks if the value of the field is `_0`"]
505 #[inline]
506 pub fn is_0(&self) -> bool {
507 *self == FTM0OCH5SRCR::_0
508 }
509 #[doc = "Checks if the value of the field is `_1`"]
510 #[inline]
511 pub fn is_1(&self) -> bool {
512 *self == FTM0OCH5SRCR::_1
513 }
514}
515#[doc = "Possible values of the field `FTM0OCH6SRC`"]
516#[derive(Clone, Copy, Debug, PartialEq)]
517pub enum FTM0OCH6SRCR {
518 #[doc = "FTM0_CH6 pin is output of FTM0 channel 6 output"]
519 _0,
520 #[doc = "FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output"]
521 _1,
522}
523impl FTM0OCH6SRCR {
524 #[doc = r" Returns `true` if the bit is clear (0)"]
525 #[inline]
526 pub fn bit_is_clear(&self) -> bool {
527 !self.bit()
528 }
529 #[doc = r" Returns `true` if the bit is set (1)"]
530 #[inline]
531 pub fn bit_is_set(&self) -> bool {
532 self.bit()
533 }
534 #[doc = r" Value of the field as raw bits"]
535 #[inline]
536 pub fn bit(&self) -> bool {
537 match *self {
538 FTM0OCH6SRCR::_0 => false,
539 FTM0OCH6SRCR::_1 => true,
540 }
541 }
542 #[allow(missing_docs)]
543 #[doc(hidden)]
544 #[inline]
545 pub fn _from(value: bool) -> FTM0OCH6SRCR {
546 match value {
547 false => FTM0OCH6SRCR::_0,
548 true => FTM0OCH6SRCR::_1,
549 }
550 }
551 #[doc = "Checks if the value of the field is `_0`"]
552 #[inline]
553 pub fn is_0(&self) -> bool {
554 *self == FTM0OCH6SRCR::_0
555 }
556 #[doc = "Checks if the value of the field is `_1`"]
557 #[inline]
558 pub fn is_1(&self) -> bool {
559 *self == FTM0OCH6SRCR::_1
560 }
561}
562#[doc = "Possible values of the field `FTM0OCH7SRC`"]
563#[derive(Clone, Copy, Debug, PartialEq)]
564pub enum FTM0OCH7SRCR {
565 #[doc = "FTM0_CH7 pin is output of FTM0 channel 7 output"]
566 _0,
567 #[doc = "FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output"]
568 _1,
569}
570impl FTM0OCH7SRCR {
571 #[doc = r" Returns `true` if the bit is clear (0)"]
572 #[inline]
573 pub fn bit_is_clear(&self) -> bool {
574 !self.bit()
575 }
576 #[doc = r" Returns `true` if the bit is set (1)"]
577 #[inline]
578 pub fn bit_is_set(&self) -> bool {
579 self.bit()
580 }
581 #[doc = r" Value of the field as raw bits"]
582 #[inline]
583 pub fn bit(&self) -> bool {
584 match *self {
585 FTM0OCH7SRCR::_0 => false,
586 FTM0OCH7SRCR::_1 => true,
587 }
588 }
589 #[allow(missing_docs)]
590 #[doc(hidden)]
591 #[inline]
592 pub fn _from(value: bool) -> FTM0OCH7SRCR {
593 match value {
594 false => FTM0OCH7SRCR::_0,
595 true => FTM0OCH7SRCR::_1,
596 }
597 }
598 #[doc = "Checks if the value of the field is `_0`"]
599 #[inline]
600 pub fn is_0(&self) -> bool {
601 *self == FTM0OCH7SRCR::_0
602 }
603 #[doc = "Checks if the value of the field is `_1`"]
604 #[inline]
605 pub fn is_1(&self) -> bool {
606 *self == FTM0OCH7SRCR::_1
607 }
608}
609#[doc = "Possible values of the field `FTM3OCH0SRC`"]
610#[derive(Clone, Copy, Debug, PartialEq)]
611pub enum FTM3OCH0SRCR {
612 #[doc = "FTM3_CH0 pin is output of FTM3 channel 0 output"]
613 _0,
614 #[doc = "FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output."]
615 _1,
616}
617impl FTM3OCH0SRCR {
618 #[doc = r" Returns `true` if the bit is clear (0)"]
619 #[inline]
620 pub fn bit_is_clear(&self) -> bool {
621 !self.bit()
622 }
623 #[doc = r" Returns `true` if the bit is set (1)"]
624 #[inline]
625 pub fn bit_is_set(&self) -> bool {
626 self.bit()
627 }
628 #[doc = r" Value of the field as raw bits"]
629 #[inline]
630 pub fn bit(&self) -> bool {
631 match *self {
632 FTM3OCH0SRCR::_0 => false,
633 FTM3OCH0SRCR::_1 => true,
634 }
635 }
636 #[allow(missing_docs)]
637 #[doc(hidden)]
638 #[inline]
639 pub fn _from(value: bool) -> FTM3OCH0SRCR {
640 match value {
641 false => FTM3OCH0SRCR::_0,
642 true => FTM3OCH0SRCR::_1,
643 }
644 }
645 #[doc = "Checks if the value of the field is `_0`"]
646 #[inline]
647 pub fn is_0(&self) -> bool {
648 *self == FTM3OCH0SRCR::_0
649 }
650 #[doc = "Checks if the value of the field is `_1`"]
651 #[inline]
652 pub fn is_1(&self) -> bool {
653 *self == FTM3OCH0SRCR::_1
654 }
655}
656#[doc = "Possible values of the field `FTM3OCH1SRC`"]
657#[derive(Clone, Copy, Debug, PartialEq)]
658pub enum FTM3OCH1SRCR {
659 #[doc = "FTM3_CH1 pin is output of FTM3 channel 1 output"]
660 _0,
661 #[doc = "FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output."]
662 _1,
663}
664impl FTM3OCH1SRCR {
665 #[doc = r" Returns `true` if the bit is clear (0)"]
666 #[inline]
667 pub fn bit_is_clear(&self) -> bool {
668 !self.bit()
669 }
670 #[doc = r" Returns `true` if the bit is set (1)"]
671 #[inline]
672 pub fn bit_is_set(&self) -> bool {
673 self.bit()
674 }
675 #[doc = r" Value of the field as raw bits"]
676 #[inline]
677 pub fn bit(&self) -> bool {
678 match *self {
679 FTM3OCH1SRCR::_0 => false,
680 FTM3OCH1SRCR::_1 => true,
681 }
682 }
683 #[allow(missing_docs)]
684 #[doc(hidden)]
685 #[inline]
686 pub fn _from(value: bool) -> FTM3OCH1SRCR {
687 match value {
688 false => FTM3OCH1SRCR::_0,
689 true => FTM3OCH1SRCR::_1,
690 }
691 }
692 #[doc = "Checks if the value of the field is `_0`"]
693 #[inline]
694 pub fn is_0(&self) -> bool {
695 *self == FTM3OCH1SRCR::_0
696 }
697 #[doc = "Checks if the value of the field is `_1`"]
698 #[inline]
699 pub fn is_1(&self) -> bool {
700 *self == FTM3OCH1SRCR::_1
701 }
702}
703#[doc = "Possible values of the field `FTM3OCH2SRC`"]
704#[derive(Clone, Copy, Debug, PartialEq)]
705pub enum FTM3OCH2SRCR {
706 #[doc = "FTM3_CH2 pin is output of FTM3 channel 2 output"]
707 _0,
708 #[doc = "FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output."]
709 _1,
710}
711impl FTM3OCH2SRCR {
712 #[doc = r" Returns `true` if the bit is clear (0)"]
713 #[inline]
714 pub fn bit_is_clear(&self) -> bool {
715 !self.bit()
716 }
717 #[doc = r" Returns `true` if the bit is set (1)"]
718 #[inline]
719 pub fn bit_is_set(&self) -> bool {
720 self.bit()
721 }
722 #[doc = r" Value of the field as raw bits"]
723 #[inline]
724 pub fn bit(&self) -> bool {
725 match *self {
726 FTM3OCH2SRCR::_0 => false,
727 FTM3OCH2SRCR::_1 => true,
728 }
729 }
730 #[allow(missing_docs)]
731 #[doc(hidden)]
732 #[inline]
733 pub fn _from(value: bool) -> FTM3OCH2SRCR {
734 match value {
735 false => FTM3OCH2SRCR::_0,
736 true => FTM3OCH2SRCR::_1,
737 }
738 }
739 #[doc = "Checks if the value of the field is `_0`"]
740 #[inline]
741 pub fn is_0(&self) -> bool {
742 *self == FTM3OCH2SRCR::_0
743 }
744 #[doc = "Checks if the value of the field is `_1`"]
745 #[inline]
746 pub fn is_1(&self) -> bool {
747 *self == FTM3OCH2SRCR::_1
748 }
749}
750#[doc = "Possible values of the field `FTM3OCH3SRC`"]
751#[derive(Clone, Copy, Debug, PartialEq)]
752pub enum FTM3OCH3SRCR {
753 #[doc = "FTM3_CH3 pin is output of FTM3 channel 3 output"]
754 _0,
755 #[doc = "FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output."]
756 _1,
757}
758impl FTM3OCH3SRCR {
759 #[doc = r" Returns `true` if the bit is clear (0)"]
760 #[inline]
761 pub fn bit_is_clear(&self) -> bool {
762 !self.bit()
763 }
764 #[doc = r" Returns `true` if the bit is set (1)"]
765 #[inline]
766 pub fn bit_is_set(&self) -> bool {
767 self.bit()
768 }
769 #[doc = r" Value of the field as raw bits"]
770 #[inline]
771 pub fn bit(&self) -> bool {
772 match *self {
773 FTM3OCH3SRCR::_0 => false,
774 FTM3OCH3SRCR::_1 => true,
775 }
776 }
777 #[allow(missing_docs)]
778 #[doc(hidden)]
779 #[inline]
780 pub fn _from(value: bool) -> FTM3OCH3SRCR {
781 match value {
782 false => FTM3OCH3SRCR::_0,
783 true => FTM3OCH3SRCR::_1,
784 }
785 }
786 #[doc = "Checks if the value of the field is `_0`"]
787 #[inline]
788 pub fn is_0(&self) -> bool {
789 *self == FTM3OCH3SRCR::_0
790 }
791 #[doc = "Checks if the value of the field is `_1`"]
792 #[inline]
793 pub fn is_1(&self) -> bool {
794 *self == FTM3OCH3SRCR::_1
795 }
796}
797#[doc = "Possible values of the field `FTM3OCH4SRC`"]
798#[derive(Clone, Copy, Debug, PartialEq)]
799pub enum FTM3OCH4SRCR {
800 #[doc = "FTM3_CH4 pin is output of FTM3 channel 4 output"]
801 _0,
802 #[doc = "FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output."]
803 _1,
804}
805impl FTM3OCH4SRCR {
806 #[doc = r" Returns `true` if the bit is clear (0)"]
807 #[inline]
808 pub fn bit_is_clear(&self) -> bool {
809 !self.bit()
810 }
811 #[doc = r" Returns `true` if the bit is set (1)"]
812 #[inline]
813 pub fn bit_is_set(&self) -> bool {
814 self.bit()
815 }
816 #[doc = r" Value of the field as raw bits"]
817 #[inline]
818 pub fn bit(&self) -> bool {
819 match *self {
820 FTM3OCH4SRCR::_0 => false,
821 FTM3OCH4SRCR::_1 => true,
822 }
823 }
824 #[allow(missing_docs)]
825 #[doc(hidden)]
826 #[inline]
827 pub fn _from(value: bool) -> FTM3OCH4SRCR {
828 match value {
829 false => FTM3OCH4SRCR::_0,
830 true => FTM3OCH4SRCR::_1,
831 }
832 }
833 #[doc = "Checks if the value of the field is `_0`"]
834 #[inline]
835 pub fn is_0(&self) -> bool {
836 *self == FTM3OCH4SRCR::_0
837 }
838 #[doc = "Checks if the value of the field is `_1`"]
839 #[inline]
840 pub fn is_1(&self) -> bool {
841 *self == FTM3OCH4SRCR::_1
842 }
843}
844#[doc = "Possible values of the field `FTM3OCH5SRC`"]
845#[derive(Clone, Copy, Debug, PartialEq)]
846pub enum FTM3OCH5SRCR {
847 #[doc = "FTM3_CH5 pin is output of FTM3 channel 5 output"]
848 _0,
849 #[doc = "FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output."]
850 _1,
851}
852impl FTM3OCH5SRCR {
853 #[doc = r" Returns `true` if the bit is clear (0)"]
854 #[inline]
855 pub fn bit_is_clear(&self) -> bool {
856 !self.bit()
857 }
858 #[doc = r" Returns `true` if the bit is set (1)"]
859 #[inline]
860 pub fn bit_is_set(&self) -> bool {
861 self.bit()
862 }
863 #[doc = r" Value of the field as raw bits"]
864 #[inline]
865 pub fn bit(&self) -> bool {
866 match *self {
867 FTM3OCH5SRCR::_0 => false,
868 FTM3OCH5SRCR::_1 => true,
869 }
870 }
871 #[allow(missing_docs)]
872 #[doc(hidden)]
873 #[inline]
874 pub fn _from(value: bool) -> FTM3OCH5SRCR {
875 match value {
876 false => FTM3OCH5SRCR::_0,
877 true => FTM3OCH5SRCR::_1,
878 }
879 }
880 #[doc = "Checks if the value of the field is `_0`"]
881 #[inline]
882 pub fn is_0(&self) -> bool {
883 *self == FTM3OCH5SRCR::_0
884 }
885 #[doc = "Checks if the value of the field is `_1`"]
886 #[inline]
887 pub fn is_1(&self) -> bool {
888 *self == FTM3OCH5SRCR::_1
889 }
890}
891#[doc = "Possible values of the field `FTM3OCH6SRC`"]
892#[derive(Clone, Copy, Debug, PartialEq)]
893pub enum FTM3OCH6SRCR {
894 #[doc = "FTM3_CH6 pin is output of FTM3 channel 6 output"]
895 _0,
896 #[doc = "FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output."]
897 _1,
898}
899impl FTM3OCH6SRCR {
900 #[doc = r" Returns `true` if the bit is clear (0)"]
901 #[inline]
902 pub fn bit_is_clear(&self) -> bool {
903 !self.bit()
904 }
905 #[doc = r" Returns `true` if the bit is set (1)"]
906 #[inline]
907 pub fn bit_is_set(&self) -> bool {
908 self.bit()
909 }
910 #[doc = r" Value of the field as raw bits"]
911 #[inline]
912 pub fn bit(&self) -> bool {
913 match *self {
914 FTM3OCH6SRCR::_0 => false,
915 FTM3OCH6SRCR::_1 => true,
916 }
917 }
918 #[allow(missing_docs)]
919 #[doc(hidden)]
920 #[inline]
921 pub fn _from(value: bool) -> FTM3OCH6SRCR {
922 match value {
923 false => FTM3OCH6SRCR::_0,
924 true => FTM3OCH6SRCR::_1,
925 }
926 }
927 #[doc = "Checks if the value of the field is `_0`"]
928 #[inline]
929 pub fn is_0(&self) -> bool {
930 *self == FTM3OCH6SRCR::_0
931 }
932 #[doc = "Checks if the value of the field is `_1`"]
933 #[inline]
934 pub fn is_1(&self) -> bool {
935 *self == FTM3OCH6SRCR::_1
936 }
937}
938#[doc = "Possible values of the field `FTM3OCH7SRC`"]
939#[derive(Clone, Copy, Debug, PartialEq)]
940pub enum FTM3OCH7SRCR {
941 #[doc = "FTM3_CH7 pin is output of FTM3 channel 7 output"]
942 _0,
943 #[doc = "FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output."]
944 _1,
945}
946impl FTM3OCH7SRCR {
947 #[doc = r" Returns `true` if the bit is clear (0)"]
948 #[inline]
949 pub fn bit_is_clear(&self) -> bool {
950 !self.bit()
951 }
952 #[doc = r" Returns `true` if the bit is set (1)"]
953 #[inline]
954 pub fn bit_is_set(&self) -> bool {
955 self.bit()
956 }
957 #[doc = r" Value of the field as raw bits"]
958 #[inline]
959 pub fn bit(&self) -> bool {
960 match *self {
961 FTM3OCH7SRCR::_0 => false,
962 FTM3OCH7SRCR::_1 => true,
963 }
964 }
965 #[allow(missing_docs)]
966 #[doc(hidden)]
967 #[inline]
968 pub fn _from(value: bool) -> FTM3OCH7SRCR {
969 match value {
970 false => FTM3OCH7SRCR::_0,
971 true => FTM3OCH7SRCR::_1,
972 }
973 }
974 #[doc = "Checks if the value of the field is `_0`"]
975 #[inline]
976 pub fn is_0(&self) -> bool {
977 *self == FTM3OCH7SRCR::_0
978 }
979 #[doc = "Checks if the value of the field is `_1`"]
980 #[inline]
981 pub fn is_1(&self) -> bool {
982 *self == FTM3OCH7SRCR::_1
983 }
984}
985#[doc = "Values that can be written to the field `FTM0SYNCBIT`"]
986pub enum FTM0SYNCBITW {
987 #[doc = "No effect"]
988 _0,
989 #[doc = "Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert."]
990 _1,
991}
992impl FTM0SYNCBITW {
993 #[allow(missing_docs)]
994 #[doc(hidden)]
995 #[inline]
996 pub fn _bits(&self) -> bool {
997 match *self {
998 FTM0SYNCBITW::_0 => false,
999 FTM0SYNCBITW::_1 => true,
1000 }
1001 }
1002}
1003#[doc = r" Proxy"]
1004pub struct _FTM0SYNCBITW<'a> {
1005 w: &'a mut W,
1006}
1007impl<'a> _FTM0SYNCBITW<'a> {
1008 #[doc = r" Writes `variant` to the field"]
1009 #[inline]
1010 pub fn variant(self, variant: FTM0SYNCBITW) -> &'a mut W {
1011 {
1012 self.bit(variant._bits())
1013 }
1014 }
1015 #[doc = "No effect"]
1016 #[inline]
1017 pub fn _0(self) -> &'a mut W {
1018 self.variant(FTM0SYNCBITW::_0)
1019 }
1020 #[doc = "Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert."]
1021 #[inline]
1022 pub fn _1(self) -> &'a mut W {
1023 self.variant(FTM0SYNCBITW::_1)
1024 }
1025 #[doc = r" Sets the field bit"]
1026 pub fn set_bit(self) -> &'a mut W {
1027 self.bit(true)
1028 }
1029 #[doc = r" Clears the field bit"]
1030 pub fn clear_bit(self) -> &'a mut W {
1031 self.bit(false)
1032 }
1033 #[doc = r" Writes raw bits to the field"]
1034 #[inline]
1035 pub fn bit(self, value: bool) -> &'a mut W {
1036 const MASK: bool = true;
1037 const OFFSET: u8 = 0;
1038 self.w.bits &= !((MASK as u32) << OFFSET);
1039 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1040 self.w
1041 }
1042}
1043#[doc = "Values that can be written to the field `FTM1SYNCBIT`"]
1044pub enum FTM1SYNCBITW {
1045 #[doc = "No effect."]
1046 _0,
1047 #[doc = "Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert."]
1048 _1,
1049}
1050impl FTM1SYNCBITW {
1051 #[allow(missing_docs)]
1052 #[doc(hidden)]
1053 #[inline]
1054 pub fn _bits(&self) -> bool {
1055 match *self {
1056 FTM1SYNCBITW::_0 => false,
1057 FTM1SYNCBITW::_1 => true,
1058 }
1059 }
1060}
1061#[doc = r" Proxy"]
1062pub struct _FTM1SYNCBITW<'a> {
1063 w: &'a mut W,
1064}
1065impl<'a> _FTM1SYNCBITW<'a> {
1066 #[doc = r" Writes `variant` to the field"]
1067 #[inline]
1068 pub fn variant(self, variant: FTM1SYNCBITW) -> &'a mut W {
1069 {
1070 self.bit(variant._bits())
1071 }
1072 }
1073 #[doc = "No effect."]
1074 #[inline]
1075 pub fn _0(self) -> &'a mut W {
1076 self.variant(FTM1SYNCBITW::_0)
1077 }
1078 #[doc = "Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert."]
1079 #[inline]
1080 pub fn _1(self) -> &'a mut W {
1081 self.variant(FTM1SYNCBITW::_1)
1082 }
1083 #[doc = r" Sets the field bit"]
1084 pub fn set_bit(self) -> &'a mut W {
1085 self.bit(true)
1086 }
1087 #[doc = r" Clears the field bit"]
1088 pub fn clear_bit(self) -> &'a mut W {
1089 self.bit(false)
1090 }
1091 #[doc = r" Writes raw bits to the field"]
1092 #[inline]
1093 pub fn bit(self, value: bool) -> &'a mut W {
1094 const MASK: bool = true;
1095 const OFFSET: u8 = 1;
1096 self.w.bits &= !((MASK as u32) << OFFSET);
1097 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1098 self.w
1099 }
1100}
1101#[doc = "Values that can be written to the field `FTM2SYNCBIT`"]
1102pub enum FTM2SYNCBITW {
1103 #[doc = "No effect."]
1104 _0,
1105 #[doc = "Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert."]
1106 _1,
1107}
1108impl FTM2SYNCBITW {
1109 #[allow(missing_docs)]
1110 #[doc(hidden)]
1111 #[inline]
1112 pub fn _bits(&self) -> bool {
1113 match *self {
1114 FTM2SYNCBITW::_0 => false,
1115 FTM2SYNCBITW::_1 => true,
1116 }
1117 }
1118}
1119#[doc = r" Proxy"]
1120pub struct _FTM2SYNCBITW<'a> {
1121 w: &'a mut W,
1122}
1123impl<'a> _FTM2SYNCBITW<'a> {
1124 #[doc = r" Writes `variant` to the field"]
1125 #[inline]
1126 pub fn variant(self, variant: FTM2SYNCBITW) -> &'a mut W {
1127 {
1128 self.bit(variant._bits())
1129 }
1130 }
1131 #[doc = "No effect."]
1132 #[inline]
1133 pub fn _0(self) -> &'a mut W {
1134 self.variant(FTM2SYNCBITW::_0)
1135 }
1136 #[doc = "Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert."]
1137 #[inline]
1138 pub fn _1(self) -> &'a mut W {
1139 self.variant(FTM2SYNCBITW::_1)
1140 }
1141 #[doc = r" Sets the field bit"]
1142 pub fn set_bit(self) -> &'a mut W {
1143 self.bit(true)
1144 }
1145 #[doc = r" Clears the field bit"]
1146 pub fn clear_bit(self) -> &'a mut W {
1147 self.bit(false)
1148 }
1149 #[doc = r" Writes raw bits to the field"]
1150 #[inline]
1151 pub fn bit(self, value: bool) -> &'a mut W {
1152 const MASK: bool = true;
1153 const OFFSET: u8 = 2;
1154 self.w.bits &= !((MASK as u32) << OFFSET);
1155 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1156 self.w
1157 }
1158}
1159#[doc = "Values that can be written to the field `FTM3SYNCBIT`"]
1160pub enum FTM3SYNCBITW {
1161 #[doc = "No effect."]
1162 _0,
1163 #[doc = "Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert."]
1164 _1,
1165}
1166impl FTM3SYNCBITW {
1167 #[allow(missing_docs)]
1168 #[doc(hidden)]
1169 #[inline]
1170 pub fn _bits(&self) -> bool {
1171 match *self {
1172 FTM3SYNCBITW::_0 => false,
1173 FTM3SYNCBITW::_1 => true,
1174 }
1175 }
1176}
1177#[doc = r" Proxy"]
1178pub struct _FTM3SYNCBITW<'a> {
1179 w: &'a mut W,
1180}
1181impl<'a> _FTM3SYNCBITW<'a> {
1182 #[doc = r" Writes `variant` to the field"]
1183 #[inline]
1184 pub fn variant(self, variant: FTM3SYNCBITW) -> &'a mut W {
1185 {
1186 self.bit(variant._bits())
1187 }
1188 }
1189 #[doc = "No effect."]
1190 #[inline]
1191 pub fn _0(self) -> &'a mut W {
1192 self.variant(FTM3SYNCBITW::_0)
1193 }
1194 #[doc = "Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert."]
1195 #[inline]
1196 pub fn _1(self) -> &'a mut W {
1197 self.variant(FTM3SYNCBITW::_1)
1198 }
1199 #[doc = r" Sets the field bit"]
1200 pub fn set_bit(self) -> &'a mut W {
1201 self.bit(true)
1202 }
1203 #[doc = r" Clears the field bit"]
1204 pub fn clear_bit(self) -> &'a mut W {
1205 self.bit(false)
1206 }
1207 #[doc = r" Writes raw bits to the field"]
1208 #[inline]
1209 pub fn bit(self, value: bool) -> &'a mut W {
1210 const MASK: bool = true;
1211 const OFFSET: u8 = 3;
1212 self.w.bits &= !((MASK as u32) << OFFSET);
1213 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1214 self.w
1215 }
1216}
1217#[doc = "Values that can be written to the field `FTM0OCH0SRC`"]
1218pub enum FTM0OCH0SRCW {
1219 #[doc = "FTM0_CH0 pin is output of FTM0 channel 0 output"]
1220 _0,
1221 #[doc = "FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output"]
1222 _1,
1223}
1224impl FTM0OCH0SRCW {
1225 #[allow(missing_docs)]
1226 #[doc(hidden)]
1227 #[inline]
1228 pub fn _bits(&self) -> bool {
1229 match *self {
1230 FTM0OCH0SRCW::_0 => false,
1231 FTM0OCH0SRCW::_1 => true,
1232 }
1233 }
1234}
1235#[doc = r" Proxy"]
1236pub struct _FTM0OCH0SRCW<'a> {
1237 w: &'a mut W,
1238}
1239impl<'a> _FTM0OCH0SRCW<'a> {
1240 #[doc = r" Writes `variant` to the field"]
1241 #[inline]
1242 pub fn variant(self, variant: FTM0OCH0SRCW) -> &'a mut W {
1243 {
1244 self.bit(variant._bits())
1245 }
1246 }
1247 #[doc = "FTM0_CH0 pin is output of FTM0 channel 0 output"]
1248 #[inline]
1249 pub fn _0(self) -> &'a mut W {
1250 self.variant(FTM0OCH0SRCW::_0)
1251 }
1252 #[doc = "FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output"]
1253 #[inline]
1254 pub fn _1(self) -> &'a mut W {
1255 self.variant(FTM0OCH0SRCW::_1)
1256 }
1257 #[doc = r" Sets the field bit"]
1258 pub fn set_bit(self) -> &'a mut W {
1259 self.bit(true)
1260 }
1261 #[doc = r" Clears the field bit"]
1262 pub fn clear_bit(self) -> &'a mut W {
1263 self.bit(false)
1264 }
1265 #[doc = r" Writes raw bits to the field"]
1266 #[inline]
1267 pub fn bit(self, value: bool) -> &'a mut W {
1268 const MASK: bool = true;
1269 const OFFSET: u8 = 16;
1270 self.w.bits &= !((MASK as u32) << OFFSET);
1271 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1272 self.w
1273 }
1274}
1275#[doc = "Values that can be written to the field `FTM0OCH1SRC`"]
1276pub enum FTM0OCH1SRCW {
1277 #[doc = "FTM0_CH1 pin is output of FTM0 channel 1 output"]
1278 _0,
1279 #[doc = "FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output"]
1280 _1,
1281}
1282impl FTM0OCH1SRCW {
1283 #[allow(missing_docs)]
1284 #[doc(hidden)]
1285 #[inline]
1286 pub fn _bits(&self) -> bool {
1287 match *self {
1288 FTM0OCH1SRCW::_0 => false,
1289 FTM0OCH1SRCW::_1 => true,
1290 }
1291 }
1292}
1293#[doc = r" Proxy"]
1294pub struct _FTM0OCH1SRCW<'a> {
1295 w: &'a mut W,
1296}
1297impl<'a> _FTM0OCH1SRCW<'a> {
1298 #[doc = r" Writes `variant` to the field"]
1299 #[inline]
1300 pub fn variant(self, variant: FTM0OCH1SRCW) -> &'a mut W {
1301 {
1302 self.bit(variant._bits())
1303 }
1304 }
1305 #[doc = "FTM0_CH1 pin is output of FTM0 channel 1 output"]
1306 #[inline]
1307 pub fn _0(self) -> &'a mut W {
1308 self.variant(FTM0OCH1SRCW::_0)
1309 }
1310 #[doc = "FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output"]
1311 #[inline]
1312 pub fn _1(self) -> &'a mut W {
1313 self.variant(FTM0OCH1SRCW::_1)
1314 }
1315 #[doc = r" Sets the field bit"]
1316 pub fn set_bit(self) -> &'a mut W {
1317 self.bit(true)
1318 }
1319 #[doc = r" Clears the field bit"]
1320 pub fn clear_bit(self) -> &'a mut W {
1321 self.bit(false)
1322 }
1323 #[doc = r" Writes raw bits to the field"]
1324 #[inline]
1325 pub fn bit(self, value: bool) -> &'a mut W {
1326 const MASK: bool = true;
1327 const OFFSET: u8 = 17;
1328 self.w.bits &= !((MASK as u32) << OFFSET);
1329 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1330 self.w
1331 }
1332}
1333#[doc = "Values that can be written to the field `FTM0OCH2SRC`"]
1334pub enum FTM0OCH2SRCW {
1335 #[doc = "FTM0_CH2 pin is output of FTM0 channel 2 output"]
1336 _0,
1337 #[doc = "FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output"]
1338 _1,
1339}
1340impl FTM0OCH2SRCW {
1341 #[allow(missing_docs)]
1342 #[doc(hidden)]
1343 #[inline]
1344 pub fn _bits(&self) -> bool {
1345 match *self {
1346 FTM0OCH2SRCW::_0 => false,
1347 FTM0OCH2SRCW::_1 => true,
1348 }
1349 }
1350}
1351#[doc = r" Proxy"]
1352pub struct _FTM0OCH2SRCW<'a> {
1353 w: &'a mut W,
1354}
1355impl<'a> _FTM0OCH2SRCW<'a> {
1356 #[doc = r" Writes `variant` to the field"]
1357 #[inline]
1358 pub fn variant(self, variant: FTM0OCH2SRCW) -> &'a mut W {
1359 {
1360 self.bit(variant._bits())
1361 }
1362 }
1363 #[doc = "FTM0_CH2 pin is output of FTM0 channel 2 output"]
1364 #[inline]
1365 pub fn _0(self) -> &'a mut W {
1366 self.variant(FTM0OCH2SRCW::_0)
1367 }
1368 #[doc = "FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output"]
1369 #[inline]
1370 pub fn _1(self) -> &'a mut W {
1371 self.variant(FTM0OCH2SRCW::_1)
1372 }
1373 #[doc = r" Sets the field bit"]
1374 pub fn set_bit(self) -> &'a mut W {
1375 self.bit(true)
1376 }
1377 #[doc = r" Clears the field bit"]
1378 pub fn clear_bit(self) -> &'a mut W {
1379 self.bit(false)
1380 }
1381 #[doc = r" Writes raw bits to the field"]
1382 #[inline]
1383 pub fn bit(self, value: bool) -> &'a mut W {
1384 const MASK: bool = true;
1385 const OFFSET: u8 = 18;
1386 self.w.bits &= !((MASK as u32) << OFFSET);
1387 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1388 self.w
1389 }
1390}
1391#[doc = "Values that can be written to the field `FTM0OCH3SRC`"]
1392pub enum FTM0OCH3SRCW {
1393 #[doc = "FTM0_CH3 pin is output of FTM0 channel 3 output"]
1394 _0,
1395 #[doc = "FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output"]
1396 _1,
1397}
1398impl FTM0OCH3SRCW {
1399 #[allow(missing_docs)]
1400 #[doc(hidden)]
1401 #[inline]
1402 pub fn _bits(&self) -> bool {
1403 match *self {
1404 FTM0OCH3SRCW::_0 => false,
1405 FTM0OCH3SRCW::_1 => true,
1406 }
1407 }
1408}
1409#[doc = r" Proxy"]
1410pub struct _FTM0OCH3SRCW<'a> {
1411 w: &'a mut W,
1412}
1413impl<'a> _FTM0OCH3SRCW<'a> {
1414 #[doc = r" Writes `variant` to the field"]
1415 #[inline]
1416 pub fn variant(self, variant: FTM0OCH3SRCW) -> &'a mut W {
1417 {
1418 self.bit(variant._bits())
1419 }
1420 }
1421 #[doc = "FTM0_CH3 pin is output of FTM0 channel 3 output"]
1422 #[inline]
1423 pub fn _0(self) -> &'a mut W {
1424 self.variant(FTM0OCH3SRCW::_0)
1425 }
1426 #[doc = "FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output"]
1427 #[inline]
1428 pub fn _1(self) -> &'a mut W {
1429 self.variant(FTM0OCH3SRCW::_1)
1430 }
1431 #[doc = r" Sets the field bit"]
1432 pub fn set_bit(self) -> &'a mut W {
1433 self.bit(true)
1434 }
1435 #[doc = r" Clears the field bit"]
1436 pub fn clear_bit(self) -> &'a mut W {
1437 self.bit(false)
1438 }
1439 #[doc = r" Writes raw bits to the field"]
1440 #[inline]
1441 pub fn bit(self, value: bool) -> &'a mut W {
1442 const MASK: bool = true;
1443 const OFFSET: u8 = 19;
1444 self.w.bits &= !((MASK as u32) << OFFSET);
1445 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1446 self.w
1447 }
1448}
1449#[doc = "Values that can be written to the field `FTM0OCH4SRC`"]
1450pub enum FTM0OCH4SRCW {
1451 #[doc = "FTM0_CH4 pin is output of FTM0 channel 4 output"]
1452 _0,
1453 #[doc = "FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output"]
1454 _1,
1455}
1456impl FTM0OCH4SRCW {
1457 #[allow(missing_docs)]
1458 #[doc(hidden)]
1459 #[inline]
1460 pub fn _bits(&self) -> bool {
1461 match *self {
1462 FTM0OCH4SRCW::_0 => false,
1463 FTM0OCH4SRCW::_1 => true,
1464 }
1465 }
1466}
1467#[doc = r" Proxy"]
1468pub struct _FTM0OCH4SRCW<'a> {
1469 w: &'a mut W,
1470}
1471impl<'a> _FTM0OCH4SRCW<'a> {
1472 #[doc = r" Writes `variant` to the field"]
1473 #[inline]
1474 pub fn variant(self, variant: FTM0OCH4SRCW) -> &'a mut W {
1475 {
1476 self.bit(variant._bits())
1477 }
1478 }
1479 #[doc = "FTM0_CH4 pin is output of FTM0 channel 4 output"]
1480 #[inline]
1481 pub fn _0(self) -> &'a mut W {
1482 self.variant(FTM0OCH4SRCW::_0)
1483 }
1484 #[doc = "FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output"]
1485 #[inline]
1486 pub fn _1(self) -> &'a mut W {
1487 self.variant(FTM0OCH4SRCW::_1)
1488 }
1489 #[doc = r" Sets the field bit"]
1490 pub fn set_bit(self) -> &'a mut W {
1491 self.bit(true)
1492 }
1493 #[doc = r" Clears the field bit"]
1494 pub fn clear_bit(self) -> &'a mut W {
1495 self.bit(false)
1496 }
1497 #[doc = r" Writes raw bits to the field"]
1498 #[inline]
1499 pub fn bit(self, value: bool) -> &'a mut W {
1500 const MASK: bool = true;
1501 const OFFSET: u8 = 20;
1502 self.w.bits &= !((MASK as u32) << OFFSET);
1503 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1504 self.w
1505 }
1506}
1507#[doc = "Values that can be written to the field `FTM0OCH5SRC`"]
1508pub enum FTM0OCH5SRCW {
1509 #[doc = "FTM0_CH5 pin is output of FTM0 channel 5 output"]
1510 _0,
1511 #[doc = "FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output"]
1512 _1,
1513}
1514impl FTM0OCH5SRCW {
1515 #[allow(missing_docs)]
1516 #[doc(hidden)]
1517 #[inline]
1518 pub fn _bits(&self) -> bool {
1519 match *self {
1520 FTM0OCH5SRCW::_0 => false,
1521 FTM0OCH5SRCW::_1 => true,
1522 }
1523 }
1524}
1525#[doc = r" Proxy"]
1526pub struct _FTM0OCH5SRCW<'a> {
1527 w: &'a mut W,
1528}
1529impl<'a> _FTM0OCH5SRCW<'a> {
1530 #[doc = r" Writes `variant` to the field"]
1531 #[inline]
1532 pub fn variant(self, variant: FTM0OCH5SRCW) -> &'a mut W {
1533 {
1534 self.bit(variant._bits())
1535 }
1536 }
1537 #[doc = "FTM0_CH5 pin is output of FTM0 channel 5 output"]
1538 #[inline]
1539 pub fn _0(self) -> &'a mut W {
1540 self.variant(FTM0OCH5SRCW::_0)
1541 }
1542 #[doc = "FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output"]
1543 #[inline]
1544 pub fn _1(self) -> &'a mut W {
1545 self.variant(FTM0OCH5SRCW::_1)
1546 }
1547 #[doc = r" Sets the field bit"]
1548 pub fn set_bit(self) -> &'a mut W {
1549 self.bit(true)
1550 }
1551 #[doc = r" Clears the field bit"]
1552 pub fn clear_bit(self) -> &'a mut W {
1553 self.bit(false)
1554 }
1555 #[doc = r" Writes raw bits to the field"]
1556 #[inline]
1557 pub fn bit(self, value: bool) -> &'a mut W {
1558 const MASK: bool = true;
1559 const OFFSET: u8 = 21;
1560 self.w.bits &= !((MASK as u32) << OFFSET);
1561 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1562 self.w
1563 }
1564}
1565#[doc = "Values that can be written to the field `FTM0OCH6SRC`"]
1566pub enum FTM0OCH6SRCW {
1567 #[doc = "FTM0_CH6 pin is output of FTM0 channel 6 output"]
1568 _0,
1569 #[doc = "FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output"]
1570 _1,
1571}
1572impl FTM0OCH6SRCW {
1573 #[allow(missing_docs)]
1574 #[doc(hidden)]
1575 #[inline]
1576 pub fn _bits(&self) -> bool {
1577 match *self {
1578 FTM0OCH6SRCW::_0 => false,
1579 FTM0OCH6SRCW::_1 => true,
1580 }
1581 }
1582}
1583#[doc = r" Proxy"]
1584pub struct _FTM0OCH6SRCW<'a> {
1585 w: &'a mut W,
1586}
1587impl<'a> _FTM0OCH6SRCW<'a> {
1588 #[doc = r" Writes `variant` to the field"]
1589 #[inline]
1590 pub fn variant(self, variant: FTM0OCH6SRCW) -> &'a mut W {
1591 {
1592 self.bit(variant._bits())
1593 }
1594 }
1595 #[doc = "FTM0_CH6 pin is output of FTM0 channel 6 output"]
1596 #[inline]
1597 pub fn _0(self) -> &'a mut W {
1598 self.variant(FTM0OCH6SRCW::_0)
1599 }
1600 #[doc = "FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output"]
1601 #[inline]
1602 pub fn _1(self) -> &'a mut W {
1603 self.variant(FTM0OCH6SRCW::_1)
1604 }
1605 #[doc = r" Sets the field bit"]
1606 pub fn set_bit(self) -> &'a mut W {
1607 self.bit(true)
1608 }
1609 #[doc = r" Clears the field bit"]
1610 pub fn clear_bit(self) -> &'a mut W {
1611 self.bit(false)
1612 }
1613 #[doc = r" Writes raw bits to the field"]
1614 #[inline]
1615 pub fn bit(self, value: bool) -> &'a mut W {
1616 const MASK: bool = true;
1617 const OFFSET: u8 = 22;
1618 self.w.bits &= !((MASK as u32) << OFFSET);
1619 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1620 self.w
1621 }
1622}
1623#[doc = "Values that can be written to the field `FTM0OCH7SRC`"]
1624pub enum FTM0OCH7SRCW {
1625 #[doc = "FTM0_CH7 pin is output of FTM0 channel 7 output"]
1626 _0,
1627 #[doc = "FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output"]
1628 _1,
1629}
1630impl FTM0OCH7SRCW {
1631 #[allow(missing_docs)]
1632 #[doc(hidden)]
1633 #[inline]
1634 pub fn _bits(&self) -> bool {
1635 match *self {
1636 FTM0OCH7SRCW::_0 => false,
1637 FTM0OCH7SRCW::_1 => true,
1638 }
1639 }
1640}
1641#[doc = r" Proxy"]
1642pub struct _FTM0OCH7SRCW<'a> {
1643 w: &'a mut W,
1644}
1645impl<'a> _FTM0OCH7SRCW<'a> {
1646 #[doc = r" Writes `variant` to the field"]
1647 #[inline]
1648 pub fn variant(self, variant: FTM0OCH7SRCW) -> &'a mut W {
1649 {
1650 self.bit(variant._bits())
1651 }
1652 }
1653 #[doc = "FTM0_CH7 pin is output of FTM0 channel 7 output"]
1654 #[inline]
1655 pub fn _0(self) -> &'a mut W {
1656 self.variant(FTM0OCH7SRCW::_0)
1657 }
1658 #[doc = "FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output"]
1659 #[inline]
1660 pub fn _1(self) -> &'a mut W {
1661 self.variant(FTM0OCH7SRCW::_1)
1662 }
1663 #[doc = r" Sets the field bit"]
1664 pub fn set_bit(self) -> &'a mut W {
1665 self.bit(true)
1666 }
1667 #[doc = r" Clears the field bit"]
1668 pub fn clear_bit(self) -> &'a mut W {
1669 self.bit(false)
1670 }
1671 #[doc = r" Writes raw bits to the field"]
1672 #[inline]
1673 pub fn bit(self, value: bool) -> &'a mut W {
1674 const MASK: bool = true;
1675 const OFFSET: u8 = 23;
1676 self.w.bits &= !((MASK as u32) << OFFSET);
1677 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1678 self.w
1679 }
1680}
1681#[doc = "Values that can be written to the field `FTM3OCH0SRC`"]
1682pub enum FTM3OCH0SRCW {
1683 #[doc = "FTM3_CH0 pin is output of FTM3 channel 0 output"]
1684 _0,
1685 #[doc = "FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output."]
1686 _1,
1687}
1688impl FTM3OCH0SRCW {
1689 #[allow(missing_docs)]
1690 #[doc(hidden)]
1691 #[inline]
1692 pub fn _bits(&self) -> bool {
1693 match *self {
1694 FTM3OCH0SRCW::_0 => false,
1695 FTM3OCH0SRCW::_1 => true,
1696 }
1697 }
1698}
1699#[doc = r" Proxy"]
1700pub struct _FTM3OCH0SRCW<'a> {
1701 w: &'a mut W,
1702}
1703impl<'a> _FTM3OCH0SRCW<'a> {
1704 #[doc = r" Writes `variant` to the field"]
1705 #[inline]
1706 pub fn variant(self, variant: FTM3OCH0SRCW) -> &'a mut W {
1707 {
1708 self.bit(variant._bits())
1709 }
1710 }
1711 #[doc = "FTM3_CH0 pin is output of FTM3 channel 0 output"]
1712 #[inline]
1713 pub fn _0(self) -> &'a mut W {
1714 self.variant(FTM3OCH0SRCW::_0)
1715 }
1716 #[doc = "FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output."]
1717 #[inline]
1718 pub fn _1(self) -> &'a mut W {
1719 self.variant(FTM3OCH0SRCW::_1)
1720 }
1721 #[doc = r" Sets the field bit"]
1722 pub fn set_bit(self) -> &'a mut W {
1723 self.bit(true)
1724 }
1725 #[doc = r" Clears the field bit"]
1726 pub fn clear_bit(self) -> &'a mut W {
1727 self.bit(false)
1728 }
1729 #[doc = r" Writes raw bits to the field"]
1730 #[inline]
1731 pub fn bit(self, value: bool) -> &'a mut W {
1732 const MASK: bool = true;
1733 const OFFSET: u8 = 24;
1734 self.w.bits &= !((MASK as u32) << OFFSET);
1735 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1736 self.w
1737 }
1738}
1739#[doc = "Values that can be written to the field `FTM3OCH1SRC`"]
1740pub enum FTM3OCH1SRCW {
1741 #[doc = "FTM3_CH1 pin is output of FTM3 channel 1 output"]
1742 _0,
1743 #[doc = "FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output."]
1744 _1,
1745}
1746impl FTM3OCH1SRCW {
1747 #[allow(missing_docs)]
1748 #[doc(hidden)]
1749 #[inline]
1750 pub fn _bits(&self) -> bool {
1751 match *self {
1752 FTM3OCH1SRCW::_0 => false,
1753 FTM3OCH1SRCW::_1 => true,
1754 }
1755 }
1756}
1757#[doc = r" Proxy"]
1758pub struct _FTM3OCH1SRCW<'a> {
1759 w: &'a mut W,
1760}
1761impl<'a> _FTM3OCH1SRCW<'a> {
1762 #[doc = r" Writes `variant` to the field"]
1763 #[inline]
1764 pub fn variant(self, variant: FTM3OCH1SRCW) -> &'a mut W {
1765 {
1766 self.bit(variant._bits())
1767 }
1768 }
1769 #[doc = "FTM3_CH1 pin is output of FTM3 channel 1 output"]
1770 #[inline]
1771 pub fn _0(self) -> &'a mut W {
1772 self.variant(FTM3OCH1SRCW::_0)
1773 }
1774 #[doc = "FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output."]
1775 #[inline]
1776 pub fn _1(self) -> &'a mut W {
1777 self.variant(FTM3OCH1SRCW::_1)
1778 }
1779 #[doc = r" Sets the field bit"]
1780 pub fn set_bit(self) -> &'a mut W {
1781 self.bit(true)
1782 }
1783 #[doc = r" Clears the field bit"]
1784 pub fn clear_bit(self) -> &'a mut W {
1785 self.bit(false)
1786 }
1787 #[doc = r" Writes raw bits to the field"]
1788 #[inline]
1789 pub fn bit(self, value: bool) -> &'a mut W {
1790 const MASK: bool = true;
1791 const OFFSET: u8 = 25;
1792 self.w.bits &= !((MASK as u32) << OFFSET);
1793 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1794 self.w
1795 }
1796}
1797#[doc = "Values that can be written to the field `FTM3OCH2SRC`"]
1798pub enum FTM3OCH2SRCW {
1799 #[doc = "FTM3_CH2 pin is output of FTM3 channel 2 output"]
1800 _0,
1801 #[doc = "FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output."]
1802 _1,
1803}
1804impl FTM3OCH2SRCW {
1805 #[allow(missing_docs)]
1806 #[doc(hidden)]
1807 #[inline]
1808 pub fn _bits(&self) -> bool {
1809 match *self {
1810 FTM3OCH2SRCW::_0 => false,
1811 FTM3OCH2SRCW::_1 => true,
1812 }
1813 }
1814}
1815#[doc = r" Proxy"]
1816pub struct _FTM3OCH2SRCW<'a> {
1817 w: &'a mut W,
1818}
1819impl<'a> _FTM3OCH2SRCW<'a> {
1820 #[doc = r" Writes `variant` to the field"]
1821 #[inline]
1822 pub fn variant(self, variant: FTM3OCH2SRCW) -> &'a mut W {
1823 {
1824 self.bit(variant._bits())
1825 }
1826 }
1827 #[doc = "FTM3_CH2 pin is output of FTM3 channel 2 output"]
1828 #[inline]
1829 pub fn _0(self) -> &'a mut W {
1830 self.variant(FTM3OCH2SRCW::_0)
1831 }
1832 #[doc = "FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output."]
1833 #[inline]
1834 pub fn _1(self) -> &'a mut W {
1835 self.variant(FTM3OCH2SRCW::_1)
1836 }
1837 #[doc = r" Sets the field bit"]
1838 pub fn set_bit(self) -> &'a mut W {
1839 self.bit(true)
1840 }
1841 #[doc = r" Clears the field bit"]
1842 pub fn clear_bit(self) -> &'a mut W {
1843 self.bit(false)
1844 }
1845 #[doc = r" Writes raw bits to the field"]
1846 #[inline]
1847 pub fn bit(self, value: bool) -> &'a mut W {
1848 const MASK: bool = true;
1849 const OFFSET: u8 = 26;
1850 self.w.bits &= !((MASK as u32) << OFFSET);
1851 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1852 self.w
1853 }
1854}
1855#[doc = "Values that can be written to the field `FTM3OCH3SRC`"]
1856pub enum FTM3OCH3SRCW {
1857 #[doc = "FTM3_CH3 pin is output of FTM3 channel 3 output"]
1858 _0,
1859 #[doc = "FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output."]
1860 _1,
1861}
1862impl FTM3OCH3SRCW {
1863 #[allow(missing_docs)]
1864 #[doc(hidden)]
1865 #[inline]
1866 pub fn _bits(&self) -> bool {
1867 match *self {
1868 FTM3OCH3SRCW::_0 => false,
1869 FTM3OCH3SRCW::_1 => true,
1870 }
1871 }
1872}
1873#[doc = r" Proxy"]
1874pub struct _FTM3OCH3SRCW<'a> {
1875 w: &'a mut W,
1876}
1877impl<'a> _FTM3OCH3SRCW<'a> {
1878 #[doc = r" Writes `variant` to the field"]
1879 #[inline]
1880 pub fn variant(self, variant: FTM3OCH3SRCW) -> &'a mut W {
1881 {
1882 self.bit(variant._bits())
1883 }
1884 }
1885 #[doc = "FTM3_CH3 pin is output of FTM3 channel 3 output"]
1886 #[inline]
1887 pub fn _0(self) -> &'a mut W {
1888 self.variant(FTM3OCH3SRCW::_0)
1889 }
1890 #[doc = "FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output."]
1891 #[inline]
1892 pub fn _1(self) -> &'a mut W {
1893 self.variant(FTM3OCH3SRCW::_1)
1894 }
1895 #[doc = r" Sets the field bit"]
1896 pub fn set_bit(self) -> &'a mut W {
1897 self.bit(true)
1898 }
1899 #[doc = r" Clears the field bit"]
1900 pub fn clear_bit(self) -> &'a mut W {
1901 self.bit(false)
1902 }
1903 #[doc = r" Writes raw bits to the field"]
1904 #[inline]
1905 pub fn bit(self, value: bool) -> &'a mut W {
1906 const MASK: bool = true;
1907 const OFFSET: u8 = 27;
1908 self.w.bits &= !((MASK as u32) << OFFSET);
1909 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1910 self.w
1911 }
1912}
1913#[doc = "Values that can be written to the field `FTM3OCH4SRC`"]
1914pub enum FTM3OCH4SRCW {
1915 #[doc = "FTM3_CH4 pin is output of FTM3 channel 4 output"]
1916 _0,
1917 #[doc = "FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output."]
1918 _1,
1919}
1920impl FTM3OCH4SRCW {
1921 #[allow(missing_docs)]
1922 #[doc(hidden)]
1923 #[inline]
1924 pub fn _bits(&self) -> bool {
1925 match *self {
1926 FTM3OCH4SRCW::_0 => false,
1927 FTM3OCH4SRCW::_1 => true,
1928 }
1929 }
1930}
1931#[doc = r" Proxy"]
1932pub struct _FTM3OCH4SRCW<'a> {
1933 w: &'a mut W,
1934}
1935impl<'a> _FTM3OCH4SRCW<'a> {
1936 #[doc = r" Writes `variant` to the field"]
1937 #[inline]
1938 pub fn variant(self, variant: FTM3OCH4SRCW) -> &'a mut W {
1939 {
1940 self.bit(variant._bits())
1941 }
1942 }
1943 #[doc = "FTM3_CH4 pin is output of FTM3 channel 4 output"]
1944 #[inline]
1945 pub fn _0(self) -> &'a mut W {
1946 self.variant(FTM3OCH4SRCW::_0)
1947 }
1948 #[doc = "FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output."]
1949 #[inline]
1950 pub fn _1(self) -> &'a mut W {
1951 self.variant(FTM3OCH4SRCW::_1)
1952 }
1953 #[doc = r" Sets the field bit"]
1954 pub fn set_bit(self) -> &'a mut W {
1955 self.bit(true)
1956 }
1957 #[doc = r" Clears the field bit"]
1958 pub fn clear_bit(self) -> &'a mut W {
1959 self.bit(false)
1960 }
1961 #[doc = r" Writes raw bits to the field"]
1962 #[inline]
1963 pub fn bit(self, value: bool) -> &'a mut W {
1964 const MASK: bool = true;
1965 const OFFSET: u8 = 28;
1966 self.w.bits &= !((MASK as u32) << OFFSET);
1967 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1968 self.w
1969 }
1970}
1971#[doc = "Values that can be written to the field `FTM3OCH5SRC`"]
1972pub enum FTM3OCH5SRCW {
1973 #[doc = "FTM3_CH5 pin is output of FTM3 channel 5 output"]
1974 _0,
1975 #[doc = "FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output."]
1976 _1,
1977}
1978impl FTM3OCH5SRCW {
1979 #[allow(missing_docs)]
1980 #[doc(hidden)]
1981 #[inline]
1982 pub fn _bits(&self) -> bool {
1983 match *self {
1984 FTM3OCH5SRCW::_0 => false,
1985 FTM3OCH5SRCW::_1 => true,
1986 }
1987 }
1988}
1989#[doc = r" Proxy"]
1990pub struct _FTM3OCH5SRCW<'a> {
1991 w: &'a mut W,
1992}
1993impl<'a> _FTM3OCH5SRCW<'a> {
1994 #[doc = r" Writes `variant` to the field"]
1995 #[inline]
1996 pub fn variant(self, variant: FTM3OCH5SRCW) -> &'a mut W {
1997 {
1998 self.bit(variant._bits())
1999 }
2000 }
2001 #[doc = "FTM3_CH5 pin is output of FTM3 channel 5 output"]
2002 #[inline]
2003 pub fn _0(self) -> &'a mut W {
2004 self.variant(FTM3OCH5SRCW::_0)
2005 }
2006 #[doc = "FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output."]
2007 #[inline]
2008 pub fn _1(self) -> &'a mut W {
2009 self.variant(FTM3OCH5SRCW::_1)
2010 }
2011 #[doc = r" Sets the field bit"]
2012 pub fn set_bit(self) -> &'a mut W {
2013 self.bit(true)
2014 }
2015 #[doc = r" Clears the field bit"]
2016 pub fn clear_bit(self) -> &'a mut W {
2017 self.bit(false)
2018 }
2019 #[doc = r" Writes raw bits to the field"]
2020 #[inline]
2021 pub fn bit(self, value: bool) -> &'a mut W {
2022 const MASK: bool = true;
2023 const OFFSET: u8 = 29;
2024 self.w.bits &= !((MASK as u32) << OFFSET);
2025 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2026 self.w
2027 }
2028}
2029#[doc = "Values that can be written to the field `FTM3OCH6SRC`"]
2030pub enum FTM3OCH6SRCW {
2031 #[doc = "FTM3_CH6 pin is output of FTM3 channel 6 output"]
2032 _0,
2033 #[doc = "FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output."]
2034 _1,
2035}
2036impl FTM3OCH6SRCW {
2037 #[allow(missing_docs)]
2038 #[doc(hidden)]
2039 #[inline]
2040 pub fn _bits(&self) -> bool {
2041 match *self {
2042 FTM3OCH6SRCW::_0 => false,
2043 FTM3OCH6SRCW::_1 => true,
2044 }
2045 }
2046}
2047#[doc = r" Proxy"]
2048pub struct _FTM3OCH6SRCW<'a> {
2049 w: &'a mut W,
2050}
2051impl<'a> _FTM3OCH6SRCW<'a> {
2052 #[doc = r" Writes `variant` to the field"]
2053 #[inline]
2054 pub fn variant(self, variant: FTM3OCH6SRCW) -> &'a mut W {
2055 {
2056 self.bit(variant._bits())
2057 }
2058 }
2059 #[doc = "FTM3_CH6 pin is output of FTM3 channel 6 output"]
2060 #[inline]
2061 pub fn _0(self) -> &'a mut W {
2062 self.variant(FTM3OCH6SRCW::_0)
2063 }
2064 #[doc = "FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output."]
2065 #[inline]
2066 pub fn _1(self) -> &'a mut W {
2067 self.variant(FTM3OCH6SRCW::_1)
2068 }
2069 #[doc = r" Sets the field bit"]
2070 pub fn set_bit(self) -> &'a mut W {
2071 self.bit(true)
2072 }
2073 #[doc = r" Clears the field bit"]
2074 pub fn clear_bit(self) -> &'a mut W {
2075 self.bit(false)
2076 }
2077 #[doc = r" Writes raw bits to the field"]
2078 #[inline]
2079 pub fn bit(self, value: bool) -> &'a mut W {
2080 const MASK: bool = true;
2081 const OFFSET: u8 = 30;
2082 self.w.bits &= !((MASK as u32) << OFFSET);
2083 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2084 self.w
2085 }
2086}
2087#[doc = "Values that can be written to the field `FTM3OCH7SRC`"]
2088pub enum FTM3OCH7SRCW {
2089 #[doc = "FTM3_CH7 pin is output of FTM3 channel 7 output"]
2090 _0,
2091 #[doc = "FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output."]
2092 _1,
2093}
2094impl FTM3OCH7SRCW {
2095 #[allow(missing_docs)]
2096 #[doc(hidden)]
2097 #[inline]
2098 pub fn _bits(&self) -> bool {
2099 match *self {
2100 FTM3OCH7SRCW::_0 => false,
2101 FTM3OCH7SRCW::_1 => true,
2102 }
2103 }
2104}
2105#[doc = r" Proxy"]
2106pub struct _FTM3OCH7SRCW<'a> {
2107 w: &'a mut W,
2108}
2109impl<'a> _FTM3OCH7SRCW<'a> {
2110 #[doc = r" Writes `variant` to the field"]
2111 #[inline]
2112 pub fn variant(self, variant: FTM3OCH7SRCW) -> &'a mut W {
2113 {
2114 self.bit(variant._bits())
2115 }
2116 }
2117 #[doc = "FTM3_CH7 pin is output of FTM3 channel 7 output"]
2118 #[inline]
2119 pub fn _0(self) -> &'a mut W {
2120 self.variant(FTM3OCH7SRCW::_0)
2121 }
2122 #[doc = "FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output."]
2123 #[inline]
2124 pub fn _1(self) -> &'a mut W {
2125 self.variant(FTM3OCH7SRCW::_1)
2126 }
2127 #[doc = r" Sets the field bit"]
2128 pub fn set_bit(self) -> &'a mut W {
2129 self.bit(true)
2130 }
2131 #[doc = r" Clears the field bit"]
2132 pub fn clear_bit(self) -> &'a mut W {
2133 self.bit(false)
2134 }
2135 #[doc = r" Writes raw bits to the field"]
2136 #[inline]
2137 pub fn bit(self, value: bool) -> &'a mut W {
2138 const MASK: bool = true;
2139 const OFFSET: u8 = 31;
2140 self.w.bits &= !((MASK as u32) << OFFSET);
2141 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2142 self.w
2143 }
2144}
2145impl R {
2146 #[doc = r" Value of the register as raw bits"]
2147 #[inline]
2148 pub fn bits(&self) -> u32 {
2149 self.bits
2150 }
2151 #[doc = "Bit 0 - FTM0 Hardware Trigger 0 Software Synchronization"]
2152 #[inline]
2153 pub fn ftm0syncbit(&self) -> FTM0SYNCBITR {
2154 FTM0SYNCBITR::_from({
2155 const MASK: bool = true;
2156 const OFFSET: u8 = 0;
2157 ((self.bits >> OFFSET) & MASK as u32) != 0
2158 })
2159 }
2160 #[doc = "Bit 1 - FTM1 Hardware Trigger 0 Software Synchronization"]
2161 #[inline]
2162 pub fn ftm1syncbit(&self) -> FTM1SYNCBITR {
2163 FTM1SYNCBITR::_from({
2164 const MASK: bool = true;
2165 const OFFSET: u8 = 1;
2166 ((self.bits >> OFFSET) & MASK as u32) != 0
2167 })
2168 }
2169 #[doc = "Bit 2 - FTM2 Hardware Trigger 0 Software Synchronization"]
2170 #[inline]
2171 pub fn ftm2syncbit(&self) -> FTM2SYNCBITR {
2172 FTM2SYNCBITR::_from({
2173 const MASK: bool = true;
2174 const OFFSET: u8 = 2;
2175 ((self.bits >> OFFSET) & MASK as u32) != 0
2176 })
2177 }
2178 #[doc = "Bit 3 - FTM3 Hardware Trigger 0 Software Synchronization"]
2179 #[inline]
2180 pub fn ftm3syncbit(&self) -> FTM3SYNCBITR {
2181 FTM3SYNCBITR::_from({
2182 const MASK: bool = true;
2183 const OFFSET: u8 = 3;
2184 ((self.bits >> OFFSET) & MASK as u32) != 0
2185 })
2186 }
2187 #[doc = "Bit 16 - FTM0 channel 0 output source"]
2188 #[inline]
2189 pub fn ftm0och0src(&self) -> FTM0OCH0SRCR {
2190 FTM0OCH0SRCR::_from({
2191 const MASK: bool = true;
2192 const OFFSET: u8 = 16;
2193 ((self.bits >> OFFSET) & MASK as u32) != 0
2194 })
2195 }
2196 #[doc = "Bit 17 - FTM0 channel 1 output source"]
2197 #[inline]
2198 pub fn ftm0och1src(&self) -> FTM0OCH1SRCR {
2199 FTM0OCH1SRCR::_from({
2200 const MASK: bool = true;
2201 const OFFSET: u8 = 17;
2202 ((self.bits >> OFFSET) & MASK as u32) != 0
2203 })
2204 }
2205 #[doc = "Bit 18 - FTM0 channel 2 output source"]
2206 #[inline]
2207 pub fn ftm0och2src(&self) -> FTM0OCH2SRCR {
2208 FTM0OCH2SRCR::_from({
2209 const MASK: bool = true;
2210 const OFFSET: u8 = 18;
2211 ((self.bits >> OFFSET) & MASK as u32) != 0
2212 })
2213 }
2214 #[doc = "Bit 19 - FTM0 channel 3 output source"]
2215 #[inline]
2216 pub fn ftm0och3src(&self) -> FTM0OCH3SRCR {
2217 FTM0OCH3SRCR::_from({
2218 const MASK: bool = true;
2219 const OFFSET: u8 = 19;
2220 ((self.bits >> OFFSET) & MASK as u32) != 0
2221 })
2222 }
2223 #[doc = "Bit 20 - FTM0 channel 4 output source"]
2224 #[inline]
2225 pub fn ftm0och4src(&self) -> FTM0OCH4SRCR {
2226 FTM0OCH4SRCR::_from({
2227 const MASK: bool = true;
2228 const OFFSET: u8 = 20;
2229 ((self.bits >> OFFSET) & MASK as u32) != 0
2230 })
2231 }
2232 #[doc = "Bit 21 - FTM0 channel 5 output source"]
2233 #[inline]
2234 pub fn ftm0och5src(&self) -> FTM0OCH5SRCR {
2235 FTM0OCH5SRCR::_from({
2236 const MASK: bool = true;
2237 const OFFSET: u8 = 21;
2238 ((self.bits >> OFFSET) & MASK as u32) != 0
2239 })
2240 }
2241 #[doc = "Bit 22 - FTM0 channel 6 output source"]
2242 #[inline]
2243 pub fn ftm0och6src(&self) -> FTM0OCH6SRCR {
2244 FTM0OCH6SRCR::_from({
2245 const MASK: bool = true;
2246 const OFFSET: u8 = 22;
2247 ((self.bits >> OFFSET) & MASK as u32) != 0
2248 })
2249 }
2250 #[doc = "Bit 23 - FTM0 channel 7 output source"]
2251 #[inline]
2252 pub fn ftm0och7src(&self) -> FTM0OCH7SRCR {
2253 FTM0OCH7SRCR::_from({
2254 const MASK: bool = true;
2255 const OFFSET: u8 = 23;
2256 ((self.bits >> OFFSET) & MASK as u32) != 0
2257 })
2258 }
2259 #[doc = "Bit 24 - FTM3 channel 0 output source"]
2260 #[inline]
2261 pub fn ftm3och0src(&self) -> FTM3OCH0SRCR {
2262 FTM3OCH0SRCR::_from({
2263 const MASK: bool = true;
2264 const OFFSET: u8 = 24;
2265 ((self.bits >> OFFSET) & MASK as u32) != 0
2266 })
2267 }
2268 #[doc = "Bit 25 - FTM3 channel 1 output source"]
2269 #[inline]
2270 pub fn ftm3och1src(&self) -> FTM3OCH1SRCR {
2271 FTM3OCH1SRCR::_from({
2272 const MASK: bool = true;
2273 const OFFSET: u8 = 25;
2274 ((self.bits >> OFFSET) & MASK as u32) != 0
2275 })
2276 }
2277 #[doc = "Bit 26 - FTM3 channel 2 output source"]
2278 #[inline]
2279 pub fn ftm3och2src(&self) -> FTM3OCH2SRCR {
2280 FTM3OCH2SRCR::_from({
2281 const MASK: bool = true;
2282 const OFFSET: u8 = 26;
2283 ((self.bits >> OFFSET) & MASK as u32) != 0
2284 })
2285 }
2286 #[doc = "Bit 27 - FTM3 channel 3 output source"]
2287 #[inline]
2288 pub fn ftm3och3src(&self) -> FTM3OCH3SRCR {
2289 FTM3OCH3SRCR::_from({
2290 const MASK: bool = true;
2291 const OFFSET: u8 = 27;
2292 ((self.bits >> OFFSET) & MASK as u32) != 0
2293 })
2294 }
2295 #[doc = "Bit 28 - FTM3 channel 4 output source"]
2296 #[inline]
2297 pub fn ftm3och4src(&self) -> FTM3OCH4SRCR {
2298 FTM3OCH4SRCR::_from({
2299 const MASK: bool = true;
2300 const OFFSET: u8 = 28;
2301 ((self.bits >> OFFSET) & MASK as u32) != 0
2302 })
2303 }
2304 #[doc = "Bit 29 - FTM3 channel 5 output source"]
2305 #[inline]
2306 pub fn ftm3och5src(&self) -> FTM3OCH5SRCR {
2307 FTM3OCH5SRCR::_from({
2308 const MASK: bool = true;
2309 const OFFSET: u8 = 29;
2310 ((self.bits >> OFFSET) & MASK as u32) != 0
2311 })
2312 }
2313 #[doc = "Bit 30 - FTM3 channel 6 output source"]
2314 #[inline]
2315 pub fn ftm3och6src(&self) -> FTM3OCH6SRCR {
2316 FTM3OCH6SRCR::_from({
2317 const MASK: bool = true;
2318 const OFFSET: u8 = 30;
2319 ((self.bits >> OFFSET) & MASK as u32) != 0
2320 })
2321 }
2322 #[doc = "Bit 31 - FTM3 channel 7 output source"]
2323 #[inline]
2324 pub fn ftm3och7src(&self) -> FTM3OCH7SRCR {
2325 FTM3OCH7SRCR::_from({
2326 const MASK: bool = true;
2327 const OFFSET: u8 = 31;
2328 ((self.bits >> OFFSET) & MASK as u32) != 0
2329 })
2330 }
2331}
2332impl W {
2333 #[doc = r" Reset value of the register"]
2334 #[inline]
2335 pub fn reset_value() -> W {
2336 W { bits: 0 }
2337 }
2338 #[doc = r" Writes raw bits to the register"]
2339 #[inline]
2340 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2341 self.bits = bits;
2342 self
2343 }
2344 #[doc = "Bit 0 - FTM0 Hardware Trigger 0 Software Synchronization"]
2345 #[inline]
2346 pub fn ftm0syncbit(&mut self) -> _FTM0SYNCBITW {
2347 _FTM0SYNCBITW { w: self }
2348 }
2349 #[doc = "Bit 1 - FTM1 Hardware Trigger 0 Software Synchronization"]
2350 #[inline]
2351 pub fn ftm1syncbit(&mut self) -> _FTM1SYNCBITW {
2352 _FTM1SYNCBITW { w: self }
2353 }
2354 #[doc = "Bit 2 - FTM2 Hardware Trigger 0 Software Synchronization"]
2355 #[inline]
2356 pub fn ftm2syncbit(&mut self) -> _FTM2SYNCBITW {
2357 _FTM2SYNCBITW { w: self }
2358 }
2359 #[doc = "Bit 3 - FTM3 Hardware Trigger 0 Software Synchronization"]
2360 #[inline]
2361 pub fn ftm3syncbit(&mut self) -> _FTM3SYNCBITW {
2362 _FTM3SYNCBITW { w: self }
2363 }
2364 #[doc = "Bit 16 - FTM0 channel 0 output source"]
2365 #[inline]
2366 pub fn ftm0och0src(&mut self) -> _FTM0OCH0SRCW {
2367 _FTM0OCH0SRCW { w: self }
2368 }
2369 #[doc = "Bit 17 - FTM0 channel 1 output source"]
2370 #[inline]
2371 pub fn ftm0och1src(&mut self) -> _FTM0OCH1SRCW {
2372 _FTM0OCH1SRCW { w: self }
2373 }
2374 #[doc = "Bit 18 - FTM0 channel 2 output source"]
2375 #[inline]
2376 pub fn ftm0och2src(&mut self) -> _FTM0OCH2SRCW {
2377 _FTM0OCH2SRCW { w: self }
2378 }
2379 #[doc = "Bit 19 - FTM0 channel 3 output source"]
2380 #[inline]
2381 pub fn ftm0och3src(&mut self) -> _FTM0OCH3SRCW {
2382 _FTM0OCH3SRCW { w: self }
2383 }
2384 #[doc = "Bit 20 - FTM0 channel 4 output source"]
2385 #[inline]
2386 pub fn ftm0och4src(&mut self) -> _FTM0OCH4SRCW {
2387 _FTM0OCH4SRCW { w: self }
2388 }
2389 #[doc = "Bit 21 - FTM0 channel 5 output source"]
2390 #[inline]
2391 pub fn ftm0och5src(&mut self) -> _FTM0OCH5SRCW {
2392 _FTM0OCH5SRCW { w: self }
2393 }
2394 #[doc = "Bit 22 - FTM0 channel 6 output source"]
2395 #[inline]
2396 pub fn ftm0och6src(&mut self) -> _FTM0OCH6SRCW {
2397 _FTM0OCH6SRCW { w: self }
2398 }
2399 #[doc = "Bit 23 - FTM0 channel 7 output source"]
2400 #[inline]
2401 pub fn ftm0och7src(&mut self) -> _FTM0OCH7SRCW {
2402 _FTM0OCH7SRCW { w: self }
2403 }
2404 #[doc = "Bit 24 - FTM3 channel 0 output source"]
2405 #[inline]
2406 pub fn ftm3och0src(&mut self) -> _FTM3OCH0SRCW {
2407 _FTM3OCH0SRCW { w: self }
2408 }
2409 #[doc = "Bit 25 - FTM3 channel 1 output source"]
2410 #[inline]
2411 pub fn ftm3och1src(&mut self) -> _FTM3OCH1SRCW {
2412 _FTM3OCH1SRCW { w: self }
2413 }
2414 #[doc = "Bit 26 - FTM3 channel 2 output source"]
2415 #[inline]
2416 pub fn ftm3och2src(&mut self) -> _FTM3OCH2SRCW {
2417 _FTM3OCH2SRCW { w: self }
2418 }
2419 #[doc = "Bit 27 - FTM3 channel 3 output source"]
2420 #[inline]
2421 pub fn ftm3och3src(&mut self) -> _FTM3OCH3SRCW {
2422 _FTM3OCH3SRCW { w: self }
2423 }
2424 #[doc = "Bit 28 - FTM3 channel 4 output source"]
2425 #[inline]
2426 pub fn ftm3och4src(&mut self) -> _FTM3OCH4SRCW {
2427 _FTM3OCH4SRCW { w: self }
2428 }
2429 #[doc = "Bit 29 - FTM3 channel 5 output source"]
2430 #[inline]
2431 pub fn ftm3och5src(&mut self) -> _FTM3OCH5SRCW {
2432 _FTM3OCH5SRCW { w: self }
2433 }
2434 #[doc = "Bit 30 - FTM3 channel 6 output source"]
2435 #[inline]
2436 pub fn ftm3och6src(&mut self) -> _FTM3OCH6SRCW {
2437 _FTM3OCH6SRCW { w: self }
2438 }
2439 #[doc = "Bit 31 - FTM3 channel 7 output source"]
2440 #[inline]
2441 pub fn ftm3och7src(&mut self) -> _FTM3OCH7SRCW {
2442 _FTM3OCH7SRCW { w: self }
2443 }
2444}