1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::PCR10 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `PS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum PSR {
48 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
49 _0,
50 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
51 _1,
52}
53impl PSR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 PSR::_0 => false,
69 PSR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> PSR {
76 match value {
77 false => PSR::_0,
78 true => PSR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == PSR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == PSR::_1
90 }
91}
92#[doc = "Possible values of the field `PE`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum PER {
95 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
96 _0,
97 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
98 _1,
99}
100impl PER {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 PER::_0 => false,
116 PER::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> PER {
123 match value {
124 false => PER::_0,
125 true => PER::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == PER::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == PER::_1
137 }
138}
139#[doc = "Possible values of the field `SRE`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum SRER {
142 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
143 _0,
144 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
145 _1,
146}
147impl SRER {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 SRER::_0 => false,
163 SRER::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> SRER {
170 match value {
171 false => SRER::_0,
172 true => SRER::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == SRER::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == SRER::_1
184 }
185}
186#[doc = "Possible values of the field `PFE`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum PFER {
189 #[doc = "Passive input filter is disabled on the corresponding pin."]
190 _0,
191 #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."]
192 _1,
193}
194impl PFER {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 PFER::_0 => false,
210 PFER::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> PFER {
217 match value {
218 false => PFER::_0,
219 true => PFER::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == PFER::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == PFER::_1
231 }
232}
233#[doc = "Possible values of the field `ODE`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum ODER {
236 #[doc = "Open drain output is disabled on the corresponding pin."]
237 _0,
238 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
239 _1,
240}
241impl ODER {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 ODER::_0 => false,
257 ODER::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> ODER {
264 match value {
265 false => ODER::_0,
266 true => ODER::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == ODER::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == ODER::_1
278 }
279}
280#[doc = "Possible values of the field `DSE`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum DSER {
283 #[doc = "Low drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
284 _0,
285 #[doc = "High drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
286 _1,
287}
288impl DSER {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 DSER::_0 => false,
304 DSER::_1 => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> DSER {
311 match value {
312 false => DSER::_0,
313 true => DSER::_1,
314 }
315 }
316 #[doc = "Checks if the value of the field is `_0`"]
317 #[inline]
318 pub fn is_0(&self) -> bool {
319 *self == DSER::_0
320 }
321 #[doc = "Checks if the value of the field is `_1`"]
322 #[inline]
323 pub fn is_1(&self) -> bool {
324 *self == DSER::_1
325 }
326}
327#[doc = "Possible values of the field `MUX`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum MUXR {
330 #[doc = "Pin disabled (analog)."]
331 _000,
332 #[doc = "Alternative 1 (GPIO)."]
333 _001,
334 #[doc = "Alternative 2 (chip-specific)."]
335 _010,
336 #[doc = "Alternative 3 (chip-specific)."]
337 _011,
338 #[doc = "Alternative 4 (chip-specific)."]
339 _100,
340 #[doc = "Alternative 5 (chip-specific)."]
341 _101,
342 #[doc = "Alternative 6 (chip-specific)."]
343 _110,
344 #[doc = "Alternative 7 (chip-specific)."]
345 _111,
346}
347impl MUXR {
348 #[doc = r" Value of the field as raw bits"]
349 #[inline]
350 pub fn bits(&self) -> u8 {
351 match *self {
352 MUXR::_000 => 0,
353 MUXR::_001 => 1,
354 MUXR::_010 => 2,
355 MUXR::_011 => 3,
356 MUXR::_100 => 4,
357 MUXR::_101 => 5,
358 MUXR::_110 => 6,
359 MUXR::_111 => 7,
360 }
361 }
362 #[allow(missing_docs)]
363 #[doc(hidden)]
364 #[inline]
365 pub fn _from(value: u8) -> MUXR {
366 match value {
367 0 => MUXR::_000,
368 1 => MUXR::_001,
369 2 => MUXR::_010,
370 3 => MUXR::_011,
371 4 => MUXR::_100,
372 5 => MUXR::_101,
373 6 => MUXR::_110,
374 7 => MUXR::_111,
375 _ => unreachable!(),
376 }
377 }
378 #[doc = "Checks if the value of the field is `_000`"]
379 #[inline]
380 pub fn is_000(&self) -> bool {
381 *self == MUXR::_000
382 }
383 #[doc = "Checks if the value of the field is `_001`"]
384 #[inline]
385 pub fn is_001(&self) -> bool {
386 *self == MUXR::_001
387 }
388 #[doc = "Checks if the value of the field is `_010`"]
389 #[inline]
390 pub fn is_010(&self) -> bool {
391 *self == MUXR::_010
392 }
393 #[doc = "Checks if the value of the field is `_011`"]
394 #[inline]
395 pub fn is_011(&self) -> bool {
396 *self == MUXR::_011
397 }
398 #[doc = "Checks if the value of the field is `_100`"]
399 #[inline]
400 pub fn is_100(&self) -> bool {
401 *self == MUXR::_100
402 }
403 #[doc = "Checks if the value of the field is `_101`"]
404 #[inline]
405 pub fn is_101(&self) -> bool {
406 *self == MUXR::_101
407 }
408 #[doc = "Checks if the value of the field is `_110`"]
409 #[inline]
410 pub fn is_110(&self) -> bool {
411 *self == MUXR::_110
412 }
413 #[doc = "Checks if the value of the field is `_111`"]
414 #[inline]
415 pub fn is_111(&self) -> bool {
416 *self == MUXR::_111
417 }
418}
419#[doc = "Possible values of the field `LK`"]
420#[derive(Clone, Copy, Debug, PartialEq)]
421pub enum LKR {
422 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
423 _0,
424 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
425 _1,
426}
427impl LKR {
428 #[doc = r" Returns `true` if the bit is clear (0)"]
429 #[inline]
430 pub fn bit_is_clear(&self) -> bool {
431 !self.bit()
432 }
433 #[doc = r" Returns `true` if the bit is set (1)"]
434 #[inline]
435 pub fn bit_is_set(&self) -> bool {
436 self.bit()
437 }
438 #[doc = r" Value of the field as raw bits"]
439 #[inline]
440 pub fn bit(&self) -> bool {
441 match *self {
442 LKR::_0 => false,
443 LKR::_1 => true,
444 }
445 }
446 #[allow(missing_docs)]
447 #[doc(hidden)]
448 #[inline]
449 pub fn _from(value: bool) -> LKR {
450 match value {
451 false => LKR::_0,
452 true => LKR::_1,
453 }
454 }
455 #[doc = "Checks if the value of the field is `_0`"]
456 #[inline]
457 pub fn is_0(&self) -> bool {
458 *self == LKR::_0
459 }
460 #[doc = "Checks if the value of the field is `_1`"]
461 #[inline]
462 pub fn is_1(&self) -> bool {
463 *self == LKR::_1
464 }
465}
466#[doc = "Possible values of the field `IRQC`"]
467#[derive(Clone, Copy, Debug, PartialEq)]
468pub enum IRQCR {
469 #[doc = "Interrupt Status Flag (ISF) is disabled."]
470 _0000,
471 #[doc = "ISF flag and DMA request on rising edge."]
472 _0001,
473 #[doc = "ISF flag and DMA request on falling edge."]
474 _0010,
475 #[doc = "ISF flag and DMA request on either edge."]
476 _0011,
477 #[doc = "ISF flag and Interrupt when logic 0."]
478 _1000,
479 #[doc = "ISF flag and Interrupt on rising-edge."]
480 _1001,
481 #[doc = "ISF flag and Interrupt on falling-edge."]
482 _1010,
483 #[doc = "ISF flag and Interrupt on either edge."]
484 _1011,
485 #[doc = "ISF flag and Interrupt when logic 1."]
486 _1100,
487 #[doc = r" Reserved"]
488 _Reserved(u8),
489}
490impl IRQCR {
491 #[doc = r" Value of the field as raw bits"]
492 #[inline]
493 pub fn bits(&self) -> u8 {
494 match *self {
495 IRQCR::_0000 => 0,
496 IRQCR::_0001 => 1,
497 IRQCR::_0010 => 2,
498 IRQCR::_0011 => 3,
499 IRQCR::_1000 => 8,
500 IRQCR::_1001 => 9,
501 IRQCR::_1010 => 10,
502 IRQCR::_1011 => 11,
503 IRQCR::_1100 => 12,
504 IRQCR::_Reserved(bits) => bits,
505 }
506 }
507 #[allow(missing_docs)]
508 #[doc(hidden)]
509 #[inline]
510 pub fn _from(value: u8) -> IRQCR {
511 match value {
512 0 => IRQCR::_0000,
513 1 => IRQCR::_0001,
514 2 => IRQCR::_0010,
515 3 => IRQCR::_0011,
516 8 => IRQCR::_1000,
517 9 => IRQCR::_1001,
518 10 => IRQCR::_1010,
519 11 => IRQCR::_1011,
520 12 => IRQCR::_1100,
521 i => IRQCR::_Reserved(i),
522 }
523 }
524 #[doc = "Checks if the value of the field is `_0000`"]
525 #[inline]
526 pub fn is_0000(&self) -> bool {
527 *self == IRQCR::_0000
528 }
529 #[doc = "Checks if the value of the field is `_0001`"]
530 #[inline]
531 pub fn is_0001(&self) -> bool {
532 *self == IRQCR::_0001
533 }
534 #[doc = "Checks if the value of the field is `_0010`"]
535 #[inline]
536 pub fn is_0010(&self) -> bool {
537 *self == IRQCR::_0010
538 }
539 #[doc = "Checks if the value of the field is `_0011`"]
540 #[inline]
541 pub fn is_0011(&self) -> bool {
542 *self == IRQCR::_0011
543 }
544 #[doc = "Checks if the value of the field is `_1000`"]
545 #[inline]
546 pub fn is_1000(&self) -> bool {
547 *self == IRQCR::_1000
548 }
549 #[doc = "Checks if the value of the field is `_1001`"]
550 #[inline]
551 pub fn is_1001(&self) -> bool {
552 *self == IRQCR::_1001
553 }
554 #[doc = "Checks if the value of the field is `_1010`"]
555 #[inline]
556 pub fn is_1010(&self) -> bool {
557 *self == IRQCR::_1010
558 }
559 #[doc = "Checks if the value of the field is `_1011`"]
560 #[inline]
561 pub fn is_1011(&self) -> bool {
562 *self == IRQCR::_1011
563 }
564 #[doc = "Checks if the value of the field is `_1100`"]
565 #[inline]
566 pub fn is_1100(&self) -> bool {
567 *self == IRQCR::_1100
568 }
569}
570#[doc = "Possible values of the field `ISF`"]
571#[derive(Clone, Copy, Debug, PartialEq)]
572pub enum ISFR {
573 #[doc = "Configured interrupt is not detected."]
574 _0,
575 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
576 _1,
577}
578impl ISFR {
579 #[doc = r" Returns `true` if the bit is clear (0)"]
580 #[inline]
581 pub fn bit_is_clear(&self) -> bool {
582 !self.bit()
583 }
584 #[doc = r" Returns `true` if the bit is set (1)"]
585 #[inline]
586 pub fn bit_is_set(&self) -> bool {
587 self.bit()
588 }
589 #[doc = r" Value of the field as raw bits"]
590 #[inline]
591 pub fn bit(&self) -> bool {
592 match *self {
593 ISFR::_0 => false,
594 ISFR::_1 => true,
595 }
596 }
597 #[allow(missing_docs)]
598 #[doc(hidden)]
599 #[inline]
600 pub fn _from(value: bool) -> ISFR {
601 match value {
602 false => ISFR::_0,
603 true => ISFR::_1,
604 }
605 }
606 #[doc = "Checks if the value of the field is `_0`"]
607 #[inline]
608 pub fn is_0(&self) -> bool {
609 *self == ISFR::_0
610 }
611 #[doc = "Checks if the value of the field is `_1`"]
612 #[inline]
613 pub fn is_1(&self) -> bool {
614 *self == ISFR::_1
615 }
616}
617#[doc = "Values that can be written to the field `PS`"]
618pub enum PSW {
619 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
620 _0,
621 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
622 _1,
623}
624impl PSW {
625 #[allow(missing_docs)]
626 #[doc(hidden)]
627 #[inline]
628 pub fn _bits(&self) -> bool {
629 match *self {
630 PSW::_0 => false,
631 PSW::_1 => true,
632 }
633 }
634}
635#[doc = r" Proxy"]
636pub struct _PSW<'a> {
637 w: &'a mut W,
638}
639impl<'a> _PSW<'a> {
640 #[doc = r" Writes `variant` to the field"]
641 #[inline]
642 pub fn variant(self, variant: PSW) -> &'a mut W {
643 {
644 self.bit(variant._bits())
645 }
646 }
647 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
648 #[inline]
649 pub fn _0(self) -> &'a mut W {
650 self.variant(PSW::_0)
651 }
652 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
653 #[inline]
654 pub fn _1(self) -> &'a mut W {
655 self.variant(PSW::_1)
656 }
657 #[doc = r" Sets the field bit"]
658 pub fn set_bit(self) -> &'a mut W {
659 self.bit(true)
660 }
661 #[doc = r" Clears the field bit"]
662 pub fn clear_bit(self) -> &'a mut W {
663 self.bit(false)
664 }
665 #[doc = r" Writes raw bits to the field"]
666 #[inline]
667 pub fn bit(self, value: bool) -> &'a mut W {
668 const MASK: bool = true;
669 const OFFSET: u8 = 0;
670 self.w.bits &= !((MASK as u32) << OFFSET);
671 self.w.bits |= ((value & MASK) as u32) << OFFSET;
672 self.w
673 }
674}
675#[doc = "Values that can be written to the field `PE`"]
676pub enum PEW {
677 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
678 _0,
679 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
680 _1,
681}
682impl PEW {
683 #[allow(missing_docs)]
684 #[doc(hidden)]
685 #[inline]
686 pub fn _bits(&self) -> bool {
687 match *self {
688 PEW::_0 => false,
689 PEW::_1 => true,
690 }
691 }
692}
693#[doc = r" Proxy"]
694pub struct _PEW<'a> {
695 w: &'a mut W,
696}
697impl<'a> _PEW<'a> {
698 #[doc = r" Writes `variant` to the field"]
699 #[inline]
700 pub fn variant(self, variant: PEW) -> &'a mut W {
701 {
702 self.bit(variant._bits())
703 }
704 }
705 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
706 #[inline]
707 pub fn _0(self) -> &'a mut W {
708 self.variant(PEW::_0)
709 }
710 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
711 #[inline]
712 pub fn _1(self) -> &'a mut W {
713 self.variant(PEW::_1)
714 }
715 #[doc = r" Sets the field bit"]
716 pub fn set_bit(self) -> &'a mut W {
717 self.bit(true)
718 }
719 #[doc = r" Clears the field bit"]
720 pub fn clear_bit(self) -> &'a mut W {
721 self.bit(false)
722 }
723 #[doc = r" Writes raw bits to the field"]
724 #[inline]
725 pub fn bit(self, value: bool) -> &'a mut W {
726 const MASK: bool = true;
727 const OFFSET: u8 = 1;
728 self.w.bits &= !((MASK as u32) << OFFSET);
729 self.w.bits |= ((value & MASK) as u32) << OFFSET;
730 self.w
731 }
732}
733#[doc = "Values that can be written to the field `SRE`"]
734pub enum SREW {
735 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
736 _0,
737 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
738 _1,
739}
740impl SREW {
741 #[allow(missing_docs)]
742 #[doc(hidden)]
743 #[inline]
744 pub fn _bits(&self) -> bool {
745 match *self {
746 SREW::_0 => false,
747 SREW::_1 => true,
748 }
749 }
750}
751#[doc = r" Proxy"]
752pub struct _SREW<'a> {
753 w: &'a mut W,
754}
755impl<'a> _SREW<'a> {
756 #[doc = r" Writes `variant` to the field"]
757 #[inline]
758 pub fn variant(self, variant: SREW) -> &'a mut W {
759 {
760 self.bit(variant._bits())
761 }
762 }
763 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
764 #[inline]
765 pub fn _0(self) -> &'a mut W {
766 self.variant(SREW::_0)
767 }
768 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
769 #[inline]
770 pub fn _1(self) -> &'a mut W {
771 self.variant(SREW::_1)
772 }
773 #[doc = r" Sets the field bit"]
774 pub fn set_bit(self) -> &'a mut W {
775 self.bit(true)
776 }
777 #[doc = r" Clears the field bit"]
778 pub fn clear_bit(self) -> &'a mut W {
779 self.bit(false)
780 }
781 #[doc = r" Writes raw bits to the field"]
782 #[inline]
783 pub fn bit(self, value: bool) -> &'a mut W {
784 const MASK: bool = true;
785 const OFFSET: u8 = 2;
786 self.w.bits &= !((MASK as u32) << OFFSET);
787 self.w.bits |= ((value & MASK) as u32) << OFFSET;
788 self.w
789 }
790}
791#[doc = "Values that can be written to the field `ODE`"]
792pub enum ODEW {
793 #[doc = "Open drain output is disabled on the corresponding pin."]
794 _0,
795 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
796 _1,
797}
798impl ODEW {
799 #[allow(missing_docs)]
800 #[doc(hidden)]
801 #[inline]
802 pub fn _bits(&self) -> bool {
803 match *self {
804 ODEW::_0 => false,
805 ODEW::_1 => true,
806 }
807 }
808}
809#[doc = r" Proxy"]
810pub struct _ODEW<'a> {
811 w: &'a mut W,
812}
813impl<'a> _ODEW<'a> {
814 #[doc = r" Writes `variant` to the field"]
815 #[inline]
816 pub fn variant(self, variant: ODEW) -> &'a mut W {
817 {
818 self.bit(variant._bits())
819 }
820 }
821 #[doc = "Open drain output is disabled on the corresponding pin."]
822 #[inline]
823 pub fn _0(self) -> &'a mut W {
824 self.variant(ODEW::_0)
825 }
826 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
827 #[inline]
828 pub fn _1(self) -> &'a mut W {
829 self.variant(ODEW::_1)
830 }
831 #[doc = r" Sets the field bit"]
832 pub fn set_bit(self) -> &'a mut W {
833 self.bit(true)
834 }
835 #[doc = r" Clears the field bit"]
836 pub fn clear_bit(self) -> &'a mut W {
837 self.bit(false)
838 }
839 #[doc = r" Writes raw bits to the field"]
840 #[inline]
841 pub fn bit(self, value: bool) -> &'a mut W {
842 const MASK: bool = true;
843 const OFFSET: u8 = 5;
844 self.w.bits &= !((MASK as u32) << OFFSET);
845 self.w.bits |= ((value & MASK) as u32) << OFFSET;
846 self.w
847 }
848}
849#[doc = "Values that can be written to the field `MUX`"]
850pub enum MUXW {
851 #[doc = "Pin disabled (analog)."]
852 _000,
853 #[doc = "Alternative 1 (GPIO)."]
854 _001,
855 #[doc = "Alternative 2 (chip-specific)."]
856 _010,
857 #[doc = "Alternative 3 (chip-specific)."]
858 _011,
859 #[doc = "Alternative 4 (chip-specific)."]
860 _100,
861 #[doc = "Alternative 5 (chip-specific)."]
862 _101,
863 #[doc = "Alternative 6 (chip-specific)."]
864 _110,
865 #[doc = "Alternative 7 (chip-specific)."]
866 _111,
867}
868impl MUXW {
869 #[allow(missing_docs)]
870 #[doc(hidden)]
871 #[inline]
872 pub fn _bits(&self) -> u8 {
873 match *self {
874 MUXW::_000 => 0,
875 MUXW::_001 => 1,
876 MUXW::_010 => 2,
877 MUXW::_011 => 3,
878 MUXW::_100 => 4,
879 MUXW::_101 => 5,
880 MUXW::_110 => 6,
881 MUXW::_111 => 7,
882 }
883 }
884}
885#[doc = r" Proxy"]
886pub struct _MUXW<'a> {
887 w: &'a mut W,
888}
889impl<'a> _MUXW<'a> {
890 #[doc = r" Writes `variant` to the field"]
891 #[inline]
892 pub fn variant(self, variant: MUXW) -> &'a mut W {
893 {
894 self.bits(variant._bits())
895 }
896 }
897 #[doc = "Pin disabled (analog)."]
898 #[inline]
899 pub fn _000(self) -> &'a mut W {
900 self.variant(MUXW::_000)
901 }
902 #[doc = "Alternative 1 (GPIO)."]
903 #[inline]
904 pub fn _001(self) -> &'a mut W {
905 self.variant(MUXW::_001)
906 }
907 #[doc = "Alternative 2 (chip-specific)."]
908 #[inline]
909 pub fn _010(self) -> &'a mut W {
910 self.variant(MUXW::_010)
911 }
912 #[doc = "Alternative 3 (chip-specific)."]
913 #[inline]
914 pub fn _011(self) -> &'a mut W {
915 self.variant(MUXW::_011)
916 }
917 #[doc = "Alternative 4 (chip-specific)."]
918 #[inline]
919 pub fn _100(self) -> &'a mut W {
920 self.variant(MUXW::_100)
921 }
922 #[doc = "Alternative 5 (chip-specific)."]
923 #[inline]
924 pub fn _101(self) -> &'a mut W {
925 self.variant(MUXW::_101)
926 }
927 #[doc = "Alternative 6 (chip-specific)."]
928 #[inline]
929 pub fn _110(self) -> &'a mut W {
930 self.variant(MUXW::_110)
931 }
932 #[doc = "Alternative 7 (chip-specific)."]
933 #[inline]
934 pub fn _111(self) -> &'a mut W {
935 self.variant(MUXW::_111)
936 }
937 #[doc = r" Writes raw bits to the field"]
938 #[inline]
939 pub fn bits(self, value: u8) -> &'a mut W {
940 const MASK: u8 = 7;
941 const OFFSET: u8 = 8;
942 self.w.bits &= !((MASK as u32) << OFFSET);
943 self.w.bits |= ((value & MASK) as u32) << OFFSET;
944 self.w
945 }
946}
947#[doc = "Values that can be written to the field `LK`"]
948pub enum LKW {
949 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
950 _0,
951 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
952 _1,
953}
954impl LKW {
955 #[allow(missing_docs)]
956 #[doc(hidden)]
957 #[inline]
958 pub fn _bits(&self) -> bool {
959 match *self {
960 LKW::_0 => false,
961 LKW::_1 => true,
962 }
963 }
964}
965#[doc = r" Proxy"]
966pub struct _LKW<'a> {
967 w: &'a mut W,
968}
969impl<'a> _LKW<'a> {
970 #[doc = r" Writes `variant` to the field"]
971 #[inline]
972 pub fn variant(self, variant: LKW) -> &'a mut W {
973 {
974 self.bit(variant._bits())
975 }
976 }
977 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
978 #[inline]
979 pub fn _0(self) -> &'a mut W {
980 self.variant(LKW::_0)
981 }
982 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
983 #[inline]
984 pub fn _1(self) -> &'a mut W {
985 self.variant(LKW::_1)
986 }
987 #[doc = r" Sets the field bit"]
988 pub fn set_bit(self) -> &'a mut W {
989 self.bit(true)
990 }
991 #[doc = r" Clears the field bit"]
992 pub fn clear_bit(self) -> &'a mut W {
993 self.bit(false)
994 }
995 #[doc = r" Writes raw bits to the field"]
996 #[inline]
997 pub fn bit(self, value: bool) -> &'a mut W {
998 const MASK: bool = true;
999 const OFFSET: u8 = 15;
1000 self.w.bits &= !((MASK as u32) << OFFSET);
1001 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1002 self.w
1003 }
1004}
1005#[doc = "Values that can be written to the field `IRQC`"]
1006pub enum IRQCW {
1007 #[doc = "Interrupt Status Flag (ISF) is disabled."]
1008 _0000,
1009 #[doc = "ISF flag and DMA request on rising edge."]
1010 _0001,
1011 #[doc = "ISF flag and DMA request on falling edge."]
1012 _0010,
1013 #[doc = "ISF flag and DMA request on either edge."]
1014 _0011,
1015 #[doc = "ISF flag and Interrupt when logic 0."]
1016 _1000,
1017 #[doc = "ISF flag and Interrupt on rising-edge."]
1018 _1001,
1019 #[doc = "ISF flag and Interrupt on falling-edge."]
1020 _1010,
1021 #[doc = "ISF flag and Interrupt on either edge."]
1022 _1011,
1023 #[doc = "ISF flag and Interrupt when logic 1."]
1024 _1100,
1025}
1026impl IRQCW {
1027 #[allow(missing_docs)]
1028 #[doc(hidden)]
1029 #[inline]
1030 pub fn _bits(&self) -> u8 {
1031 match *self {
1032 IRQCW::_0000 => 0,
1033 IRQCW::_0001 => 1,
1034 IRQCW::_0010 => 2,
1035 IRQCW::_0011 => 3,
1036 IRQCW::_1000 => 8,
1037 IRQCW::_1001 => 9,
1038 IRQCW::_1010 => 10,
1039 IRQCW::_1011 => 11,
1040 IRQCW::_1100 => 12,
1041 }
1042 }
1043}
1044#[doc = r" Proxy"]
1045pub struct _IRQCW<'a> {
1046 w: &'a mut W,
1047}
1048impl<'a> _IRQCW<'a> {
1049 #[doc = r" Writes `variant` to the field"]
1050 #[inline]
1051 pub fn variant(self, variant: IRQCW) -> &'a mut W {
1052 unsafe { self.bits(variant._bits()) }
1053 }
1054 #[doc = "Interrupt Status Flag (ISF) is disabled."]
1055 #[inline]
1056 pub fn _0000(self) -> &'a mut W {
1057 self.variant(IRQCW::_0000)
1058 }
1059 #[doc = "ISF flag and DMA request on rising edge."]
1060 #[inline]
1061 pub fn _0001(self) -> &'a mut W {
1062 self.variant(IRQCW::_0001)
1063 }
1064 #[doc = "ISF flag and DMA request on falling edge."]
1065 #[inline]
1066 pub fn _0010(self) -> &'a mut W {
1067 self.variant(IRQCW::_0010)
1068 }
1069 #[doc = "ISF flag and DMA request on either edge."]
1070 #[inline]
1071 pub fn _0011(self) -> &'a mut W {
1072 self.variant(IRQCW::_0011)
1073 }
1074 #[doc = "ISF flag and Interrupt when logic 0."]
1075 #[inline]
1076 pub fn _1000(self) -> &'a mut W {
1077 self.variant(IRQCW::_1000)
1078 }
1079 #[doc = "ISF flag and Interrupt on rising-edge."]
1080 #[inline]
1081 pub fn _1001(self) -> &'a mut W {
1082 self.variant(IRQCW::_1001)
1083 }
1084 #[doc = "ISF flag and Interrupt on falling-edge."]
1085 #[inline]
1086 pub fn _1010(self) -> &'a mut W {
1087 self.variant(IRQCW::_1010)
1088 }
1089 #[doc = "ISF flag and Interrupt on either edge."]
1090 #[inline]
1091 pub fn _1011(self) -> &'a mut W {
1092 self.variant(IRQCW::_1011)
1093 }
1094 #[doc = "ISF flag and Interrupt when logic 1."]
1095 #[inline]
1096 pub fn _1100(self) -> &'a mut W {
1097 self.variant(IRQCW::_1100)
1098 }
1099 #[doc = r" Writes raw bits to the field"]
1100 #[inline]
1101 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1102 const MASK: u8 = 15;
1103 const OFFSET: u8 = 16;
1104 self.w.bits &= !((MASK as u32) << OFFSET);
1105 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1106 self.w
1107 }
1108}
1109#[doc = "Values that can be written to the field `ISF`"]
1110pub enum ISFW {
1111 #[doc = "Configured interrupt is not detected."]
1112 _0,
1113 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1114 _1,
1115}
1116impl ISFW {
1117 #[allow(missing_docs)]
1118 #[doc(hidden)]
1119 #[inline]
1120 pub fn _bits(&self) -> bool {
1121 match *self {
1122 ISFW::_0 => false,
1123 ISFW::_1 => true,
1124 }
1125 }
1126}
1127#[doc = r" Proxy"]
1128pub struct _ISFW<'a> {
1129 w: &'a mut W,
1130}
1131impl<'a> _ISFW<'a> {
1132 #[doc = r" Writes `variant` to the field"]
1133 #[inline]
1134 pub fn variant(self, variant: ISFW) -> &'a mut W {
1135 {
1136 self.bit(variant._bits())
1137 }
1138 }
1139 #[doc = "Configured interrupt is not detected."]
1140 #[inline]
1141 pub fn _0(self) -> &'a mut W {
1142 self.variant(ISFW::_0)
1143 }
1144 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1145 #[inline]
1146 pub fn _1(self) -> &'a mut W {
1147 self.variant(ISFW::_1)
1148 }
1149 #[doc = r" Sets the field bit"]
1150 pub fn set_bit(self) -> &'a mut W {
1151 self.bit(true)
1152 }
1153 #[doc = r" Clears the field bit"]
1154 pub fn clear_bit(self) -> &'a mut W {
1155 self.bit(false)
1156 }
1157 #[doc = r" Writes raw bits to the field"]
1158 #[inline]
1159 pub fn bit(self, value: bool) -> &'a mut W {
1160 const MASK: bool = true;
1161 const OFFSET: u8 = 24;
1162 self.w.bits &= !((MASK as u32) << OFFSET);
1163 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1164 self.w
1165 }
1166}
1167impl R {
1168 #[doc = r" Value of the register as raw bits"]
1169 #[inline]
1170 pub fn bits(&self) -> u32 {
1171 self.bits
1172 }
1173 #[doc = "Bit 0 - Pull Select"]
1174 #[inline]
1175 pub fn ps(&self) -> PSR {
1176 PSR::_from({
1177 const MASK: bool = true;
1178 const OFFSET: u8 = 0;
1179 ((self.bits >> OFFSET) & MASK as u32) != 0
1180 })
1181 }
1182 #[doc = "Bit 1 - Pull Enable"]
1183 #[inline]
1184 pub fn pe(&self) -> PER {
1185 PER::_from({
1186 const MASK: bool = true;
1187 const OFFSET: u8 = 1;
1188 ((self.bits >> OFFSET) & MASK as u32) != 0
1189 })
1190 }
1191 #[doc = "Bit 2 - Slew Rate Enable"]
1192 #[inline]
1193 pub fn sre(&self) -> SRER {
1194 SRER::_from({
1195 const MASK: bool = true;
1196 const OFFSET: u8 = 2;
1197 ((self.bits >> OFFSET) & MASK as u32) != 0
1198 })
1199 }
1200 #[doc = "Bit 4 - Passive Filter Enable"]
1201 #[inline]
1202 pub fn pfe(&self) -> PFER {
1203 PFER::_from({
1204 const MASK: bool = true;
1205 const OFFSET: u8 = 4;
1206 ((self.bits >> OFFSET) & MASK as u32) != 0
1207 })
1208 }
1209 #[doc = "Bit 5 - Open Drain Enable"]
1210 #[inline]
1211 pub fn ode(&self) -> ODER {
1212 ODER::_from({
1213 const MASK: bool = true;
1214 const OFFSET: u8 = 5;
1215 ((self.bits >> OFFSET) & MASK as u32) != 0
1216 })
1217 }
1218 #[doc = "Bit 6 - Drive Strength Enable"]
1219 #[inline]
1220 pub fn dse(&self) -> DSER {
1221 DSER::_from({
1222 const MASK: bool = true;
1223 const OFFSET: u8 = 6;
1224 ((self.bits >> OFFSET) & MASK as u32) != 0
1225 })
1226 }
1227 #[doc = "Bits 8:10 - Pin Mux Control"]
1228 #[inline]
1229 pub fn mux(&self) -> MUXR {
1230 MUXR::_from({
1231 const MASK: u8 = 7;
1232 const OFFSET: u8 = 8;
1233 ((self.bits >> OFFSET) & MASK as u32) as u8
1234 })
1235 }
1236 #[doc = "Bit 15 - Lock Register"]
1237 #[inline]
1238 pub fn lk(&self) -> LKR {
1239 LKR::_from({
1240 const MASK: bool = true;
1241 const OFFSET: u8 = 15;
1242 ((self.bits >> OFFSET) & MASK as u32) != 0
1243 })
1244 }
1245 #[doc = "Bits 16:19 - Interrupt Configuration"]
1246 #[inline]
1247 pub fn irqc(&self) -> IRQCR {
1248 IRQCR::_from({
1249 const MASK: u8 = 15;
1250 const OFFSET: u8 = 16;
1251 ((self.bits >> OFFSET) & MASK as u32) as u8
1252 })
1253 }
1254 #[doc = "Bit 24 - Interrupt Status Flag"]
1255 #[inline]
1256 pub fn isf(&self) -> ISFR {
1257 ISFR::_from({
1258 const MASK: bool = true;
1259 const OFFSET: u8 = 24;
1260 ((self.bits >> OFFSET) & MASK as u32) != 0
1261 })
1262 }
1263}
1264impl W {
1265 #[doc = r" Reset value of the register"]
1266 #[inline]
1267 pub fn reset_value() -> W {
1268 W { bits: 0 }
1269 }
1270 #[doc = r" Writes raw bits to the register"]
1271 #[inline]
1272 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1273 self.bits = bits;
1274 self
1275 }
1276 #[doc = "Bit 0 - Pull Select"]
1277 #[inline]
1278 pub fn ps(&mut self) -> _PSW {
1279 _PSW { w: self }
1280 }
1281 #[doc = "Bit 1 - Pull Enable"]
1282 #[inline]
1283 pub fn pe(&mut self) -> _PEW {
1284 _PEW { w: self }
1285 }
1286 #[doc = "Bit 2 - Slew Rate Enable"]
1287 #[inline]
1288 pub fn sre(&mut self) -> _SREW {
1289 _SREW { w: self }
1290 }
1291 #[doc = "Bit 5 - Open Drain Enable"]
1292 #[inline]
1293 pub fn ode(&mut self) -> _ODEW {
1294 _ODEW { w: self }
1295 }
1296 #[doc = "Bits 8:10 - Pin Mux Control"]
1297 #[inline]
1298 pub fn mux(&mut self) -> _MUXW {
1299 _MUXW { w: self }
1300 }
1301 #[doc = "Bit 15 - Lock Register"]
1302 #[inline]
1303 pub fn lk(&mut self) -> _LKW {
1304 _LKW { w: self }
1305 }
1306 #[doc = "Bits 16:19 - Interrupt Configuration"]
1307 #[inline]
1308 pub fn irqc(&mut self) -> _IRQCW {
1309 _IRQCW { w: self }
1310 }
1311 #[doc = "Bit 24 - Interrupt Status Flag"]
1312 #[inline]
1313 pub fn isf(&mut self) -> _ISFW {
1314 _ISFW { w: self }
1315 }
1316}