1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::TCR4 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `FSD`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum FSDR {
48 #[doc = "Frame sync is generated externally in Slave mode."]
49 _0,
50 #[doc = "Frame sync is generated internally in Master mode."]
51 _1,
52}
53impl FSDR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 FSDR::_0 => false,
69 FSDR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> FSDR {
76 match value {
77 false => FSDR::_0,
78 true => FSDR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == FSDR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == FSDR::_1
90 }
91}
92#[doc = "Possible values of the field `FSP`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum FSPR {
95 #[doc = "Frame sync is active high."]
96 _0,
97 #[doc = "Frame sync is active low."]
98 _1,
99}
100impl FSPR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 FSPR::_0 => false,
116 FSPR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> FSPR {
123 match value {
124 false => FSPR::_0,
125 true => FSPR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == FSPR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == FSPR::_1
137 }
138}
139#[doc = "Possible values of the field `ONDEM`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum ONDEMR {
142 #[doc = "Internal frame sync is generated continuously."]
143 _0,
144 #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."]
145 _1,
146}
147impl ONDEMR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 ONDEMR::_0 => false,
163 ONDEMR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> ONDEMR {
170 match value {
171 false => ONDEMR::_0,
172 true => ONDEMR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == ONDEMR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == ONDEMR::_1
184 }
185}
186#[doc = "Possible values of the field `FSE`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum FSER {
189 #[doc = "Frame sync asserts with the first bit of the frame."]
190 _0,
191 #[doc = "Frame sync asserts one bit before the first bit of the frame."]
192 _1,
193}
194impl FSER {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 FSER::_0 => false,
210 FSER::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> FSER {
217 match value {
218 false => FSER::_0,
219 true => FSER::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == FSER::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == FSER::_1
231 }
232}
233#[doc = "Possible values of the field `MF`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum MFR {
236 #[doc = "LSB is transmitted first."]
237 _0,
238 #[doc = "MSB is transmitted first."]
239 _1,
240}
241impl MFR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 MFR::_0 => false,
257 MFR::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> MFR {
264 match value {
265 false => MFR::_0,
266 true => MFR::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == MFR::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == MFR::_1
278 }
279}
280#[doc = r" Value of the field"]
281pub struct SYWDR {
282 bits: u8,
283}
284impl SYWDR {
285 #[doc = r" Value of the field as raw bits"]
286 #[inline]
287 pub fn bits(&self) -> u8 {
288 self.bits
289 }
290}
291#[doc = r" Value of the field"]
292pub struct FRSZR {
293 bits: u8,
294}
295impl FRSZR {
296 #[doc = r" Value of the field as raw bits"]
297 #[inline]
298 pub fn bits(&self) -> u8 {
299 self.bits
300 }
301}
302#[doc = "Possible values of the field `FPACK`"]
303#[derive(Clone, Copy, Debug, PartialEq)]
304pub enum FPACKR {
305 #[doc = "FIFO packing is disabled"]
306 _00,
307 #[doc = "8-bit FIFO packing is enabled"]
308 _10,
309 #[doc = "16-bit FIFO packing is enabled"]
310 _11,
311 #[doc = r" Reserved"]
312 _Reserved(u8),
313}
314impl FPACKR {
315 #[doc = r" Value of the field as raw bits"]
316 #[inline]
317 pub fn bits(&self) -> u8 {
318 match *self {
319 FPACKR::_00 => 0,
320 FPACKR::_10 => 2,
321 FPACKR::_11 => 3,
322 FPACKR::_Reserved(bits) => bits,
323 }
324 }
325 #[allow(missing_docs)]
326 #[doc(hidden)]
327 #[inline]
328 pub fn _from(value: u8) -> FPACKR {
329 match value {
330 0 => FPACKR::_00,
331 2 => FPACKR::_10,
332 3 => FPACKR::_11,
333 i => FPACKR::_Reserved(i),
334 }
335 }
336 #[doc = "Checks if the value of the field is `_00`"]
337 #[inline]
338 pub fn is_00(&self) -> bool {
339 *self == FPACKR::_00
340 }
341 #[doc = "Checks if the value of the field is `_10`"]
342 #[inline]
343 pub fn is_10(&self) -> bool {
344 *self == FPACKR::_10
345 }
346 #[doc = "Checks if the value of the field is `_11`"]
347 #[inline]
348 pub fn is_11(&self) -> bool {
349 *self == FPACKR::_11
350 }
351}
352#[doc = "Possible values of the field `FCOMB`"]
353#[derive(Clone, Copy, Debug, PartialEq)]
354pub enum FCOMBR {
355 #[doc = "FIFO combine mode disabled."]
356 _00,
357 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."]
358 _01,
359 #[doc = "FIFO combine mode enabled on FIFO writes (by software)."]
360 _10,
361 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."]
362 _11,
363}
364impl FCOMBR {
365 #[doc = r" Value of the field as raw bits"]
366 #[inline]
367 pub fn bits(&self) -> u8 {
368 match *self {
369 FCOMBR::_00 => 0,
370 FCOMBR::_01 => 1,
371 FCOMBR::_10 => 2,
372 FCOMBR::_11 => 3,
373 }
374 }
375 #[allow(missing_docs)]
376 #[doc(hidden)]
377 #[inline]
378 pub fn _from(value: u8) -> FCOMBR {
379 match value {
380 0 => FCOMBR::_00,
381 1 => FCOMBR::_01,
382 2 => FCOMBR::_10,
383 3 => FCOMBR::_11,
384 _ => unreachable!(),
385 }
386 }
387 #[doc = "Checks if the value of the field is `_00`"]
388 #[inline]
389 pub fn is_00(&self) -> bool {
390 *self == FCOMBR::_00
391 }
392 #[doc = "Checks if the value of the field is `_01`"]
393 #[inline]
394 pub fn is_01(&self) -> bool {
395 *self == FCOMBR::_01
396 }
397 #[doc = "Checks if the value of the field is `_10`"]
398 #[inline]
399 pub fn is_10(&self) -> bool {
400 *self == FCOMBR::_10
401 }
402 #[doc = "Checks if the value of the field is `_11`"]
403 #[inline]
404 pub fn is_11(&self) -> bool {
405 *self == FCOMBR::_11
406 }
407}
408#[doc = "Possible values of the field `FCONT`"]
409#[derive(Clone, Copy, Debug, PartialEq)]
410pub enum FCONTR {
411 #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."]
412 _0,
413 #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."]
414 _1,
415}
416impl FCONTR {
417 #[doc = r" Returns `true` if the bit is clear (0)"]
418 #[inline]
419 pub fn bit_is_clear(&self) -> bool {
420 !self.bit()
421 }
422 #[doc = r" Returns `true` if the bit is set (1)"]
423 #[inline]
424 pub fn bit_is_set(&self) -> bool {
425 self.bit()
426 }
427 #[doc = r" Value of the field as raw bits"]
428 #[inline]
429 pub fn bit(&self) -> bool {
430 match *self {
431 FCONTR::_0 => false,
432 FCONTR::_1 => true,
433 }
434 }
435 #[allow(missing_docs)]
436 #[doc(hidden)]
437 #[inline]
438 pub fn _from(value: bool) -> FCONTR {
439 match value {
440 false => FCONTR::_0,
441 true => FCONTR::_1,
442 }
443 }
444 #[doc = "Checks if the value of the field is `_0`"]
445 #[inline]
446 pub fn is_0(&self) -> bool {
447 *self == FCONTR::_0
448 }
449 #[doc = "Checks if the value of the field is `_1`"]
450 #[inline]
451 pub fn is_1(&self) -> bool {
452 *self == FCONTR::_1
453 }
454}
455#[doc = "Values that can be written to the field `FSD`"]
456pub enum FSDW {
457 #[doc = "Frame sync is generated externally in Slave mode."]
458 _0,
459 #[doc = "Frame sync is generated internally in Master mode."]
460 _1,
461}
462impl FSDW {
463 #[allow(missing_docs)]
464 #[doc(hidden)]
465 #[inline]
466 pub fn _bits(&self) -> bool {
467 match *self {
468 FSDW::_0 => false,
469 FSDW::_1 => true,
470 }
471 }
472}
473#[doc = r" Proxy"]
474pub struct _FSDW<'a> {
475 w: &'a mut W,
476}
477impl<'a> _FSDW<'a> {
478 #[doc = r" Writes `variant` to the field"]
479 #[inline]
480 pub fn variant(self, variant: FSDW) -> &'a mut W {
481 {
482 self.bit(variant._bits())
483 }
484 }
485 #[doc = "Frame sync is generated externally in Slave mode."]
486 #[inline]
487 pub fn _0(self) -> &'a mut W {
488 self.variant(FSDW::_0)
489 }
490 #[doc = "Frame sync is generated internally in Master mode."]
491 #[inline]
492 pub fn _1(self) -> &'a mut W {
493 self.variant(FSDW::_1)
494 }
495 #[doc = r" Sets the field bit"]
496 pub fn set_bit(self) -> &'a mut W {
497 self.bit(true)
498 }
499 #[doc = r" Clears the field bit"]
500 pub fn clear_bit(self) -> &'a mut W {
501 self.bit(false)
502 }
503 #[doc = r" Writes raw bits to the field"]
504 #[inline]
505 pub fn bit(self, value: bool) -> &'a mut W {
506 const MASK: bool = true;
507 const OFFSET: u8 = 0;
508 self.w.bits &= !((MASK as u32) << OFFSET);
509 self.w.bits |= ((value & MASK) as u32) << OFFSET;
510 self.w
511 }
512}
513#[doc = "Values that can be written to the field `FSP`"]
514pub enum FSPW {
515 #[doc = "Frame sync is active high."]
516 _0,
517 #[doc = "Frame sync is active low."]
518 _1,
519}
520impl FSPW {
521 #[allow(missing_docs)]
522 #[doc(hidden)]
523 #[inline]
524 pub fn _bits(&self) -> bool {
525 match *self {
526 FSPW::_0 => false,
527 FSPW::_1 => true,
528 }
529 }
530}
531#[doc = r" Proxy"]
532pub struct _FSPW<'a> {
533 w: &'a mut W,
534}
535impl<'a> _FSPW<'a> {
536 #[doc = r" Writes `variant` to the field"]
537 #[inline]
538 pub fn variant(self, variant: FSPW) -> &'a mut W {
539 {
540 self.bit(variant._bits())
541 }
542 }
543 #[doc = "Frame sync is active high."]
544 #[inline]
545 pub fn _0(self) -> &'a mut W {
546 self.variant(FSPW::_0)
547 }
548 #[doc = "Frame sync is active low."]
549 #[inline]
550 pub fn _1(self) -> &'a mut W {
551 self.variant(FSPW::_1)
552 }
553 #[doc = r" Sets the field bit"]
554 pub fn set_bit(self) -> &'a mut W {
555 self.bit(true)
556 }
557 #[doc = r" Clears the field bit"]
558 pub fn clear_bit(self) -> &'a mut W {
559 self.bit(false)
560 }
561 #[doc = r" Writes raw bits to the field"]
562 #[inline]
563 pub fn bit(self, value: bool) -> &'a mut W {
564 const MASK: bool = true;
565 const OFFSET: u8 = 1;
566 self.w.bits &= !((MASK as u32) << OFFSET);
567 self.w.bits |= ((value & MASK) as u32) << OFFSET;
568 self.w
569 }
570}
571#[doc = "Values that can be written to the field `ONDEM`"]
572pub enum ONDEMW {
573 #[doc = "Internal frame sync is generated continuously."]
574 _0,
575 #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."]
576 _1,
577}
578impl ONDEMW {
579 #[allow(missing_docs)]
580 #[doc(hidden)]
581 #[inline]
582 pub fn _bits(&self) -> bool {
583 match *self {
584 ONDEMW::_0 => false,
585 ONDEMW::_1 => true,
586 }
587 }
588}
589#[doc = r" Proxy"]
590pub struct _ONDEMW<'a> {
591 w: &'a mut W,
592}
593impl<'a> _ONDEMW<'a> {
594 #[doc = r" Writes `variant` to the field"]
595 #[inline]
596 pub fn variant(self, variant: ONDEMW) -> &'a mut W {
597 {
598 self.bit(variant._bits())
599 }
600 }
601 #[doc = "Internal frame sync is generated continuously."]
602 #[inline]
603 pub fn _0(self) -> &'a mut W {
604 self.variant(ONDEMW::_0)
605 }
606 #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."]
607 #[inline]
608 pub fn _1(self) -> &'a mut W {
609 self.variant(ONDEMW::_1)
610 }
611 #[doc = r" Sets the field bit"]
612 pub fn set_bit(self) -> &'a mut W {
613 self.bit(true)
614 }
615 #[doc = r" Clears the field bit"]
616 pub fn clear_bit(self) -> &'a mut W {
617 self.bit(false)
618 }
619 #[doc = r" Writes raw bits to the field"]
620 #[inline]
621 pub fn bit(self, value: bool) -> &'a mut W {
622 const MASK: bool = true;
623 const OFFSET: u8 = 2;
624 self.w.bits &= !((MASK as u32) << OFFSET);
625 self.w.bits |= ((value & MASK) as u32) << OFFSET;
626 self.w
627 }
628}
629#[doc = "Values that can be written to the field `FSE`"]
630pub enum FSEW {
631 #[doc = "Frame sync asserts with the first bit of the frame."]
632 _0,
633 #[doc = "Frame sync asserts one bit before the first bit of the frame."]
634 _1,
635}
636impl FSEW {
637 #[allow(missing_docs)]
638 #[doc(hidden)]
639 #[inline]
640 pub fn _bits(&self) -> bool {
641 match *self {
642 FSEW::_0 => false,
643 FSEW::_1 => true,
644 }
645 }
646}
647#[doc = r" Proxy"]
648pub struct _FSEW<'a> {
649 w: &'a mut W,
650}
651impl<'a> _FSEW<'a> {
652 #[doc = r" Writes `variant` to the field"]
653 #[inline]
654 pub fn variant(self, variant: FSEW) -> &'a mut W {
655 {
656 self.bit(variant._bits())
657 }
658 }
659 #[doc = "Frame sync asserts with the first bit of the frame."]
660 #[inline]
661 pub fn _0(self) -> &'a mut W {
662 self.variant(FSEW::_0)
663 }
664 #[doc = "Frame sync asserts one bit before the first bit of the frame."]
665 #[inline]
666 pub fn _1(self) -> &'a mut W {
667 self.variant(FSEW::_1)
668 }
669 #[doc = r" Sets the field bit"]
670 pub fn set_bit(self) -> &'a mut W {
671 self.bit(true)
672 }
673 #[doc = r" Clears the field bit"]
674 pub fn clear_bit(self) -> &'a mut W {
675 self.bit(false)
676 }
677 #[doc = r" Writes raw bits to the field"]
678 #[inline]
679 pub fn bit(self, value: bool) -> &'a mut W {
680 const MASK: bool = true;
681 const OFFSET: u8 = 3;
682 self.w.bits &= !((MASK as u32) << OFFSET);
683 self.w.bits |= ((value & MASK) as u32) << OFFSET;
684 self.w
685 }
686}
687#[doc = "Values that can be written to the field `MF`"]
688pub enum MFW {
689 #[doc = "LSB is transmitted first."]
690 _0,
691 #[doc = "MSB is transmitted first."]
692 _1,
693}
694impl MFW {
695 #[allow(missing_docs)]
696 #[doc(hidden)]
697 #[inline]
698 pub fn _bits(&self) -> bool {
699 match *self {
700 MFW::_0 => false,
701 MFW::_1 => true,
702 }
703 }
704}
705#[doc = r" Proxy"]
706pub struct _MFW<'a> {
707 w: &'a mut W,
708}
709impl<'a> _MFW<'a> {
710 #[doc = r" Writes `variant` to the field"]
711 #[inline]
712 pub fn variant(self, variant: MFW) -> &'a mut W {
713 {
714 self.bit(variant._bits())
715 }
716 }
717 #[doc = "LSB is transmitted first."]
718 #[inline]
719 pub fn _0(self) -> &'a mut W {
720 self.variant(MFW::_0)
721 }
722 #[doc = "MSB is transmitted first."]
723 #[inline]
724 pub fn _1(self) -> &'a mut W {
725 self.variant(MFW::_1)
726 }
727 #[doc = r" Sets the field bit"]
728 pub fn set_bit(self) -> &'a mut W {
729 self.bit(true)
730 }
731 #[doc = r" Clears the field bit"]
732 pub fn clear_bit(self) -> &'a mut W {
733 self.bit(false)
734 }
735 #[doc = r" Writes raw bits to the field"]
736 #[inline]
737 pub fn bit(self, value: bool) -> &'a mut W {
738 const MASK: bool = true;
739 const OFFSET: u8 = 4;
740 self.w.bits &= !((MASK as u32) << OFFSET);
741 self.w.bits |= ((value & MASK) as u32) << OFFSET;
742 self.w
743 }
744}
745#[doc = r" Proxy"]
746pub struct _SYWDW<'a> {
747 w: &'a mut W,
748}
749impl<'a> _SYWDW<'a> {
750 #[doc = r" Writes raw bits to the field"]
751 #[inline]
752 pub unsafe fn bits(self, value: u8) -> &'a mut W {
753 const MASK: u8 = 31;
754 const OFFSET: u8 = 8;
755 self.w.bits &= !((MASK as u32) << OFFSET);
756 self.w.bits |= ((value & MASK) as u32) << OFFSET;
757 self.w
758 }
759}
760#[doc = r" Proxy"]
761pub struct _FRSZW<'a> {
762 w: &'a mut W,
763}
764impl<'a> _FRSZW<'a> {
765 #[doc = r" Writes raw bits to the field"]
766 #[inline]
767 pub unsafe fn bits(self, value: u8) -> &'a mut W {
768 const MASK: u8 = 31;
769 const OFFSET: u8 = 16;
770 self.w.bits &= !((MASK as u32) << OFFSET);
771 self.w.bits |= ((value & MASK) as u32) << OFFSET;
772 self.w
773 }
774}
775#[doc = "Values that can be written to the field `FPACK`"]
776pub enum FPACKW {
777 #[doc = "FIFO packing is disabled"]
778 _00,
779 #[doc = "8-bit FIFO packing is enabled"]
780 _10,
781 #[doc = "16-bit FIFO packing is enabled"]
782 _11,
783}
784impl FPACKW {
785 #[allow(missing_docs)]
786 #[doc(hidden)]
787 #[inline]
788 pub fn _bits(&self) -> u8 {
789 match *self {
790 FPACKW::_00 => 0,
791 FPACKW::_10 => 2,
792 FPACKW::_11 => 3,
793 }
794 }
795}
796#[doc = r" Proxy"]
797pub struct _FPACKW<'a> {
798 w: &'a mut W,
799}
800impl<'a> _FPACKW<'a> {
801 #[doc = r" Writes `variant` to the field"]
802 #[inline]
803 pub fn variant(self, variant: FPACKW) -> &'a mut W {
804 unsafe { self.bits(variant._bits()) }
805 }
806 #[doc = "FIFO packing is disabled"]
807 #[inline]
808 pub fn _00(self) -> &'a mut W {
809 self.variant(FPACKW::_00)
810 }
811 #[doc = "8-bit FIFO packing is enabled"]
812 #[inline]
813 pub fn _10(self) -> &'a mut W {
814 self.variant(FPACKW::_10)
815 }
816 #[doc = "16-bit FIFO packing is enabled"]
817 #[inline]
818 pub fn _11(self) -> &'a mut W {
819 self.variant(FPACKW::_11)
820 }
821 #[doc = r" Writes raw bits to the field"]
822 #[inline]
823 pub unsafe fn bits(self, value: u8) -> &'a mut W {
824 const MASK: u8 = 3;
825 const OFFSET: u8 = 24;
826 self.w.bits &= !((MASK as u32) << OFFSET);
827 self.w.bits |= ((value & MASK) as u32) << OFFSET;
828 self.w
829 }
830}
831#[doc = "Values that can be written to the field `FCOMB`"]
832pub enum FCOMBW {
833 #[doc = "FIFO combine mode disabled."]
834 _00,
835 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."]
836 _01,
837 #[doc = "FIFO combine mode enabled on FIFO writes (by software)."]
838 _10,
839 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."]
840 _11,
841}
842impl FCOMBW {
843 #[allow(missing_docs)]
844 #[doc(hidden)]
845 #[inline]
846 pub fn _bits(&self) -> u8 {
847 match *self {
848 FCOMBW::_00 => 0,
849 FCOMBW::_01 => 1,
850 FCOMBW::_10 => 2,
851 FCOMBW::_11 => 3,
852 }
853 }
854}
855#[doc = r" Proxy"]
856pub struct _FCOMBW<'a> {
857 w: &'a mut W,
858}
859impl<'a> _FCOMBW<'a> {
860 #[doc = r" Writes `variant` to the field"]
861 #[inline]
862 pub fn variant(self, variant: FCOMBW) -> &'a mut W {
863 {
864 self.bits(variant._bits())
865 }
866 }
867 #[doc = "FIFO combine mode disabled."]
868 #[inline]
869 pub fn _00(self) -> &'a mut W {
870 self.variant(FCOMBW::_00)
871 }
872 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."]
873 #[inline]
874 pub fn _01(self) -> &'a mut W {
875 self.variant(FCOMBW::_01)
876 }
877 #[doc = "FIFO combine mode enabled on FIFO writes (by software)."]
878 #[inline]
879 pub fn _10(self) -> &'a mut W {
880 self.variant(FCOMBW::_10)
881 }
882 #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."]
883 #[inline]
884 pub fn _11(self) -> &'a mut W {
885 self.variant(FCOMBW::_11)
886 }
887 #[doc = r" Writes raw bits to the field"]
888 #[inline]
889 pub fn bits(self, value: u8) -> &'a mut W {
890 const MASK: u8 = 3;
891 const OFFSET: u8 = 26;
892 self.w.bits &= !((MASK as u32) << OFFSET);
893 self.w.bits |= ((value & MASK) as u32) << OFFSET;
894 self.w
895 }
896}
897#[doc = "Values that can be written to the field `FCONT`"]
898pub enum FCONTW {
899 #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."]
900 _0,
901 #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."]
902 _1,
903}
904impl FCONTW {
905 #[allow(missing_docs)]
906 #[doc(hidden)]
907 #[inline]
908 pub fn _bits(&self) -> bool {
909 match *self {
910 FCONTW::_0 => false,
911 FCONTW::_1 => true,
912 }
913 }
914}
915#[doc = r" Proxy"]
916pub struct _FCONTW<'a> {
917 w: &'a mut W,
918}
919impl<'a> _FCONTW<'a> {
920 #[doc = r" Writes `variant` to the field"]
921 #[inline]
922 pub fn variant(self, variant: FCONTW) -> &'a mut W {
923 {
924 self.bit(variant._bits())
925 }
926 }
927 #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."]
928 #[inline]
929 pub fn _0(self) -> &'a mut W {
930 self.variant(FCONTW::_0)
931 }
932 #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."]
933 #[inline]
934 pub fn _1(self) -> &'a mut W {
935 self.variant(FCONTW::_1)
936 }
937 #[doc = r" Sets the field bit"]
938 pub fn set_bit(self) -> &'a mut W {
939 self.bit(true)
940 }
941 #[doc = r" Clears the field bit"]
942 pub fn clear_bit(self) -> &'a mut W {
943 self.bit(false)
944 }
945 #[doc = r" Writes raw bits to the field"]
946 #[inline]
947 pub fn bit(self, value: bool) -> &'a mut W {
948 const MASK: bool = true;
949 const OFFSET: u8 = 28;
950 self.w.bits &= !((MASK as u32) << OFFSET);
951 self.w.bits |= ((value & MASK) as u32) << OFFSET;
952 self.w
953 }
954}
955impl R {
956 #[doc = r" Value of the register as raw bits"]
957 #[inline]
958 pub fn bits(&self) -> u32 {
959 self.bits
960 }
961 #[doc = "Bit 0 - Frame Sync Direction"]
962 #[inline]
963 pub fn fsd(&self) -> FSDR {
964 FSDR::_from({
965 const MASK: bool = true;
966 const OFFSET: u8 = 0;
967 ((self.bits >> OFFSET) & MASK as u32) != 0
968 })
969 }
970 #[doc = "Bit 1 - Frame Sync Polarity"]
971 #[inline]
972 pub fn fsp(&self) -> FSPR {
973 FSPR::_from({
974 const MASK: bool = true;
975 const OFFSET: u8 = 1;
976 ((self.bits >> OFFSET) & MASK as u32) != 0
977 })
978 }
979 #[doc = "Bit 2 - On Demand Mode"]
980 #[inline]
981 pub fn ondem(&self) -> ONDEMR {
982 ONDEMR::_from({
983 const MASK: bool = true;
984 const OFFSET: u8 = 2;
985 ((self.bits >> OFFSET) & MASK as u32) != 0
986 })
987 }
988 #[doc = "Bit 3 - Frame Sync Early"]
989 #[inline]
990 pub fn fse(&self) -> FSER {
991 FSER::_from({
992 const MASK: bool = true;
993 const OFFSET: u8 = 3;
994 ((self.bits >> OFFSET) & MASK as u32) != 0
995 })
996 }
997 #[doc = "Bit 4 - MSB First"]
998 #[inline]
999 pub fn mf(&self) -> MFR {
1000 MFR::_from({
1001 const MASK: bool = true;
1002 const OFFSET: u8 = 4;
1003 ((self.bits >> OFFSET) & MASK as u32) != 0
1004 })
1005 }
1006 #[doc = "Bits 8:12 - Sync Width"]
1007 #[inline]
1008 pub fn sywd(&self) -> SYWDR {
1009 let bits = {
1010 const MASK: u8 = 31;
1011 const OFFSET: u8 = 8;
1012 ((self.bits >> OFFSET) & MASK as u32) as u8
1013 };
1014 SYWDR { bits }
1015 }
1016 #[doc = "Bits 16:20 - Frame size"]
1017 #[inline]
1018 pub fn frsz(&self) -> FRSZR {
1019 let bits = {
1020 const MASK: u8 = 31;
1021 const OFFSET: u8 = 16;
1022 ((self.bits >> OFFSET) & MASK as u32) as u8
1023 };
1024 FRSZR { bits }
1025 }
1026 #[doc = "Bits 24:25 - FIFO Packing Mode"]
1027 #[inline]
1028 pub fn fpack(&self) -> FPACKR {
1029 FPACKR::_from({
1030 const MASK: u8 = 3;
1031 const OFFSET: u8 = 24;
1032 ((self.bits >> OFFSET) & MASK as u32) as u8
1033 })
1034 }
1035 #[doc = "Bits 26:27 - FIFO Combine Mode"]
1036 #[inline]
1037 pub fn fcomb(&self) -> FCOMBR {
1038 FCOMBR::_from({
1039 const MASK: u8 = 3;
1040 const OFFSET: u8 = 26;
1041 ((self.bits >> OFFSET) & MASK as u32) as u8
1042 })
1043 }
1044 #[doc = "Bit 28 - FIFO Continue on Error"]
1045 #[inline]
1046 pub fn fcont(&self) -> FCONTR {
1047 FCONTR::_from({
1048 const MASK: bool = true;
1049 const OFFSET: u8 = 28;
1050 ((self.bits >> OFFSET) & MASK as u32) != 0
1051 })
1052 }
1053}
1054impl W {
1055 #[doc = r" Reset value of the register"]
1056 #[inline]
1057 pub fn reset_value() -> W {
1058 W { bits: 0 }
1059 }
1060 #[doc = r" Writes raw bits to the register"]
1061 #[inline]
1062 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1063 self.bits = bits;
1064 self
1065 }
1066 #[doc = "Bit 0 - Frame Sync Direction"]
1067 #[inline]
1068 pub fn fsd(&mut self) -> _FSDW {
1069 _FSDW { w: self }
1070 }
1071 #[doc = "Bit 1 - Frame Sync Polarity"]
1072 #[inline]
1073 pub fn fsp(&mut self) -> _FSPW {
1074 _FSPW { w: self }
1075 }
1076 #[doc = "Bit 2 - On Demand Mode"]
1077 #[inline]
1078 pub fn ondem(&mut self) -> _ONDEMW {
1079 _ONDEMW { w: self }
1080 }
1081 #[doc = "Bit 3 - Frame Sync Early"]
1082 #[inline]
1083 pub fn fse(&mut self) -> _FSEW {
1084 _FSEW { w: self }
1085 }
1086 #[doc = "Bit 4 - MSB First"]
1087 #[inline]
1088 pub fn mf(&mut self) -> _MFW {
1089 _MFW { w: self }
1090 }
1091 #[doc = "Bits 8:12 - Sync Width"]
1092 #[inline]
1093 pub fn sywd(&mut self) -> _SYWDW {
1094 _SYWDW { w: self }
1095 }
1096 #[doc = "Bits 16:20 - Frame size"]
1097 #[inline]
1098 pub fn frsz(&mut self) -> _FRSZW {
1099 _FRSZW { w: self }
1100 }
1101 #[doc = "Bits 24:25 - FIFO Packing Mode"]
1102 #[inline]
1103 pub fn fpack(&mut self) -> _FPACKW {
1104 _FPACKW { w: self }
1105 }
1106 #[doc = "Bits 26:27 - FIFO Combine Mode"]
1107 #[inline]
1108 pub fn fcomb(&mut self) -> _FCOMBW {
1109 _FCOMBW { w: self }
1110 }
1111 #[doc = "Bit 28 - FIFO Continue on Error"]
1112 #[inline]
1113 pub fn fcont(&mut self) -> _FCONTW {
1114 _FCONTW { w: self }
1115 }
1116}