1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::PCR29 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `PS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum PSR {
48 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
49 _0,
50 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
51 _1,
52}
53impl PSR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 PSR::_0 => false,
69 PSR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> PSR {
76 match value {
77 false => PSR::_0,
78 true => PSR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == PSR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == PSR::_1
90 }
91}
92#[doc = "Possible values of the field `PE`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum PER {
95 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
96 _0,
97 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
98 _1,
99}
100impl PER {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 PER::_0 => false,
116 PER::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> PER {
123 match value {
124 false => PER::_0,
125 true => PER::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == PER::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == PER::_1
137 }
138}
139#[doc = "Possible values of the field `SRE`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum SRER {
142 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
143 _0,
144 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
145 _1,
146}
147impl SRER {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 SRER::_0 => false,
163 SRER::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> SRER {
170 match value {
171 false => SRER::_0,
172 true => SRER::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == SRER::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == SRER::_1
184 }
185}
186#[doc = "Possible values of the field `PFE`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum PFER {
189 #[doc = "Passive input filter is disabled on the corresponding pin."]
190 _0,
191 #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."]
192 _1,
193}
194impl PFER {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 PFER::_0 => false,
210 PFER::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> PFER {
217 match value {
218 false => PFER::_0,
219 true => PFER::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == PFER::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == PFER::_1
231 }
232}
233#[doc = "Possible values of the field `ODE`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum ODER {
236 #[doc = "Open drain output is disabled on the corresponding pin."]
237 _0,
238 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
239 _1,
240}
241impl ODER {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 ODER::_0 => false,
257 ODER::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> ODER {
264 match value {
265 false => ODER::_0,
266 true => ODER::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == ODER::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == ODER::_1
278 }
279}
280#[doc = "Possible values of the field `DSE`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum DSER {
283 #[doc = "Low drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
284 _0,
285 #[doc = "High drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
286 _1,
287}
288impl DSER {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 DSER::_0 => false,
304 DSER::_1 => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> DSER {
311 match value {
312 false => DSER::_0,
313 true => DSER::_1,
314 }
315 }
316 #[doc = "Checks if the value of the field is `_0`"]
317 #[inline]
318 pub fn is_0(&self) -> bool {
319 *self == DSER::_0
320 }
321 #[doc = "Checks if the value of the field is `_1`"]
322 #[inline]
323 pub fn is_1(&self) -> bool {
324 *self == DSER::_1
325 }
326}
327#[doc = "Possible values of the field `MUX`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum MUXR {
330 #[doc = "Pin disabled (analog)."]
331 _000,
332 #[doc = "Alternative 1 (GPIO)."]
333 _001,
334 #[doc = "Alternative 2 (chip-specific)."]
335 _010,
336 #[doc = "Alternative 3 (chip-specific)."]
337 _011,
338 #[doc = "Alternative 4 (chip-specific)."]
339 _100,
340 #[doc = "Alternative 5 (chip-specific)."]
341 _101,
342 #[doc = "Alternative 6 (chip-specific)."]
343 _110,
344 #[doc = "Alternative 7 (chip-specific)."]
345 _111,
346}
347impl MUXR {
348 #[doc = r" Value of the field as raw bits"]
349 #[inline]
350 pub fn bits(&self) -> u8 {
351 match *self {
352 MUXR::_000 => 0,
353 MUXR::_001 => 1,
354 MUXR::_010 => 2,
355 MUXR::_011 => 3,
356 MUXR::_100 => 4,
357 MUXR::_101 => 5,
358 MUXR::_110 => 6,
359 MUXR::_111 => 7,
360 }
361 }
362 #[allow(missing_docs)]
363 #[doc(hidden)]
364 #[inline]
365 pub fn _from(value: u8) -> MUXR {
366 match value {
367 0 => MUXR::_000,
368 1 => MUXR::_001,
369 2 => MUXR::_010,
370 3 => MUXR::_011,
371 4 => MUXR::_100,
372 5 => MUXR::_101,
373 6 => MUXR::_110,
374 7 => MUXR::_111,
375 _ => unreachable!(),
376 }
377 }
378 #[doc = "Checks if the value of the field is `_000`"]
379 #[inline]
380 pub fn is_000(&self) -> bool {
381 *self == MUXR::_000
382 }
383 #[doc = "Checks if the value of the field is `_001`"]
384 #[inline]
385 pub fn is_001(&self) -> bool {
386 *self == MUXR::_001
387 }
388 #[doc = "Checks if the value of the field is `_010`"]
389 #[inline]
390 pub fn is_010(&self) -> bool {
391 *self == MUXR::_010
392 }
393 #[doc = "Checks if the value of the field is `_011`"]
394 #[inline]
395 pub fn is_011(&self) -> bool {
396 *self == MUXR::_011
397 }
398 #[doc = "Checks if the value of the field is `_100`"]
399 #[inline]
400 pub fn is_100(&self) -> bool {
401 *self == MUXR::_100
402 }
403 #[doc = "Checks if the value of the field is `_101`"]
404 #[inline]
405 pub fn is_101(&self) -> bool {
406 *self == MUXR::_101
407 }
408 #[doc = "Checks if the value of the field is `_110`"]
409 #[inline]
410 pub fn is_110(&self) -> bool {
411 *self == MUXR::_110
412 }
413 #[doc = "Checks if the value of the field is `_111`"]
414 #[inline]
415 pub fn is_111(&self) -> bool {
416 *self == MUXR::_111
417 }
418}
419#[doc = "Possible values of the field `LK`"]
420#[derive(Clone, Copy, Debug, PartialEq)]
421pub enum LKR {
422 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
423 _0,
424 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
425 _1,
426}
427impl LKR {
428 #[doc = r" Returns `true` if the bit is clear (0)"]
429 #[inline]
430 pub fn bit_is_clear(&self) -> bool {
431 !self.bit()
432 }
433 #[doc = r" Returns `true` if the bit is set (1)"]
434 #[inline]
435 pub fn bit_is_set(&self) -> bool {
436 self.bit()
437 }
438 #[doc = r" Value of the field as raw bits"]
439 #[inline]
440 pub fn bit(&self) -> bool {
441 match *self {
442 LKR::_0 => false,
443 LKR::_1 => true,
444 }
445 }
446 #[allow(missing_docs)]
447 #[doc(hidden)]
448 #[inline]
449 pub fn _from(value: bool) -> LKR {
450 match value {
451 false => LKR::_0,
452 true => LKR::_1,
453 }
454 }
455 #[doc = "Checks if the value of the field is `_0`"]
456 #[inline]
457 pub fn is_0(&self) -> bool {
458 *self == LKR::_0
459 }
460 #[doc = "Checks if the value of the field is `_1`"]
461 #[inline]
462 pub fn is_1(&self) -> bool {
463 *self == LKR::_1
464 }
465}
466#[doc = "Possible values of the field `IRQC`"]
467#[derive(Clone, Copy, Debug, PartialEq)]
468pub enum IRQCR {
469 #[doc = "Interrupt/DMA request disabled."]
470 _0000,
471 #[doc = "DMA request on rising edge."]
472 _0001,
473 #[doc = "DMA request on falling edge."]
474 _0010,
475 #[doc = "DMA request on either edge."]
476 _0011,
477 #[doc = "Interrupt when logic 0."]
478 _1000,
479 #[doc = "Interrupt on rising-edge."]
480 _1001,
481 #[doc = "Interrupt on falling-edge."]
482 _1010,
483 #[doc = "Interrupt on either edge."]
484 _1011,
485 #[doc = "Interrupt when logic 1."]
486 _1100,
487 #[doc = r" Reserved"]
488 _Reserved(u8),
489}
490impl IRQCR {
491 #[doc = r" Value of the field as raw bits"]
492 #[inline]
493 pub fn bits(&self) -> u8 {
494 match *self {
495 IRQCR::_0000 => 0,
496 IRQCR::_0001 => 1,
497 IRQCR::_0010 => 2,
498 IRQCR::_0011 => 3,
499 IRQCR::_1000 => 8,
500 IRQCR::_1001 => 9,
501 IRQCR::_1010 => 10,
502 IRQCR::_1011 => 11,
503 IRQCR::_1100 => 12,
504 IRQCR::_Reserved(bits) => bits,
505 }
506 }
507 #[allow(missing_docs)]
508 #[doc(hidden)]
509 #[inline]
510 pub fn _from(value: u8) -> IRQCR {
511 match value {
512 0 => IRQCR::_0000,
513 1 => IRQCR::_0001,
514 2 => IRQCR::_0010,
515 3 => IRQCR::_0011,
516 8 => IRQCR::_1000,
517 9 => IRQCR::_1001,
518 10 => IRQCR::_1010,
519 11 => IRQCR::_1011,
520 12 => IRQCR::_1100,
521 i => IRQCR::_Reserved(i),
522 }
523 }
524 #[doc = "Checks if the value of the field is `_0000`"]
525 #[inline]
526 pub fn is_0000(&self) -> bool {
527 *self == IRQCR::_0000
528 }
529 #[doc = "Checks if the value of the field is `_0001`"]
530 #[inline]
531 pub fn is_0001(&self) -> bool {
532 *self == IRQCR::_0001
533 }
534 #[doc = "Checks if the value of the field is `_0010`"]
535 #[inline]
536 pub fn is_0010(&self) -> bool {
537 *self == IRQCR::_0010
538 }
539 #[doc = "Checks if the value of the field is `_0011`"]
540 #[inline]
541 pub fn is_0011(&self) -> bool {
542 *self == IRQCR::_0011
543 }
544 #[doc = "Checks if the value of the field is `_1000`"]
545 #[inline]
546 pub fn is_1000(&self) -> bool {
547 *self == IRQCR::_1000
548 }
549 #[doc = "Checks if the value of the field is `_1001`"]
550 #[inline]
551 pub fn is_1001(&self) -> bool {
552 *self == IRQCR::_1001
553 }
554 #[doc = "Checks if the value of the field is `_1010`"]
555 #[inline]
556 pub fn is_1010(&self) -> bool {
557 *self == IRQCR::_1010
558 }
559 #[doc = "Checks if the value of the field is `_1011`"]
560 #[inline]
561 pub fn is_1011(&self) -> bool {
562 *self == IRQCR::_1011
563 }
564 #[doc = "Checks if the value of the field is `_1100`"]
565 #[inline]
566 pub fn is_1100(&self) -> bool {
567 *self == IRQCR::_1100
568 }
569}
570#[doc = "Possible values of the field `ISF`"]
571#[derive(Clone, Copy, Debug, PartialEq)]
572pub enum ISFR {
573 #[doc = "Configured interrupt is not detected."]
574 _0,
575 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
576 _1,
577}
578impl ISFR {
579 #[doc = r" Returns `true` if the bit is clear (0)"]
580 #[inline]
581 pub fn bit_is_clear(&self) -> bool {
582 !self.bit()
583 }
584 #[doc = r" Returns `true` if the bit is set (1)"]
585 #[inline]
586 pub fn bit_is_set(&self) -> bool {
587 self.bit()
588 }
589 #[doc = r" Value of the field as raw bits"]
590 #[inline]
591 pub fn bit(&self) -> bool {
592 match *self {
593 ISFR::_0 => false,
594 ISFR::_1 => true,
595 }
596 }
597 #[allow(missing_docs)]
598 #[doc(hidden)]
599 #[inline]
600 pub fn _from(value: bool) -> ISFR {
601 match value {
602 false => ISFR::_0,
603 true => ISFR::_1,
604 }
605 }
606 #[doc = "Checks if the value of the field is `_0`"]
607 #[inline]
608 pub fn is_0(&self) -> bool {
609 *self == ISFR::_0
610 }
611 #[doc = "Checks if the value of the field is `_1`"]
612 #[inline]
613 pub fn is_1(&self) -> bool {
614 *self == ISFR::_1
615 }
616}
617#[doc = "Values that can be written to the field `PS`"]
618pub enum PSW {
619 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
620 _0,
621 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
622 _1,
623}
624impl PSW {
625 #[allow(missing_docs)]
626 #[doc(hidden)]
627 #[inline]
628 pub fn _bits(&self) -> bool {
629 match *self {
630 PSW::_0 => false,
631 PSW::_1 => true,
632 }
633 }
634}
635#[doc = r" Proxy"]
636pub struct _PSW<'a> {
637 w: &'a mut W,
638}
639impl<'a> _PSW<'a> {
640 #[doc = r" Writes `variant` to the field"]
641 #[inline]
642 pub fn variant(self, variant: PSW) -> &'a mut W {
643 {
644 self.bit(variant._bits())
645 }
646 }
647 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
648 #[inline]
649 pub fn _0(self) -> &'a mut W {
650 self.variant(PSW::_0)
651 }
652 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
653 #[inline]
654 pub fn _1(self) -> &'a mut W {
655 self.variant(PSW::_1)
656 }
657 #[doc = r" Sets the field bit"]
658 pub fn set_bit(self) -> &'a mut W {
659 self.bit(true)
660 }
661 #[doc = r" Clears the field bit"]
662 pub fn clear_bit(self) -> &'a mut W {
663 self.bit(false)
664 }
665 #[doc = r" Writes raw bits to the field"]
666 #[inline]
667 pub fn bit(self, value: bool) -> &'a mut W {
668 const MASK: bool = true;
669 const OFFSET: u8 = 0;
670 self.w.bits &= !((MASK as u32) << OFFSET);
671 self.w.bits |= ((value & MASK) as u32) << OFFSET;
672 self.w
673 }
674}
675#[doc = "Values that can be written to the field `PE`"]
676pub enum PEW {
677 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
678 _0,
679 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
680 _1,
681}
682impl PEW {
683 #[allow(missing_docs)]
684 #[doc(hidden)]
685 #[inline]
686 pub fn _bits(&self) -> bool {
687 match *self {
688 PEW::_0 => false,
689 PEW::_1 => true,
690 }
691 }
692}
693#[doc = r" Proxy"]
694pub struct _PEW<'a> {
695 w: &'a mut W,
696}
697impl<'a> _PEW<'a> {
698 #[doc = r" Writes `variant` to the field"]
699 #[inline]
700 pub fn variant(self, variant: PEW) -> &'a mut W {
701 {
702 self.bit(variant._bits())
703 }
704 }
705 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
706 #[inline]
707 pub fn _0(self) -> &'a mut W {
708 self.variant(PEW::_0)
709 }
710 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
711 #[inline]
712 pub fn _1(self) -> &'a mut W {
713 self.variant(PEW::_1)
714 }
715 #[doc = r" Sets the field bit"]
716 pub fn set_bit(self) -> &'a mut W {
717 self.bit(true)
718 }
719 #[doc = r" Clears the field bit"]
720 pub fn clear_bit(self) -> &'a mut W {
721 self.bit(false)
722 }
723 #[doc = r" Writes raw bits to the field"]
724 #[inline]
725 pub fn bit(self, value: bool) -> &'a mut W {
726 const MASK: bool = true;
727 const OFFSET: u8 = 1;
728 self.w.bits &= !((MASK as u32) << OFFSET);
729 self.w.bits |= ((value & MASK) as u32) << OFFSET;
730 self.w
731 }
732}
733#[doc = "Values that can be written to the field `SRE`"]
734pub enum SREW {
735 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
736 _0,
737 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
738 _1,
739}
740impl SREW {
741 #[allow(missing_docs)]
742 #[doc(hidden)]
743 #[inline]
744 pub fn _bits(&self) -> bool {
745 match *self {
746 SREW::_0 => false,
747 SREW::_1 => true,
748 }
749 }
750}
751#[doc = r" Proxy"]
752pub struct _SREW<'a> {
753 w: &'a mut W,
754}
755impl<'a> _SREW<'a> {
756 #[doc = r" Writes `variant` to the field"]
757 #[inline]
758 pub fn variant(self, variant: SREW) -> &'a mut W {
759 {
760 self.bit(variant._bits())
761 }
762 }
763 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
764 #[inline]
765 pub fn _0(self) -> &'a mut W {
766 self.variant(SREW::_0)
767 }
768 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
769 #[inline]
770 pub fn _1(self) -> &'a mut W {
771 self.variant(SREW::_1)
772 }
773 #[doc = r" Sets the field bit"]
774 pub fn set_bit(self) -> &'a mut W {
775 self.bit(true)
776 }
777 #[doc = r" Clears the field bit"]
778 pub fn clear_bit(self) -> &'a mut W {
779 self.bit(false)
780 }
781 #[doc = r" Writes raw bits to the field"]
782 #[inline]
783 pub fn bit(self, value: bool) -> &'a mut W {
784 const MASK: bool = true;
785 const OFFSET: u8 = 2;
786 self.w.bits &= !((MASK as u32) << OFFSET);
787 self.w.bits |= ((value & MASK) as u32) << OFFSET;
788 self.w
789 }
790}
791#[doc = "Values that can be written to the field `PFE`"]
792pub enum PFEW {
793 #[doc = "Passive input filter is disabled on the corresponding pin."]
794 _0,
795 #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."]
796 _1,
797}
798impl PFEW {
799 #[allow(missing_docs)]
800 #[doc(hidden)]
801 #[inline]
802 pub fn _bits(&self) -> bool {
803 match *self {
804 PFEW::_0 => false,
805 PFEW::_1 => true,
806 }
807 }
808}
809#[doc = r" Proxy"]
810pub struct _PFEW<'a> {
811 w: &'a mut W,
812}
813impl<'a> _PFEW<'a> {
814 #[doc = r" Writes `variant` to the field"]
815 #[inline]
816 pub fn variant(self, variant: PFEW) -> &'a mut W {
817 {
818 self.bit(variant._bits())
819 }
820 }
821 #[doc = "Passive input filter is disabled on the corresponding pin."]
822 #[inline]
823 pub fn _0(self) -> &'a mut W {
824 self.variant(PFEW::_0)
825 }
826 #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."]
827 #[inline]
828 pub fn _1(self) -> &'a mut W {
829 self.variant(PFEW::_1)
830 }
831 #[doc = r" Sets the field bit"]
832 pub fn set_bit(self) -> &'a mut W {
833 self.bit(true)
834 }
835 #[doc = r" Clears the field bit"]
836 pub fn clear_bit(self) -> &'a mut W {
837 self.bit(false)
838 }
839 #[doc = r" Writes raw bits to the field"]
840 #[inline]
841 pub fn bit(self, value: bool) -> &'a mut W {
842 const MASK: bool = true;
843 const OFFSET: u8 = 4;
844 self.w.bits &= !((MASK as u32) << OFFSET);
845 self.w.bits |= ((value & MASK) as u32) << OFFSET;
846 self.w
847 }
848}
849#[doc = "Values that can be written to the field `ODE`"]
850pub enum ODEW {
851 #[doc = "Open drain output is disabled on the corresponding pin."]
852 _0,
853 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
854 _1,
855}
856impl ODEW {
857 #[allow(missing_docs)]
858 #[doc(hidden)]
859 #[inline]
860 pub fn _bits(&self) -> bool {
861 match *self {
862 ODEW::_0 => false,
863 ODEW::_1 => true,
864 }
865 }
866}
867#[doc = r" Proxy"]
868pub struct _ODEW<'a> {
869 w: &'a mut W,
870}
871impl<'a> _ODEW<'a> {
872 #[doc = r" Writes `variant` to the field"]
873 #[inline]
874 pub fn variant(self, variant: ODEW) -> &'a mut W {
875 {
876 self.bit(variant._bits())
877 }
878 }
879 #[doc = "Open drain output is disabled on the corresponding pin."]
880 #[inline]
881 pub fn _0(self) -> &'a mut W {
882 self.variant(ODEW::_0)
883 }
884 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
885 #[inline]
886 pub fn _1(self) -> &'a mut W {
887 self.variant(ODEW::_1)
888 }
889 #[doc = r" Sets the field bit"]
890 pub fn set_bit(self) -> &'a mut W {
891 self.bit(true)
892 }
893 #[doc = r" Clears the field bit"]
894 pub fn clear_bit(self) -> &'a mut W {
895 self.bit(false)
896 }
897 #[doc = r" Writes raw bits to the field"]
898 #[inline]
899 pub fn bit(self, value: bool) -> &'a mut W {
900 const MASK: bool = true;
901 const OFFSET: u8 = 5;
902 self.w.bits &= !((MASK as u32) << OFFSET);
903 self.w.bits |= ((value & MASK) as u32) << OFFSET;
904 self.w
905 }
906}
907#[doc = "Values that can be written to the field `DSE`"]
908pub enum DSEW {
909 #[doc = "Low drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
910 _0,
911 #[doc = "High drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
912 _1,
913}
914impl DSEW {
915 #[allow(missing_docs)]
916 #[doc(hidden)]
917 #[inline]
918 pub fn _bits(&self) -> bool {
919 match *self {
920 DSEW::_0 => false,
921 DSEW::_1 => true,
922 }
923 }
924}
925#[doc = r" Proxy"]
926pub struct _DSEW<'a> {
927 w: &'a mut W,
928}
929impl<'a> _DSEW<'a> {
930 #[doc = r" Writes `variant` to the field"]
931 #[inline]
932 pub fn variant(self, variant: DSEW) -> &'a mut W {
933 {
934 self.bit(variant._bits())
935 }
936 }
937 #[doc = "Low drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
938 #[inline]
939 pub fn _0(self) -> &'a mut W {
940 self.variant(DSEW::_0)
941 }
942 #[doc = "High drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
943 #[inline]
944 pub fn _1(self) -> &'a mut W {
945 self.variant(DSEW::_1)
946 }
947 #[doc = r" Sets the field bit"]
948 pub fn set_bit(self) -> &'a mut W {
949 self.bit(true)
950 }
951 #[doc = r" Clears the field bit"]
952 pub fn clear_bit(self) -> &'a mut W {
953 self.bit(false)
954 }
955 #[doc = r" Writes raw bits to the field"]
956 #[inline]
957 pub fn bit(self, value: bool) -> &'a mut W {
958 const MASK: bool = true;
959 const OFFSET: u8 = 6;
960 self.w.bits &= !((MASK as u32) << OFFSET);
961 self.w.bits |= ((value & MASK) as u32) << OFFSET;
962 self.w
963 }
964}
965#[doc = "Values that can be written to the field `MUX`"]
966pub enum MUXW {
967 #[doc = "Pin disabled (analog)."]
968 _000,
969 #[doc = "Alternative 1 (GPIO)."]
970 _001,
971 #[doc = "Alternative 2 (chip-specific)."]
972 _010,
973 #[doc = "Alternative 3 (chip-specific)."]
974 _011,
975 #[doc = "Alternative 4 (chip-specific)."]
976 _100,
977 #[doc = "Alternative 5 (chip-specific)."]
978 _101,
979 #[doc = "Alternative 6 (chip-specific)."]
980 _110,
981 #[doc = "Alternative 7 (chip-specific)."]
982 _111,
983}
984impl MUXW {
985 #[allow(missing_docs)]
986 #[doc(hidden)]
987 #[inline]
988 pub fn _bits(&self) -> u8 {
989 match *self {
990 MUXW::_000 => 0,
991 MUXW::_001 => 1,
992 MUXW::_010 => 2,
993 MUXW::_011 => 3,
994 MUXW::_100 => 4,
995 MUXW::_101 => 5,
996 MUXW::_110 => 6,
997 MUXW::_111 => 7,
998 }
999 }
1000}
1001#[doc = r" Proxy"]
1002pub struct _MUXW<'a> {
1003 w: &'a mut W,
1004}
1005impl<'a> _MUXW<'a> {
1006 #[doc = r" Writes `variant` to the field"]
1007 #[inline]
1008 pub fn variant(self, variant: MUXW) -> &'a mut W {
1009 {
1010 self.bits(variant._bits())
1011 }
1012 }
1013 #[doc = "Pin disabled (analog)."]
1014 #[inline]
1015 pub fn _000(self) -> &'a mut W {
1016 self.variant(MUXW::_000)
1017 }
1018 #[doc = "Alternative 1 (GPIO)."]
1019 #[inline]
1020 pub fn _001(self) -> &'a mut W {
1021 self.variant(MUXW::_001)
1022 }
1023 #[doc = "Alternative 2 (chip-specific)."]
1024 #[inline]
1025 pub fn _010(self) -> &'a mut W {
1026 self.variant(MUXW::_010)
1027 }
1028 #[doc = "Alternative 3 (chip-specific)."]
1029 #[inline]
1030 pub fn _011(self) -> &'a mut W {
1031 self.variant(MUXW::_011)
1032 }
1033 #[doc = "Alternative 4 (chip-specific)."]
1034 #[inline]
1035 pub fn _100(self) -> &'a mut W {
1036 self.variant(MUXW::_100)
1037 }
1038 #[doc = "Alternative 5 (chip-specific)."]
1039 #[inline]
1040 pub fn _101(self) -> &'a mut W {
1041 self.variant(MUXW::_101)
1042 }
1043 #[doc = "Alternative 6 (chip-specific)."]
1044 #[inline]
1045 pub fn _110(self) -> &'a mut W {
1046 self.variant(MUXW::_110)
1047 }
1048 #[doc = "Alternative 7 (chip-specific)."]
1049 #[inline]
1050 pub fn _111(self) -> &'a mut W {
1051 self.variant(MUXW::_111)
1052 }
1053 #[doc = r" Writes raw bits to the field"]
1054 #[inline]
1055 pub fn bits(self, value: u8) -> &'a mut W {
1056 const MASK: u8 = 7;
1057 const OFFSET: u8 = 8;
1058 self.w.bits &= !((MASK as u32) << OFFSET);
1059 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1060 self.w
1061 }
1062}
1063#[doc = "Values that can be written to the field `LK`"]
1064pub enum LKW {
1065 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
1066 _0,
1067 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
1068 _1,
1069}
1070impl LKW {
1071 #[allow(missing_docs)]
1072 #[doc(hidden)]
1073 #[inline]
1074 pub fn _bits(&self) -> bool {
1075 match *self {
1076 LKW::_0 => false,
1077 LKW::_1 => true,
1078 }
1079 }
1080}
1081#[doc = r" Proxy"]
1082pub struct _LKW<'a> {
1083 w: &'a mut W,
1084}
1085impl<'a> _LKW<'a> {
1086 #[doc = r" Writes `variant` to the field"]
1087 #[inline]
1088 pub fn variant(self, variant: LKW) -> &'a mut W {
1089 {
1090 self.bit(variant._bits())
1091 }
1092 }
1093 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
1094 #[inline]
1095 pub fn _0(self) -> &'a mut W {
1096 self.variant(LKW::_0)
1097 }
1098 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
1099 #[inline]
1100 pub fn _1(self) -> &'a mut W {
1101 self.variant(LKW::_1)
1102 }
1103 #[doc = r" Sets the field bit"]
1104 pub fn set_bit(self) -> &'a mut W {
1105 self.bit(true)
1106 }
1107 #[doc = r" Clears the field bit"]
1108 pub fn clear_bit(self) -> &'a mut W {
1109 self.bit(false)
1110 }
1111 #[doc = r" Writes raw bits to the field"]
1112 #[inline]
1113 pub fn bit(self, value: bool) -> &'a mut W {
1114 const MASK: bool = true;
1115 const OFFSET: u8 = 15;
1116 self.w.bits &= !((MASK as u32) << OFFSET);
1117 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1118 self.w
1119 }
1120}
1121#[doc = "Values that can be written to the field `IRQC`"]
1122pub enum IRQCW {
1123 #[doc = "Interrupt/DMA request disabled."]
1124 _0000,
1125 #[doc = "DMA request on rising edge."]
1126 _0001,
1127 #[doc = "DMA request on falling edge."]
1128 _0010,
1129 #[doc = "DMA request on either edge."]
1130 _0011,
1131 #[doc = "Interrupt when logic 0."]
1132 _1000,
1133 #[doc = "Interrupt on rising-edge."]
1134 _1001,
1135 #[doc = "Interrupt on falling-edge."]
1136 _1010,
1137 #[doc = "Interrupt on either edge."]
1138 _1011,
1139 #[doc = "Interrupt when logic 1."]
1140 _1100,
1141}
1142impl IRQCW {
1143 #[allow(missing_docs)]
1144 #[doc(hidden)]
1145 #[inline]
1146 pub fn _bits(&self) -> u8 {
1147 match *self {
1148 IRQCW::_0000 => 0,
1149 IRQCW::_0001 => 1,
1150 IRQCW::_0010 => 2,
1151 IRQCW::_0011 => 3,
1152 IRQCW::_1000 => 8,
1153 IRQCW::_1001 => 9,
1154 IRQCW::_1010 => 10,
1155 IRQCW::_1011 => 11,
1156 IRQCW::_1100 => 12,
1157 }
1158 }
1159}
1160#[doc = r" Proxy"]
1161pub struct _IRQCW<'a> {
1162 w: &'a mut W,
1163}
1164impl<'a> _IRQCW<'a> {
1165 #[doc = r" Writes `variant` to the field"]
1166 #[inline]
1167 pub fn variant(self, variant: IRQCW) -> &'a mut W {
1168 unsafe { self.bits(variant._bits()) }
1169 }
1170 #[doc = "Interrupt/DMA request disabled."]
1171 #[inline]
1172 pub fn _0000(self) -> &'a mut W {
1173 self.variant(IRQCW::_0000)
1174 }
1175 #[doc = "DMA request on rising edge."]
1176 #[inline]
1177 pub fn _0001(self) -> &'a mut W {
1178 self.variant(IRQCW::_0001)
1179 }
1180 #[doc = "DMA request on falling edge."]
1181 #[inline]
1182 pub fn _0010(self) -> &'a mut W {
1183 self.variant(IRQCW::_0010)
1184 }
1185 #[doc = "DMA request on either edge."]
1186 #[inline]
1187 pub fn _0011(self) -> &'a mut W {
1188 self.variant(IRQCW::_0011)
1189 }
1190 #[doc = "Interrupt when logic 0."]
1191 #[inline]
1192 pub fn _1000(self) -> &'a mut W {
1193 self.variant(IRQCW::_1000)
1194 }
1195 #[doc = "Interrupt on rising-edge."]
1196 #[inline]
1197 pub fn _1001(self) -> &'a mut W {
1198 self.variant(IRQCW::_1001)
1199 }
1200 #[doc = "Interrupt on falling-edge."]
1201 #[inline]
1202 pub fn _1010(self) -> &'a mut W {
1203 self.variant(IRQCW::_1010)
1204 }
1205 #[doc = "Interrupt on either edge."]
1206 #[inline]
1207 pub fn _1011(self) -> &'a mut W {
1208 self.variant(IRQCW::_1011)
1209 }
1210 #[doc = "Interrupt when logic 1."]
1211 #[inline]
1212 pub fn _1100(self) -> &'a mut W {
1213 self.variant(IRQCW::_1100)
1214 }
1215 #[doc = r" Writes raw bits to the field"]
1216 #[inline]
1217 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1218 const MASK: u8 = 15;
1219 const OFFSET: u8 = 16;
1220 self.w.bits &= !((MASK as u32) << OFFSET);
1221 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1222 self.w
1223 }
1224}
1225#[doc = "Values that can be written to the field `ISF`"]
1226pub enum ISFW {
1227 #[doc = "Configured interrupt is not detected."]
1228 _0,
1229 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1230 _1,
1231}
1232impl ISFW {
1233 #[allow(missing_docs)]
1234 #[doc(hidden)]
1235 #[inline]
1236 pub fn _bits(&self) -> bool {
1237 match *self {
1238 ISFW::_0 => false,
1239 ISFW::_1 => true,
1240 }
1241 }
1242}
1243#[doc = r" Proxy"]
1244pub struct _ISFW<'a> {
1245 w: &'a mut W,
1246}
1247impl<'a> _ISFW<'a> {
1248 #[doc = r" Writes `variant` to the field"]
1249 #[inline]
1250 pub fn variant(self, variant: ISFW) -> &'a mut W {
1251 {
1252 self.bit(variant._bits())
1253 }
1254 }
1255 #[doc = "Configured interrupt is not detected."]
1256 #[inline]
1257 pub fn _0(self) -> &'a mut W {
1258 self.variant(ISFW::_0)
1259 }
1260 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
1261 #[inline]
1262 pub fn _1(self) -> &'a mut W {
1263 self.variant(ISFW::_1)
1264 }
1265 #[doc = r" Sets the field bit"]
1266 pub fn set_bit(self) -> &'a mut W {
1267 self.bit(true)
1268 }
1269 #[doc = r" Clears the field bit"]
1270 pub fn clear_bit(self) -> &'a mut W {
1271 self.bit(false)
1272 }
1273 #[doc = r" Writes raw bits to the field"]
1274 #[inline]
1275 pub fn bit(self, value: bool) -> &'a mut W {
1276 const MASK: bool = true;
1277 const OFFSET: u8 = 24;
1278 self.w.bits &= !((MASK as u32) << OFFSET);
1279 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1280 self.w
1281 }
1282}
1283impl R {
1284 #[doc = r" Value of the register as raw bits"]
1285 #[inline]
1286 pub fn bits(&self) -> u32 {
1287 self.bits
1288 }
1289 #[doc = "Bit 0 - Pull Select"]
1290 #[inline]
1291 pub fn ps(&self) -> PSR {
1292 PSR::_from({
1293 const MASK: bool = true;
1294 const OFFSET: u8 = 0;
1295 ((self.bits >> OFFSET) & MASK as u32) != 0
1296 })
1297 }
1298 #[doc = "Bit 1 - Pull Enable"]
1299 #[inline]
1300 pub fn pe(&self) -> PER {
1301 PER::_from({
1302 const MASK: bool = true;
1303 const OFFSET: u8 = 1;
1304 ((self.bits >> OFFSET) & MASK as u32) != 0
1305 })
1306 }
1307 #[doc = "Bit 2 - Slew Rate Enable"]
1308 #[inline]
1309 pub fn sre(&self) -> SRER {
1310 SRER::_from({
1311 const MASK: bool = true;
1312 const OFFSET: u8 = 2;
1313 ((self.bits >> OFFSET) & MASK as u32) != 0
1314 })
1315 }
1316 #[doc = "Bit 4 - Passive Filter Enable"]
1317 #[inline]
1318 pub fn pfe(&self) -> PFER {
1319 PFER::_from({
1320 const MASK: bool = true;
1321 const OFFSET: u8 = 4;
1322 ((self.bits >> OFFSET) & MASK as u32) != 0
1323 })
1324 }
1325 #[doc = "Bit 5 - Open Drain Enable"]
1326 #[inline]
1327 pub fn ode(&self) -> ODER {
1328 ODER::_from({
1329 const MASK: bool = true;
1330 const OFFSET: u8 = 5;
1331 ((self.bits >> OFFSET) & MASK as u32) != 0
1332 })
1333 }
1334 #[doc = "Bit 6 - Drive Strength Enable"]
1335 #[inline]
1336 pub fn dse(&self) -> DSER {
1337 DSER::_from({
1338 const MASK: bool = true;
1339 const OFFSET: u8 = 6;
1340 ((self.bits >> OFFSET) & MASK as u32) != 0
1341 })
1342 }
1343 #[doc = "Bits 8:10 - Pin Mux Control"]
1344 #[inline]
1345 pub fn mux(&self) -> MUXR {
1346 MUXR::_from({
1347 const MASK: u8 = 7;
1348 const OFFSET: u8 = 8;
1349 ((self.bits >> OFFSET) & MASK as u32) as u8
1350 })
1351 }
1352 #[doc = "Bit 15 - Lock Register"]
1353 #[inline]
1354 pub fn lk(&self) -> LKR {
1355 LKR::_from({
1356 const MASK: bool = true;
1357 const OFFSET: u8 = 15;
1358 ((self.bits >> OFFSET) & MASK as u32) != 0
1359 })
1360 }
1361 #[doc = "Bits 16:19 - Interrupt Configuration"]
1362 #[inline]
1363 pub fn irqc(&self) -> IRQCR {
1364 IRQCR::_from({
1365 const MASK: u8 = 15;
1366 const OFFSET: u8 = 16;
1367 ((self.bits >> OFFSET) & MASK as u32) as u8
1368 })
1369 }
1370 #[doc = "Bit 24 - Interrupt Status Flag"]
1371 #[inline]
1372 pub fn isf(&self) -> ISFR {
1373 ISFR::_from({
1374 const MASK: bool = true;
1375 const OFFSET: u8 = 24;
1376 ((self.bits >> OFFSET) & MASK as u32) != 0
1377 })
1378 }
1379}
1380impl W {
1381 #[doc = r" Reset value of the register"]
1382 #[inline]
1383 pub fn reset_value() -> W {
1384 W { bits: 0 }
1385 }
1386 #[doc = r" Writes raw bits to the register"]
1387 #[inline]
1388 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1389 self.bits = bits;
1390 self
1391 }
1392 #[doc = "Bit 0 - Pull Select"]
1393 #[inline]
1394 pub fn ps(&mut self) -> _PSW {
1395 _PSW { w: self }
1396 }
1397 #[doc = "Bit 1 - Pull Enable"]
1398 #[inline]
1399 pub fn pe(&mut self) -> _PEW {
1400 _PEW { w: self }
1401 }
1402 #[doc = "Bit 2 - Slew Rate Enable"]
1403 #[inline]
1404 pub fn sre(&mut self) -> _SREW {
1405 _SREW { w: self }
1406 }
1407 #[doc = "Bit 4 - Passive Filter Enable"]
1408 #[inline]
1409 pub fn pfe(&mut self) -> _PFEW {
1410 _PFEW { w: self }
1411 }
1412 #[doc = "Bit 5 - Open Drain Enable"]
1413 #[inline]
1414 pub fn ode(&mut self) -> _ODEW {
1415 _ODEW { w: self }
1416 }
1417 #[doc = "Bit 6 - Drive Strength Enable"]
1418 #[inline]
1419 pub fn dse(&mut self) -> _DSEW {
1420 _DSEW { w: self }
1421 }
1422 #[doc = "Bits 8:10 - Pin Mux Control"]
1423 #[inline]
1424 pub fn mux(&mut self) -> _MUXW {
1425 _MUXW { w: self }
1426 }
1427 #[doc = "Bit 15 - Lock Register"]
1428 #[inline]
1429 pub fn lk(&mut self) -> _LKW {
1430 _LKW { w: self }
1431 }
1432 #[doc = "Bits 16:19 - Interrupt Configuration"]
1433 #[inline]
1434 pub fn irqc(&mut self) -> _IRQCW {
1435 _IRQCW { w: self }
1436 }
1437 #[doc = "Bit 24 - Interrupt Status Flag"]
1438 #[inline]
1439 pub fn isf(&mut self) -> _ISFW {
1440 _ISFW { w: self }
1441 }
1442}