1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u8,
8}
9impl super::C6 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `VDIV0`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum VDIV0R {
48 #[doc = "Multiply Factor is 24"]
49 _0,
50 #[doc = "Multiply Factor is 25"]
51 _1,
52 #[doc = "Multiply Factor is 26"]
53 _2,
54 #[doc = "Multiply Factor is 27"]
55 _3,
56 #[doc = "Multiply Factor is 28"]
57 _4,
58 #[doc = "Multiply Factor is 29"]
59 _5,
60 #[doc = "Multiply Factor is 30"]
61 _6,
62 #[doc = "Multiply Factor is 31"]
63 _7,
64 #[doc = "Multiply Factor is 32"]
65 _8,
66 #[doc = "Multiply Factor is 33"]
67 _9,
68 #[doc = "Multiply Factor is 34"]
69 _10,
70 #[doc = "Multiply Factor is 35"]
71 _11,
72 #[doc = "Multiply Factor is 36"]
73 _12,
74 #[doc = "Multiply Factor is 37"]
75 _13,
76 #[doc = "Multiply Factor is 38"]
77 _14,
78 #[doc = "Multiply Factor is 39"]
79 _15,
80 #[doc = "Multiply Factor is 40"]
81 _16,
82 #[doc = "Multiply Factor is 41"]
83 _17,
84 #[doc = "Multiply Factor is 42"]
85 _18,
86 #[doc = "Multiply Factor is 43"]
87 _19,
88 #[doc = "Multiply Factor is 44"]
89 _20,
90 #[doc = "Multiply Factor is 45"]
91 _21,
92 #[doc = "Multiply Factor is 46"]
93 _22,
94 #[doc = "Multiply Factor is 47"]
95 _23,
96 #[doc = "Multiply Factor is 48"]
97 _24,
98 #[doc = "Multiply Factor is 49"]
99 _25,
100 #[doc = "Multiply Factor is 50"]
101 _26,
102 #[doc = "Multiply Factor is 51"]
103 _27,
104 #[doc = "Multiply Factor is 52"]
105 _28,
106 #[doc = "Multiply Factor is 53"]
107 _29,
108 #[doc = "Multiply Factor is 54"]
109 _30,
110 #[doc = "Multiply Factor is 55"]
111 _31,
112}
113impl VDIV0R {
114 #[doc = r" Value of the field as raw bits"]
115 #[inline]
116 pub fn bits(&self) -> u8 {
117 match *self {
118 VDIV0R::_0 => 0,
119 VDIV0R::_1 => 1,
120 VDIV0R::_2 => 2,
121 VDIV0R::_3 => 3,
122 VDIV0R::_4 => 4,
123 VDIV0R::_5 => 5,
124 VDIV0R::_6 => 6,
125 VDIV0R::_7 => 7,
126 VDIV0R::_8 => 8,
127 VDIV0R::_9 => 9,
128 VDIV0R::_10 => 10,
129 VDIV0R::_11 => 11,
130 VDIV0R::_12 => 12,
131 VDIV0R::_13 => 13,
132 VDIV0R::_14 => 14,
133 VDIV0R::_15 => 15,
134 VDIV0R::_16 => 16,
135 VDIV0R::_17 => 17,
136 VDIV0R::_18 => 18,
137 VDIV0R::_19 => 19,
138 VDIV0R::_20 => 20,
139 VDIV0R::_21 => 21,
140 VDIV0R::_22 => 22,
141 VDIV0R::_23 => 23,
142 VDIV0R::_24 => 24,
143 VDIV0R::_25 => 25,
144 VDIV0R::_26 => 26,
145 VDIV0R::_27 => 27,
146 VDIV0R::_28 => 28,
147 VDIV0R::_29 => 29,
148 VDIV0R::_30 => 30,
149 VDIV0R::_31 => 31,
150 }
151 }
152 #[allow(missing_docs)]
153 #[doc(hidden)]
154 #[inline]
155 pub fn _from(value: u8) -> VDIV0R {
156 match value {
157 0 => VDIV0R::_0,
158 1 => VDIV0R::_1,
159 2 => VDIV0R::_2,
160 3 => VDIV0R::_3,
161 4 => VDIV0R::_4,
162 5 => VDIV0R::_5,
163 6 => VDIV0R::_6,
164 7 => VDIV0R::_7,
165 8 => VDIV0R::_8,
166 9 => VDIV0R::_9,
167 10 => VDIV0R::_10,
168 11 => VDIV0R::_11,
169 12 => VDIV0R::_12,
170 13 => VDIV0R::_13,
171 14 => VDIV0R::_14,
172 15 => VDIV0R::_15,
173 16 => VDIV0R::_16,
174 17 => VDIV0R::_17,
175 18 => VDIV0R::_18,
176 19 => VDIV0R::_19,
177 20 => VDIV0R::_20,
178 21 => VDIV0R::_21,
179 22 => VDIV0R::_22,
180 23 => VDIV0R::_23,
181 24 => VDIV0R::_24,
182 25 => VDIV0R::_25,
183 26 => VDIV0R::_26,
184 27 => VDIV0R::_27,
185 28 => VDIV0R::_28,
186 29 => VDIV0R::_29,
187 30 => VDIV0R::_30,
188 31 => VDIV0R::_31,
189 _ => unreachable!(),
190 }
191 }
192 #[doc = "Checks if the value of the field is `_0`"]
193 #[inline]
194 pub fn is_0(&self) -> bool {
195 *self == VDIV0R::_0
196 }
197 #[doc = "Checks if the value of the field is `_1`"]
198 #[inline]
199 pub fn is_1(&self) -> bool {
200 *self == VDIV0R::_1
201 }
202 #[doc = "Checks if the value of the field is `_2`"]
203 #[inline]
204 pub fn is_2(&self) -> bool {
205 *self == VDIV0R::_2
206 }
207 #[doc = "Checks if the value of the field is `_3`"]
208 #[inline]
209 pub fn is_3(&self) -> bool {
210 *self == VDIV0R::_3
211 }
212 #[doc = "Checks if the value of the field is `_4`"]
213 #[inline]
214 pub fn is_4(&self) -> bool {
215 *self == VDIV0R::_4
216 }
217 #[doc = "Checks if the value of the field is `_5`"]
218 #[inline]
219 pub fn is_5(&self) -> bool {
220 *self == VDIV0R::_5
221 }
222 #[doc = "Checks if the value of the field is `_6`"]
223 #[inline]
224 pub fn is_6(&self) -> bool {
225 *self == VDIV0R::_6
226 }
227 #[doc = "Checks if the value of the field is `_7`"]
228 #[inline]
229 pub fn is_7(&self) -> bool {
230 *self == VDIV0R::_7
231 }
232 #[doc = "Checks if the value of the field is `_8`"]
233 #[inline]
234 pub fn is_8(&self) -> bool {
235 *self == VDIV0R::_8
236 }
237 #[doc = "Checks if the value of the field is `_9`"]
238 #[inline]
239 pub fn is_9(&self) -> bool {
240 *self == VDIV0R::_9
241 }
242 #[doc = "Checks if the value of the field is `_10`"]
243 #[inline]
244 pub fn is_10(&self) -> bool {
245 *self == VDIV0R::_10
246 }
247 #[doc = "Checks if the value of the field is `_11`"]
248 #[inline]
249 pub fn is_11(&self) -> bool {
250 *self == VDIV0R::_11
251 }
252 #[doc = "Checks if the value of the field is `_12`"]
253 #[inline]
254 pub fn is_12(&self) -> bool {
255 *self == VDIV0R::_12
256 }
257 #[doc = "Checks if the value of the field is `_13`"]
258 #[inline]
259 pub fn is_13(&self) -> bool {
260 *self == VDIV0R::_13
261 }
262 #[doc = "Checks if the value of the field is `_14`"]
263 #[inline]
264 pub fn is_14(&self) -> bool {
265 *self == VDIV0R::_14
266 }
267 #[doc = "Checks if the value of the field is `_15`"]
268 #[inline]
269 pub fn is_15(&self) -> bool {
270 *self == VDIV0R::_15
271 }
272 #[doc = "Checks if the value of the field is `_16`"]
273 #[inline]
274 pub fn is_16(&self) -> bool {
275 *self == VDIV0R::_16
276 }
277 #[doc = "Checks if the value of the field is `_17`"]
278 #[inline]
279 pub fn is_17(&self) -> bool {
280 *self == VDIV0R::_17
281 }
282 #[doc = "Checks if the value of the field is `_18`"]
283 #[inline]
284 pub fn is_18(&self) -> bool {
285 *self == VDIV0R::_18
286 }
287 #[doc = "Checks if the value of the field is `_19`"]
288 #[inline]
289 pub fn is_19(&self) -> bool {
290 *self == VDIV0R::_19
291 }
292 #[doc = "Checks if the value of the field is `_20`"]
293 #[inline]
294 pub fn is_20(&self) -> bool {
295 *self == VDIV0R::_20
296 }
297 #[doc = "Checks if the value of the field is `_21`"]
298 #[inline]
299 pub fn is_21(&self) -> bool {
300 *self == VDIV0R::_21
301 }
302 #[doc = "Checks if the value of the field is `_22`"]
303 #[inline]
304 pub fn is_22(&self) -> bool {
305 *self == VDIV0R::_22
306 }
307 #[doc = "Checks if the value of the field is `_23`"]
308 #[inline]
309 pub fn is_23(&self) -> bool {
310 *self == VDIV0R::_23
311 }
312 #[doc = "Checks if the value of the field is `_24`"]
313 #[inline]
314 pub fn is_24(&self) -> bool {
315 *self == VDIV0R::_24
316 }
317 #[doc = "Checks if the value of the field is `_25`"]
318 #[inline]
319 pub fn is_25(&self) -> bool {
320 *self == VDIV0R::_25
321 }
322 #[doc = "Checks if the value of the field is `_26`"]
323 #[inline]
324 pub fn is_26(&self) -> bool {
325 *self == VDIV0R::_26
326 }
327 #[doc = "Checks if the value of the field is `_27`"]
328 #[inline]
329 pub fn is_27(&self) -> bool {
330 *self == VDIV0R::_27
331 }
332 #[doc = "Checks if the value of the field is `_28`"]
333 #[inline]
334 pub fn is_28(&self) -> bool {
335 *self == VDIV0R::_28
336 }
337 #[doc = "Checks if the value of the field is `_29`"]
338 #[inline]
339 pub fn is_29(&self) -> bool {
340 *self == VDIV0R::_29
341 }
342 #[doc = "Checks if the value of the field is `_30`"]
343 #[inline]
344 pub fn is_30(&self) -> bool {
345 *self == VDIV0R::_30
346 }
347 #[doc = "Checks if the value of the field is `_31`"]
348 #[inline]
349 pub fn is_31(&self) -> bool {
350 *self == VDIV0R::_31
351 }
352}
353#[doc = "Possible values of the field `CME0`"]
354#[derive(Clone, Copy, Debug, PartialEq)]
355pub enum CME0R {
356 #[doc = "External clock monitor is disabled for OSC0."]
357 _0,
358 #[doc = "External clock monitor is enabled for OSC0."]
359 _1,
360}
361impl CME0R {
362 #[doc = r" Returns `true` if the bit is clear (0)"]
363 #[inline]
364 pub fn bit_is_clear(&self) -> bool {
365 !self.bit()
366 }
367 #[doc = r" Returns `true` if the bit is set (1)"]
368 #[inline]
369 pub fn bit_is_set(&self) -> bool {
370 self.bit()
371 }
372 #[doc = r" Value of the field as raw bits"]
373 #[inline]
374 pub fn bit(&self) -> bool {
375 match *self {
376 CME0R::_0 => false,
377 CME0R::_1 => true,
378 }
379 }
380 #[allow(missing_docs)]
381 #[doc(hidden)]
382 #[inline]
383 pub fn _from(value: bool) -> CME0R {
384 match value {
385 false => CME0R::_0,
386 true => CME0R::_1,
387 }
388 }
389 #[doc = "Checks if the value of the field is `_0`"]
390 #[inline]
391 pub fn is_0(&self) -> bool {
392 *self == CME0R::_0
393 }
394 #[doc = "Checks if the value of the field is `_1`"]
395 #[inline]
396 pub fn is_1(&self) -> bool {
397 *self == CME0R::_1
398 }
399}
400#[doc = "Possible values of the field `PLLS`"]
401#[derive(Clone, Copy, Debug, PartialEq)]
402pub enum PLLSR {
403 #[doc = "FLL is selected."]
404 _0,
405 #[doc = "PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit)."]
406 _1,
407}
408impl PLLSR {
409 #[doc = r" Returns `true` if the bit is clear (0)"]
410 #[inline]
411 pub fn bit_is_clear(&self) -> bool {
412 !self.bit()
413 }
414 #[doc = r" Returns `true` if the bit is set (1)"]
415 #[inline]
416 pub fn bit_is_set(&self) -> bool {
417 self.bit()
418 }
419 #[doc = r" Value of the field as raw bits"]
420 #[inline]
421 pub fn bit(&self) -> bool {
422 match *self {
423 PLLSR::_0 => false,
424 PLLSR::_1 => true,
425 }
426 }
427 #[allow(missing_docs)]
428 #[doc(hidden)]
429 #[inline]
430 pub fn _from(value: bool) -> PLLSR {
431 match value {
432 false => PLLSR::_0,
433 true => PLLSR::_1,
434 }
435 }
436 #[doc = "Checks if the value of the field is `_0`"]
437 #[inline]
438 pub fn is_0(&self) -> bool {
439 *self == PLLSR::_0
440 }
441 #[doc = "Checks if the value of the field is `_1`"]
442 #[inline]
443 pub fn is_1(&self) -> bool {
444 *self == PLLSR::_1
445 }
446}
447#[doc = "Possible values of the field `LOLIE0`"]
448#[derive(Clone, Copy, Debug, PartialEq)]
449pub enum LOLIE0R {
450 #[doc = "No interrupt request is generated on loss of lock."]
451 _0,
452 #[doc = "Generate an interrupt request on loss of lock."]
453 _1,
454}
455impl LOLIE0R {
456 #[doc = r" Returns `true` if the bit is clear (0)"]
457 #[inline]
458 pub fn bit_is_clear(&self) -> bool {
459 !self.bit()
460 }
461 #[doc = r" Returns `true` if the bit is set (1)"]
462 #[inline]
463 pub fn bit_is_set(&self) -> bool {
464 self.bit()
465 }
466 #[doc = r" Value of the field as raw bits"]
467 #[inline]
468 pub fn bit(&self) -> bool {
469 match *self {
470 LOLIE0R::_0 => false,
471 LOLIE0R::_1 => true,
472 }
473 }
474 #[allow(missing_docs)]
475 #[doc(hidden)]
476 #[inline]
477 pub fn _from(value: bool) -> LOLIE0R {
478 match value {
479 false => LOLIE0R::_0,
480 true => LOLIE0R::_1,
481 }
482 }
483 #[doc = "Checks if the value of the field is `_0`"]
484 #[inline]
485 pub fn is_0(&self) -> bool {
486 *self == LOLIE0R::_0
487 }
488 #[doc = "Checks if the value of the field is `_1`"]
489 #[inline]
490 pub fn is_1(&self) -> bool {
491 *self == LOLIE0R::_1
492 }
493}
494#[doc = "Values that can be written to the field `VDIV0`"]
495pub enum VDIV0W {
496 #[doc = "Multiply Factor is 24"]
497 _0,
498 #[doc = "Multiply Factor is 25"]
499 _1,
500 #[doc = "Multiply Factor is 26"]
501 _2,
502 #[doc = "Multiply Factor is 27"]
503 _3,
504 #[doc = "Multiply Factor is 28"]
505 _4,
506 #[doc = "Multiply Factor is 29"]
507 _5,
508 #[doc = "Multiply Factor is 30"]
509 _6,
510 #[doc = "Multiply Factor is 31"]
511 _7,
512 #[doc = "Multiply Factor is 32"]
513 _8,
514 #[doc = "Multiply Factor is 33"]
515 _9,
516 #[doc = "Multiply Factor is 34"]
517 _10,
518 #[doc = "Multiply Factor is 35"]
519 _11,
520 #[doc = "Multiply Factor is 36"]
521 _12,
522 #[doc = "Multiply Factor is 37"]
523 _13,
524 #[doc = "Multiply Factor is 38"]
525 _14,
526 #[doc = "Multiply Factor is 39"]
527 _15,
528 #[doc = "Multiply Factor is 40"]
529 _16,
530 #[doc = "Multiply Factor is 41"]
531 _17,
532 #[doc = "Multiply Factor is 42"]
533 _18,
534 #[doc = "Multiply Factor is 43"]
535 _19,
536 #[doc = "Multiply Factor is 44"]
537 _20,
538 #[doc = "Multiply Factor is 45"]
539 _21,
540 #[doc = "Multiply Factor is 46"]
541 _22,
542 #[doc = "Multiply Factor is 47"]
543 _23,
544 #[doc = "Multiply Factor is 48"]
545 _24,
546 #[doc = "Multiply Factor is 49"]
547 _25,
548 #[doc = "Multiply Factor is 50"]
549 _26,
550 #[doc = "Multiply Factor is 51"]
551 _27,
552 #[doc = "Multiply Factor is 52"]
553 _28,
554 #[doc = "Multiply Factor is 53"]
555 _29,
556 #[doc = "Multiply Factor is 54"]
557 _30,
558 #[doc = "Multiply Factor is 55"]
559 _31,
560}
561impl VDIV0W {
562 #[allow(missing_docs)]
563 #[doc(hidden)]
564 #[inline]
565 pub fn _bits(&self) -> u8 {
566 match *self {
567 VDIV0W::_0 => 0,
568 VDIV0W::_1 => 1,
569 VDIV0W::_2 => 2,
570 VDIV0W::_3 => 3,
571 VDIV0W::_4 => 4,
572 VDIV0W::_5 => 5,
573 VDIV0W::_6 => 6,
574 VDIV0W::_7 => 7,
575 VDIV0W::_8 => 8,
576 VDIV0W::_9 => 9,
577 VDIV0W::_10 => 10,
578 VDIV0W::_11 => 11,
579 VDIV0W::_12 => 12,
580 VDIV0W::_13 => 13,
581 VDIV0W::_14 => 14,
582 VDIV0W::_15 => 15,
583 VDIV0W::_16 => 16,
584 VDIV0W::_17 => 17,
585 VDIV0W::_18 => 18,
586 VDIV0W::_19 => 19,
587 VDIV0W::_20 => 20,
588 VDIV0W::_21 => 21,
589 VDIV0W::_22 => 22,
590 VDIV0W::_23 => 23,
591 VDIV0W::_24 => 24,
592 VDIV0W::_25 => 25,
593 VDIV0W::_26 => 26,
594 VDIV0W::_27 => 27,
595 VDIV0W::_28 => 28,
596 VDIV0W::_29 => 29,
597 VDIV0W::_30 => 30,
598 VDIV0W::_31 => 31,
599 }
600 }
601}
602#[doc = r" Proxy"]
603pub struct _VDIV0W<'a> {
604 w: &'a mut W,
605}
606impl<'a> _VDIV0W<'a> {
607 #[doc = r" Writes `variant` to the field"]
608 #[inline]
609 pub fn variant(self, variant: VDIV0W) -> &'a mut W {
610 {
611 self.bits(variant._bits())
612 }
613 }
614 #[doc = "Multiply Factor is 24"]
615 #[inline]
616 pub fn _0(self) -> &'a mut W {
617 self.variant(VDIV0W::_0)
618 }
619 #[doc = "Multiply Factor is 25"]
620 #[inline]
621 pub fn _1(self) -> &'a mut W {
622 self.variant(VDIV0W::_1)
623 }
624 #[doc = "Multiply Factor is 26"]
625 #[inline]
626 pub fn _2(self) -> &'a mut W {
627 self.variant(VDIV0W::_2)
628 }
629 #[doc = "Multiply Factor is 27"]
630 #[inline]
631 pub fn _3(self) -> &'a mut W {
632 self.variant(VDIV0W::_3)
633 }
634 #[doc = "Multiply Factor is 28"]
635 #[inline]
636 pub fn _4(self) -> &'a mut W {
637 self.variant(VDIV0W::_4)
638 }
639 #[doc = "Multiply Factor is 29"]
640 #[inline]
641 pub fn _5(self) -> &'a mut W {
642 self.variant(VDIV0W::_5)
643 }
644 #[doc = "Multiply Factor is 30"]
645 #[inline]
646 pub fn _6(self) -> &'a mut W {
647 self.variant(VDIV0W::_6)
648 }
649 #[doc = "Multiply Factor is 31"]
650 #[inline]
651 pub fn _7(self) -> &'a mut W {
652 self.variant(VDIV0W::_7)
653 }
654 #[doc = "Multiply Factor is 32"]
655 #[inline]
656 pub fn _8(self) -> &'a mut W {
657 self.variant(VDIV0W::_8)
658 }
659 #[doc = "Multiply Factor is 33"]
660 #[inline]
661 pub fn _9(self) -> &'a mut W {
662 self.variant(VDIV0W::_9)
663 }
664 #[doc = "Multiply Factor is 34"]
665 #[inline]
666 pub fn _10(self) -> &'a mut W {
667 self.variant(VDIV0W::_10)
668 }
669 #[doc = "Multiply Factor is 35"]
670 #[inline]
671 pub fn _11(self) -> &'a mut W {
672 self.variant(VDIV0W::_11)
673 }
674 #[doc = "Multiply Factor is 36"]
675 #[inline]
676 pub fn _12(self) -> &'a mut W {
677 self.variant(VDIV0W::_12)
678 }
679 #[doc = "Multiply Factor is 37"]
680 #[inline]
681 pub fn _13(self) -> &'a mut W {
682 self.variant(VDIV0W::_13)
683 }
684 #[doc = "Multiply Factor is 38"]
685 #[inline]
686 pub fn _14(self) -> &'a mut W {
687 self.variant(VDIV0W::_14)
688 }
689 #[doc = "Multiply Factor is 39"]
690 #[inline]
691 pub fn _15(self) -> &'a mut W {
692 self.variant(VDIV0W::_15)
693 }
694 #[doc = "Multiply Factor is 40"]
695 #[inline]
696 pub fn _16(self) -> &'a mut W {
697 self.variant(VDIV0W::_16)
698 }
699 #[doc = "Multiply Factor is 41"]
700 #[inline]
701 pub fn _17(self) -> &'a mut W {
702 self.variant(VDIV0W::_17)
703 }
704 #[doc = "Multiply Factor is 42"]
705 #[inline]
706 pub fn _18(self) -> &'a mut W {
707 self.variant(VDIV0W::_18)
708 }
709 #[doc = "Multiply Factor is 43"]
710 #[inline]
711 pub fn _19(self) -> &'a mut W {
712 self.variant(VDIV0W::_19)
713 }
714 #[doc = "Multiply Factor is 44"]
715 #[inline]
716 pub fn _20(self) -> &'a mut W {
717 self.variant(VDIV0W::_20)
718 }
719 #[doc = "Multiply Factor is 45"]
720 #[inline]
721 pub fn _21(self) -> &'a mut W {
722 self.variant(VDIV0W::_21)
723 }
724 #[doc = "Multiply Factor is 46"]
725 #[inline]
726 pub fn _22(self) -> &'a mut W {
727 self.variant(VDIV0W::_22)
728 }
729 #[doc = "Multiply Factor is 47"]
730 #[inline]
731 pub fn _23(self) -> &'a mut W {
732 self.variant(VDIV0W::_23)
733 }
734 #[doc = "Multiply Factor is 48"]
735 #[inline]
736 pub fn _24(self) -> &'a mut W {
737 self.variant(VDIV0W::_24)
738 }
739 #[doc = "Multiply Factor is 49"]
740 #[inline]
741 pub fn _25(self) -> &'a mut W {
742 self.variant(VDIV0W::_25)
743 }
744 #[doc = "Multiply Factor is 50"]
745 #[inline]
746 pub fn _26(self) -> &'a mut W {
747 self.variant(VDIV0W::_26)
748 }
749 #[doc = "Multiply Factor is 51"]
750 #[inline]
751 pub fn _27(self) -> &'a mut W {
752 self.variant(VDIV0W::_27)
753 }
754 #[doc = "Multiply Factor is 52"]
755 #[inline]
756 pub fn _28(self) -> &'a mut W {
757 self.variant(VDIV0W::_28)
758 }
759 #[doc = "Multiply Factor is 53"]
760 #[inline]
761 pub fn _29(self) -> &'a mut W {
762 self.variant(VDIV0W::_29)
763 }
764 #[doc = "Multiply Factor is 54"]
765 #[inline]
766 pub fn _30(self) -> &'a mut W {
767 self.variant(VDIV0W::_30)
768 }
769 #[doc = "Multiply Factor is 55"]
770 #[inline]
771 pub fn _31(self) -> &'a mut W {
772 self.variant(VDIV0W::_31)
773 }
774 #[doc = r" Writes raw bits to the field"]
775 #[inline]
776 pub fn bits(self, value: u8) -> &'a mut W {
777 const MASK: u8 = 31;
778 const OFFSET: u8 = 0;
779 self.w.bits &= !((MASK as u8) << OFFSET);
780 self.w.bits |= ((value & MASK) as u8) << OFFSET;
781 self.w
782 }
783}
784#[doc = "Values that can be written to the field `CME0`"]
785pub enum CME0W {
786 #[doc = "External clock monitor is disabled for OSC0."]
787 _0,
788 #[doc = "External clock monitor is enabled for OSC0."]
789 _1,
790}
791impl CME0W {
792 #[allow(missing_docs)]
793 #[doc(hidden)]
794 #[inline]
795 pub fn _bits(&self) -> bool {
796 match *self {
797 CME0W::_0 => false,
798 CME0W::_1 => true,
799 }
800 }
801}
802#[doc = r" Proxy"]
803pub struct _CME0W<'a> {
804 w: &'a mut W,
805}
806impl<'a> _CME0W<'a> {
807 #[doc = r" Writes `variant` to the field"]
808 #[inline]
809 pub fn variant(self, variant: CME0W) -> &'a mut W {
810 {
811 self.bit(variant._bits())
812 }
813 }
814 #[doc = "External clock monitor is disabled for OSC0."]
815 #[inline]
816 pub fn _0(self) -> &'a mut W {
817 self.variant(CME0W::_0)
818 }
819 #[doc = "External clock monitor is enabled for OSC0."]
820 #[inline]
821 pub fn _1(self) -> &'a mut W {
822 self.variant(CME0W::_1)
823 }
824 #[doc = r" Sets the field bit"]
825 pub fn set_bit(self) -> &'a mut W {
826 self.bit(true)
827 }
828 #[doc = r" Clears the field bit"]
829 pub fn clear_bit(self) -> &'a mut W {
830 self.bit(false)
831 }
832 #[doc = r" Writes raw bits to the field"]
833 #[inline]
834 pub fn bit(self, value: bool) -> &'a mut W {
835 const MASK: bool = true;
836 const OFFSET: u8 = 5;
837 self.w.bits &= !((MASK as u8) << OFFSET);
838 self.w.bits |= ((value & MASK) as u8) << OFFSET;
839 self.w
840 }
841}
842#[doc = "Values that can be written to the field `PLLS`"]
843pub enum PLLSW {
844 #[doc = "FLL is selected."]
845 _0,
846 #[doc = "PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit)."]
847 _1,
848}
849impl PLLSW {
850 #[allow(missing_docs)]
851 #[doc(hidden)]
852 #[inline]
853 pub fn _bits(&self) -> bool {
854 match *self {
855 PLLSW::_0 => false,
856 PLLSW::_1 => true,
857 }
858 }
859}
860#[doc = r" Proxy"]
861pub struct _PLLSW<'a> {
862 w: &'a mut W,
863}
864impl<'a> _PLLSW<'a> {
865 #[doc = r" Writes `variant` to the field"]
866 #[inline]
867 pub fn variant(self, variant: PLLSW) -> &'a mut W {
868 {
869 self.bit(variant._bits())
870 }
871 }
872 #[doc = "FLL is selected."]
873 #[inline]
874 pub fn _0(self) -> &'a mut W {
875 self.variant(PLLSW::_0)
876 }
877 #[doc = "PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit)."]
878 #[inline]
879 pub fn _1(self) -> &'a mut W {
880 self.variant(PLLSW::_1)
881 }
882 #[doc = r" Sets the field bit"]
883 pub fn set_bit(self) -> &'a mut W {
884 self.bit(true)
885 }
886 #[doc = r" Clears the field bit"]
887 pub fn clear_bit(self) -> &'a mut W {
888 self.bit(false)
889 }
890 #[doc = r" Writes raw bits to the field"]
891 #[inline]
892 pub fn bit(self, value: bool) -> &'a mut W {
893 const MASK: bool = true;
894 const OFFSET: u8 = 6;
895 self.w.bits &= !((MASK as u8) << OFFSET);
896 self.w.bits |= ((value & MASK) as u8) << OFFSET;
897 self.w
898 }
899}
900#[doc = "Values that can be written to the field `LOLIE0`"]
901pub enum LOLIE0W {
902 #[doc = "No interrupt request is generated on loss of lock."]
903 _0,
904 #[doc = "Generate an interrupt request on loss of lock."]
905 _1,
906}
907impl LOLIE0W {
908 #[allow(missing_docs)]
909 #[doc(hidden)]
910 #[inline]
911 pub fn _bits(&self) -> bool {
912 match *self {
913 LOLIE0W::_0 => false,
914 LOLIE0W::_1 => true,
915 }
916 }
917}
918#[doc = r" Proxy"]
919pub struct _LOLIE0W<'a> {
920 w: &'a mut W,
921}
922impl<'a> _LOLIE0W<'a> {
923 #[doc = r" Writes `variant` to the field"]
924 #[inline]
925 pub fn variant(self, variant: LOLIE0W) -> &'a mut W {
926 {
927 self.bit(variant._bits())
928 }
929 }
930 #[doc = "No interrupt request is generated on loss of lock."]
931 #[inline]
932 pub fn _0(self) -> &'a mut W {
933 self.variant(LOLIE0W::_0)
934 }
935 #[doc = "Generate an interrupt request on loss of lock."]
936 #[inline]
937 pub fn _1(self) -> &'a mut W {
938 self.variant(LOLIE0W::_1)
939 }
940 #[doc = r" Sets the field bit"]
941 pub fn set_bit(self) -> &'a mut W {
942 self.bit(true)
943 }
944 #[doc = r" Clears the field bit"]
945 pub fn clear_bit(self) -> &'a mut W {
946 self.bit(false)
947 }
948 #[doc = r" Writes raw bits to the field"]
949 #[inline]
950 pub fn bit(self, value: bool) -> &'a mut W {
951 const MASK: bool = true;
952 const OFFSET: u8 = 7;
953 self.w.bits &= !((MASK as u8) << OFFSET);
954 self.w.bits |= ((value & MASK) as u8) << OFFSET;
955 self.w
956 }
957}
958impl R {
959 #[doc = r" Value of the register as raw bits"]
960 #[inline]
961 pub fn bits(&self) -> u8 {
962 self.bits
963 }
964 #[doc = "Bits 0:4 - VCO 0 Divider"]
965 #[inline]
966 pub fn vdiv0(&self) -> VDIV0R {
967 VDIV0R::_from({
968 const MASK: u8 = 31;
969 const OFFSET: u8 = 0;
970 ((self.bits >> OFFSET) & MASK as u8) as u8
971 })
972 }
973 #[doc = "Bit 5 - Clock Monitor Enable"]
974 #[inline]
975 pub fn cme0(&self) -> CME0R {
976 CME0R::_from({
977 const MASK: bool = true;
978 const OFFSET: u8 = 5;
979 ((self.bits >> OFFSET) & MASK as u8) != 0
980 })
981 }
982 #[doc = "Bit 6 - PLL Select"]
983 #[inline]
984 pub fn plls(&self) -> PLLSR {
985 PLLSR::_from({
986 const MASK: bool = true;
987 const OFFSET: u8 = 6;
988 ((self.bits >> OFFSET) & MASK as u8) != 0
989 })
990 }
991 #[doc = "Bit 7 - Loss of Lock Interrrupt Enable"]
992 #[inline]
993 pub fn lolie0(&self) -> LOLIE0R {
994 LOLIE0R::_from({
995 const MASK: bool = true;
996 const OFFSET: u8 = 7;
997 ((self.bits >> OFFSET) & MASK as u8) != 0
998 })
999 }
1000}
1001impl W {
1002 #[doc = r" Reset value of the register"]
1003 #[inline]
1004 pub fn reset_value() -> W {
1005 W { bits: 0 }
1006 }
1007 #[doc = r" Writes raw bits to the register"]
1008 #[inline]
1009 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
1010 self.bits = bits;
1011 self
1012 }
1013 #[doc = "Bits 0:4 - VCO 0 Divider"]
1014 #[inline]
1015 pub fn vdiv0(&mut self) -> _VDIV0W {
1016 _VDIV0W { w: self }
1017 }
1018 #[doc = "Bit 5 - Clock Monitor Enable"]
1019 #[inline]
1020 pub fn cme0(&mut self) -> _CME0W {
1021 _CME0W { w: self }
1022 }
1023 #[doc = "Bit 6 - PLL Select"]
1024 #[inline]
1025 pub fn plls(&mut self) -> _PLLSW {
1026 _PLLSW { w: self }
1027 }
1028 #[doc = "Bit 7 - Loss of Lock Interrrupt Enable"]
1029 #[inline]
1030 pub fn lolie0(&mut self) -> _LOLIE0W {
1031 _LOLIE0W { w: self }
1032 }
1033}