1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u8,
8}
9impl super::C1 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `IREFSTEN`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum IREFSTENR {
48 #[doc = "Internal reference clock is disabled in Stop mode."]
49 _0,
50 #[doc = "Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode."]
51 _1,
52}
53impl IREFSTENR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 IREFSTENR::_0 => false,
69 IREFSTENR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> IREFSTENR {
76 match value {
77 false => IREFSTENR::_0,
78 true => IREFSTENR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == IREFSTENR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == IREFSTENR::_1
90 }
91}
92#[doc = "Possible values of the field `IRCLKEN`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum IRCLKENR {
95 #[doc = "MCGIRCLK inactive."]
96 _0,
97 #[doc = "MCGIRCLK active."]
98 _1,
99}
100impl IRCLKENR {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 IRCLKENR::_0 => false,
116 IRCLKENR::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> IRCLKENR {
123 match value {
124 false => IRCLKENR::_0,
125 true => IRCLKENR::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == IRCLKENR::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == IRCLKENR::_1
137 }
138}
139#[doc = "Possible values of the field `IREFS`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum IREFSR {
142 #[doc = "External reference clock is selected."]
143 _0,
144 #[doc = "The slow internal reference clock is selected."]
145 _1,
146}
147impl IREFSR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 IREFSR::_0 => false,
163 IREFSR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> IREFSR {
170 match value {
171 false => IREFSR::_0,
172 true => IREFSR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == IREFSR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == IREFSR::_1
184 }
185}
186#[doc = "Possible values of the field `FRDIV`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum FRDIVR {
189 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32."]
190 _000,
191 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64."]
192 _001,
193 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128."]
194 _010,
195 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256."]
196 _011,
197 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512."]
198 _100,
199 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024."]
200 _101,
201 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 ."]
202 _110,
203 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 ."]
204 _111,
205}
206impl FRDIVR {
207 #[doc = r" Value of the field as raw bits"]
208 #[inline]
209 pub fn bits(&self) -> u8 {
210 match *self {
211 FRDIVR::_000 => 0,
212 FRDIVR::_001 => 1,
213 FRDIVR::_010 => 2,
214 FRDIVR::_011 => 3,
215 FRDIVR::_100 => 4,
216 FRDIVR::_101 => 5,
217 FRDIVR::_110 => 6,
218 FRDIVR::_111 => 7,
219 }
220 }
221 #[allow(missing_docs)]
222 #[doc(hidden)]
223 #[inline]
224 pub fn _from(value: u8) -> FRDIVR {
225 match value {
226 0 => FRDIVR::_000,
227 1 => FRDIVR::_001,
228 2 => FRDIVR::_010,
229 3 => FRDIVR::_011,
230 4 => FRDIVR::_100,
231 5 => FRDIVR::_101,
232 6 => FRDIVR::_110,
233 7 => FRDIVR::_111,
234 _ => unreachable!(),
235 }
236 }
237 #[doc = "Checks if the value of the field is `_000`"]
238 #[inline]
239 pub fn is_000(&self) -> bool {
240 *self == FRDIVR::_000
241 }
242 #[doc = "Checks if the value of the field is `_001`"]
243 #[inline]
244 pub fn is_001(&self) -> bool {
245 *self == FRDIVR::_001
246 }
247 #[doc = "Checks if the value of the field is `_010`"]
248 #[inline]
249 pub fn is_010(&self) -> bool {
250 *self == FRDIVR::_010
251 }
252 #[doc = "Checks if the value of the field is `_011`"]
253 #[inline]
254 pub fn is_011(&self) -> bool {
255 *self == FRDIVR::_011
256 }
257 #[doc = "Checks if the value of the field is `_100`"]
258 #[inline]
259 pub fn is_100(&self) -> bool {
260 *self == FRDIVR::_100
261 }
262 #[doc = "Checks if the value of the field is `_101`"]
263 #[inline]
264 pub fn is_101(&self) -> bool {
265 *self == FRDIVR::_101
266 }
267 #[doc = "Checks if the value of the field is `_110`"]
268 #[inline]
269 pub fn is_110(&self) -> bool {
270 *self == FRDIVR::_110
271 }
272 #[doc = "Checks if the value of the field is `_111`"]
273 #[inline]
274 pub fn is_111(&self) -> bool {
275 *self == FRDIVR::_111
276 }
277}
278#[doc = "Possible values of the field `CLKS`"]
279#[derive(Clone, Copy, Debug, PartialEq)]
280pub enum CLKSR {
281 #[doc = "Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit)."]
282 _00,
283 #[doc = "Encoding 1 - Internal reference clock is selected."]
284 _01,
285 #[doc = "Encoding 2 - External reference clock is selected."]
286 _10,
287 #[doc = "Encoding 3 - Reserved."]
288 _11,
289}
290impl CLKSR {
291 #[doc = r" Value of the field as raw bits"]
292 #[inline]
293 pub fn bits(&self) -> u8 {
294 match *self {
295 CLKSR::_00 => 0,
296 CLKSR::_01 => 1,
297 CLKSR::_10 => 2,
298 CLKSR::_11 => 3,
299 }
300 }
301 #[allow(missing_docs)]
302 #[doc(hidden)]
303 #[inline]
304 pub fn _from(value: u8) -> CLKSR {
305 match value {
306 0 => CLKSR::_00,
307 1 => CLKSR::_01,
308 2 => CLKSR::_10,
309 3 => CLKSR::_11,
310 _ => unreachable!(),
311 }
312 }
313 #[doc = "Checks if the value of the field is `_00`"]
314 #[inline]
315 pub fn is_00(&self) -> bool {
316 *self == CLKSR::_00
317 }
318 #[doc = "Checks if the value of the field is `_01`"]
319 #[inline]
320 pub fn is_01(&self) -> bool {
321 *self == CLKSR::_01
322 }
323 #[doc = "Checks if the value of the field is `_10`"]
324 #[inline]
325 pub fn is_10(&self) -> bool {
326 *self == CLKSR::_10
327 }
328 #[doc = "Checks if the value of the field is `_11`"]
329 #[inline]
330 pub fn is_11(&self) -> bool {
331 *self == CLKSR::_11
332 }
333}
334#[doc = "Values that can be written to the field `IREFSTEN`"]
335pub enum IREFSTENW {
336 #[doc = "Internal reference clock is disabled in Stop mode."]
337 _0,
338 #[doc = "Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode."]
339 _1,
340}
341impl IREFSTENW {
342 #[allow(missing_docs)]
343 #[doc(hidden)]
344 #[inline]
345 pub fn _bits(&self) -> bool {
346 match *self {
347 IREFSTENW::_0 => false,
348 IREFSTENW::_1 => true,
349 }
350 }
351}
352#[doc = r" Proxy"]
353pub struct _IREFSTENW<'a> {
354 w: &'a mut W,
355}
356impl<'a> _IREFSTENW<'a> {
357 #[doc = r" Writes `variant` to the field"]
358 #[inline]
359 pub fn variant(self, variant: IREFSTENW) -> &'a mut W {
360 {
361 self.bit(variant._bits())
362 }
363 }
364 #[doc = "Internal reference clock is disabled in Stop mode."]
365 #[inline]
366 pub fn _0(self) -> &'a mut W {
367 self.variant(IREFSTENW::_0)
368 }
369 #[doc = "Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode."]
370 #[inline]
371 pub fn _1(self) -> &'a mut W {
372 self.variant(IREFSTENW::_1)
373 }
374 #[doc = r" Sets the field bit"]
375 pub fn set_bit(self) -> &'a mut W {
376 self.bit(true)
377 }
378 #[doc = r" Clears the field bit"]
379 pub fn clear_bit(self) -> &'a mut W {
380 self.bit(false)
381 }
382 #[doc = r" Writes raw bits to the field"]
383 #[inline]
384 pub fn bit(self, value: bool) -> &'a mut W {
385 const MASK: bool = true;
386 const OFFSET: u8 = 0;
387 self.w.bits &= !((MASK as u8) << OFFSET);
388 self.w.bits |= ((value & MASK) as u8) << OFFSET;
389 self.w
390 }
391}
392#[doc = "Values that can be written to the field `IRCLKEN`"]
393pub enum IRCLKENW {
394 #[doc = "MCGIRCLK inactive."]
395 _0,
396 #[doc = "MCGIRCLK active."]
397 _1,
398}
399impl IRCLKENW {
400 #[allow(missing_docs)]
401 #[doc(hidden)]
402 #[inline]
403 pub fn _bits(&self) -> bool {
404 match *self {
405 IRCLKENW::_0 => false,
406 IRCLKENW::_1 => true,
407 }
408 }
409}
410#[doc = r" Proxy"]
411pub struct _IRCLKENW<'a> {
412 w: &'a mut W,
413}
414impl<'a> _IRCLKENW<'a> {
415 #[doc = r" Writes `variant` to the field"]
416 #[inline]
417 pub fn variant(self, variant: IRCLKENW) -> &'a mut W {
418 {
419 self.bit(variant._bits())
420 }
421 }
422 #[doc = "MCGIRCLK inactive."]
423 #[inline]
424 pub fn _0(self) -> &'a mut W {
425 self.variant(IRCLKENW::_0)
426 }
427 #[doc = "MCGIRCLK active."]
428 #[inline]
429 pub fn _1(self) -> &'a mut W {
430 self.variant(IRCLKENW::_1)
431 }
432 #[doc = r" Sets the field bit"]
433 pub fn set_bit(self) -> &'a mut W {
434 self.bit(true)
435 }
436 #[doc = r" Clears the field bit"]
437 pub fn clear_bit(self) -> &'a mut W {
438 self.bit(false)
439 }
440 #[doc = r" Writes raw bits to the field"]
441 #[inline]
442 pub fn bit(self, value: bool) -> &'a mut W {
443 const MASK: bool = true;
444 const OFFSET: u8 = 1;
445 self.w.bits &= !((MASK as u8) << OFFSET);
446 self.w.bits |= ((value & MASK) as u8) << OFFSET;
447 self.w
448 }
449}
450#[doc = "Values that can be written to the field `IREFS`"]
451pub enum IREFSW {
452 #[doc = "External reference clock is selected."]
453 _0,
454 #[doc = "The slow internal reference clock is selected."]
455 _1,
456}
457impl IREFSW {
458 #[allow(missing_docs)]
459 #[doc(hidden)]
460 #[inline]
461 pub fn _bits(&self) -> bool {
462 match *self {
463 IREFSW::_0 => false,
464 IREFSW::_1 => true,
465 }
466 }
467}
468#[doc = r" Proxy"]
469pub struct _IREFSW<'a> {
470 w: &'a mut W,
471}
472impl<'a> _IREFSW<'a> {
473 #[doc = r" Writes `variant` to the field"]
474 #[inline]
475 pub fn variant(self, variant: IREFSW) -> &'a mut W {
476 {
477 self.bit(variant._bits())
478 }
479 }
480 #[doc = "External reference clock is selected."]
481 #[inline]
482 pub fn _0(self) -> &'a mut W {
483 self.variant(IREFSW::_0)
484 }
485 #[doc = "The slow internal reference clock is selected."]
486 #[inline]
487 pub fn _1(self) -> &'a mut W {
488 self.variant(IREFSW::_1)
489 }
490 #[doc = r" Sets the field bit"]
491 pub fn set_bit(self) -> &'a mut W {
492 self.bit(true)
493 }
494 #[doc = r" Clears the field bit"]
495 pub fn clear_bit(self) -> &'a mut W {
496 self.bit(false)
497 }
498 #[doc = r" Writes raw bits to the field"]
499 #[inline]
500 pub fn bit(self, value: bool) -> &'a mut W {
501 const MASK: bool = true;
502 const OFFSET: u8 = 2;
503 self.w.bits &= !((MASK as u8) << OFFSET);
504 self.w.bits |= ((value & MASK) as u8) << OFFSET;
505 self.w
506 }
507}
508#[doc = "Values that can be written to the field `FRDIV`"]
509pub enum FRDIVW {
510 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32."]
511 _000,
512 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64."]
513 _001,
514 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128."]
515 _010,
516 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256."]
517 _011,
518 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512."]
519 _100,
520 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024."]
521 _101,
522 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 ."]
523 _110,
524 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 ."]
525 _111,
526}
527impl FRDIVW {
528 #[allow(missing_docs)]
529 #[doc(hidden)]
530 #[inline]
531 pub fn _bits(&self) -> u8 {
532 match *self {
533 FRDIVW::_000 => 0,
534 FRDIVW::_001 => 1,
535 FRDIVW::_010 => 2,
536 FRDIVW::_011 => 3,
537 FRDIVW::_100 => 4,
538 FRDIVW::_101 => 5,
539 FRDIVW::_110 => 6,
540 FRDIVW::_111 => 7,
541 }
542 }
543}
544#[doc = r" Proxy"]
545pub struct _FRDIVW<'a> {
546 w: &'a mut W,
547}
548impl<'a> _FRDIVW<'a> {
549 #[doc = r" Writes `variant` to the field"]
550 #[inline]
551 pub fn variant(self, variant: FRDIVW) -> &'a mut W {
552 {
553 self.bits(variant._bits())
554 }
555 }
556 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32."]
557 #[inline]
558 pub fn _000(self) -> &'a mut W {
559 self.variant(FRDIVW::_000)
560 }
561 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64."]
562 #[inline]
563 pub fn _001(self) -> &'a mut W {
564 self.variant(FRDIVW::_001)
565 }
566 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128."]
567 #[inline]
568 pub fn _010(self) -> &'a mut W {
569 self.variant(FRDIVW::_010)
570 }
571 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256."]
572 #[inline]
573 pub fn _011(self) -> &'a mut W {
574 self.variant(FRDIVW::_011)
575 }
576 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512."]
577 #[inline]
578 pub fn _100(self) -> &'a mut W {
579 self.variant(FRDIVW::_100)
580 }
581 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024."]
582 #[inline]
583 pub fn _101(self) -> &'a mut W {
584 self.variant(FRDIVW::_101)
585 }
586 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 ."]
587 #[inline]
588 pub fn _110(self) -> &'a mut W {
589 self.variant(FRDIVW::_110)
590 }
591 #[doc = "If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 ."]
592 #[inline]
593 pub fn _111(self) -> &'a mut W {
594 self.variant(FRDIVW::_111)
595 }
596 #[doc = r" Writes raw bits to the field"]
597 #[inline]
598 pub fn bits(self, value: u8) -> &'a mut W {
599 const MASK: u8 = 7;
600 const OFFSET: u8 = 3;
601 self.w.bits &= !((MASK as u8) << OFFSET);
602 self.w.bits |= ((value & MASK) as u8) << OFFSET;
603 self.w
604 }
605}
606#[doc = "Values that can be written to the field `CLKS`"]
607pub enum CLKSW {
608 #[doc = "Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit)."]
609 _00,
610 #[doc = "Encoding 1 - Internal reference clock is selected."]
611 _01,
612 #[doc = "Encoding 2 - External reference clock is selected."]
613 _10,
614 #[doc = "Encoding 3 - Reserved."]
615 _11,
616}
617impl CLKSW {
618 #[allow(missing_docs)]
619 #[doc(hidden)]
620 #[inline]
621 pub fn _bits(&self) -> u8 {
622 match *self {
623 CLKSW::_00 => 0,
624 CLKSW::_01 => 1,
625 CLKSW::_10 => 2,
626 CLKSW::_11 => 3,
627 }
628 }
629}
630#[doc = r" Proxy"]
631pub struct _CLKSW<'a> {
632 w: &'a mut W,
633}
634impl<'a> _CLKSW<'a> {
635 #[doc = r" Writes `variant` to the field"]
636 #[inline]
637 pub fn variant(self, variant: CLKSW) -> &'a mut W {
638 {
639 self.bits(variant._bits())
640 }
641 }
642 #[doc = "Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit)."]
643 #[inline]
644 pub fn _00(self) -> &'a mut W {
645 self.variant(CLKSW::_00)
646 }
647 #[doc = "Encoding 1 - Internal reference clock is selected."]
648 #[inline]
649 pub fn _01(self) -> &'a mut W {
650 self.variant(CLKSW::_01)
651 }
652 #[doc = "Encoding 2 - External reference clock is selected."]
653 #[inline]
654 pub fn _10(self) -> &'a mut W {
655 self.variant(CLKSW::_10)
656 }
657 #[doc = "Encoding 3 - Reserved."]
658 #[inline]
659 pub fn _11(self) -> &'a mut W {
660 self.variant(CLKSW::_11)
661 }
662 #[doc = r" Writes raw bits to the field"]
663 #[inline]
664 pub fn bits(self, value: u8) -> &'a mut W {
665 const MASK: u8 = 3;
666 const OFFSET: u8 = 6;
667 self.w.bits &= !((MASK as u8) << OFFSET);
668 self.w.bits |= ((value & MASK) as u8) << OFFSET;
669 self.w
670 }
671}
672impl R {
673 #[doc = r" Value of the register as raw bits"]
674 #[inline]
675 pub fn bits(&self) -> u8 {
676 self.bits
677 }
678 #[doc = "Bit 0 - Internal Reference Stop Enable"]
679 #[inline]
680 pub fn irefsten(&self) -> IREFSTENR {
681 IREFSTENR::_from({
682 const MASK: bool = true;
683 const OFFSET: u8 = 0;
684 ((self.bits >> OFFSET) & MASK as u8) != 0
685 })
686 }
687 #[doc = "Bit 1 - Internal Reference Clock Enable"]
688 #[inline]
689 pub fn irclken(&self) -> IRCLKENR {
690 IRCLKENR::_from({
691 const MASK: bool = true;
692 const OFFSET: u8 = 1;
693 ((self.bits >> OFFSET) & MASK as u8) != 0
694 })
695 }
696 #[doc = "Bit 2 - Internal Reference Select"]
697 #[inline]
698 pub fn irefs(&self) -> IREFSR {
699 IREFSR::_from({
700 const MASK: bool = true;
701 const OFFSET: u8 = 2;
702 ((self.bits >> OFFSET) & MASK as u8) != 0
703 })
704 }
705 #[doc = "Bits 3:5 - FLL External Reference Divider"]
706 #[inline]
707 pub fn frdiv(&self) -> FRDIVR {
708 FRDIVR::_from({
709 const MASK: u8 = 7;
710 const OFFSET: u8 = 3;
711 ((self.bits >> OFFSET) & MASK as u8) as u8
712 })
713 }
714 #[doc = "Bits 6:7 - Clock Source Select"]
715 #[inline]
716 pub fn clks(&self) -> CLKSR {
717 CLKSR::_from({
718 const MASK: u8 = 3;
719 const OFFSET: u8 = 6;
720 ((self.bits >> OFFSET) & MASK as u8) as u8
721 })
722 }
723}
724impl W {
725 #[doc = r" Reset value of the register"]
726 #[inline]
727 pub fn reset_value() -> W {
728 W { bits: 4 }
729 }
730 #[doc = r" Writes raw bits to the register"]
731 #[inline]
732 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
733 self.bits = bits;
734 self
735 }
736 #[doc = "Bit 0 - Internal Reference Stop Enable"]
737 #[inline]
738 pub fn irefsten(&mut self) -> _IREFSTENW {
739 _IREFSTENW { w: self }
740 }
741 #[doc = "Bit 1 - Internal Reference Clock Enable"]
742 #[inline]
743 pub fn irclken(&mut self) -> _IRCLKENW {
744 _IRCLKENW { w: self }
745 }
746 #[doc = "Bit 2 - Internal Reference Select"]
747 #[inline]
748 pub fn irefs(&mut self) -> _IREFSW {
749 _IREFSW { w: self }
750 }
751 #[doc = "Bits 3:5 - FLL External Reference Divider"]
752 #[inline]
753 pub fn frdiv(&mut self) -> _FRDIVW {
754 _FRDIVW { w: self }
755 }
756 #[doc = "Bits 6:7 - Clock Source Select"]
757 #[inline]
758 pub fn clks(&mut self) -> _CLKSW {
759 _CLKSW { w: self }
760 }
761}