1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u8,
8}
9impl super::MSC {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `MCGEN`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum MCGENR {
48 #[doc = "Modulator and carrier generator disabled"]
49 _0,
50 #[doc = "Modulator and carrier generator enabled"]
51 _1,
52}
53impl MCGENR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 MCGENR::_0 => false,
69 MCGENR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> MCGENR {
76 match value {
77 false => MCGENR::_0,
78 true => MCGENR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == MCGENR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == MCGENR::_1
90 }
91}
92#[doc = "Possible values of the field `EOCIE`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum EOCIER {
95 #[doc = "CPU interrupt is disabled."]
96 _0,
97 #[doc = "CPU interrupt is enabled."]
98 _1,
99}
100impl EOCIER {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 EOCIER::_0 => false,
116 EOCIER::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> EOCIER {
123 match value {
124 false => EOCIER::_0,
125 true => EOCIER::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == EOCIER::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == EOCIER::_1
137 }
138}
139#[doc = "Possible values of the field `FSK`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum FSKR {
142 #[doc = "The CMT operates in Time or Baseband mode."]
143 _0,
144 #[doc = "The CMT operates in FSK mode."]
145 _1,
146}
147impl FSKR {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 FSKR::_0 => false,
163 FSKR::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> FSKR {
170 match value {
171 false => FSKR::_0,
172 true => FSKR::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == FSKR::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == FSKR::_1
184 }
185}
186#[doc = "Possible values of the field `BASE`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum BASER {
189 #[doc = "Baseband mode is disabled."]
190 _0,
191 #[doc = "Baseband mode is enabled."]
192 _1,
193}
194impl BASER {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 BASER::_0 => false,
210 BASER::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> BASER {
217 match value {
218 false => BASER::_0,
219 true => BASER::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == BASER::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == BASER::_1
231 }
232}
233#[doc = "Possible values of the field `EXSPC`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum EXSPCR {
236 #[doc = "Extended space is disabled."]
237 _0,
238 #[doc = "Extended space is enabled."]
239 _1,
240}
241impl EXSPCR {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 EXSPCR::_0 => false,
257 EXSPCR::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> EXSPCR {
264 match value {
265 false => EXSPCR::_0,
266 true => EXSPCR::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == EXSPCR::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == EXSPCR::_1
278 }
279}
280#[doc = "Possible values of the field `CMTDIV`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum CMTDIVR {
283 #[doc = "IF * 1"]
284 _00,
285 #[doc = "IF * 2"]
286 _01,
287 #[doc = "IF * 4"]
288 _10,
289 #[doc = "IF * 8"]
290 _11,
291}
292impl CMTDIVR {
293 #[doc = r" Value of the field as raw bits"]
294 #[inline]
295 pub fn bits(&self) -> u8 {
296 match *self {
297 CMTDIVR::_00 => 0,
298 CMTDIVR::_01 => 1,
299 CMTDIVR::_10 => 2,
300 CMTDIVR::_11 => 3,
301 }
302 }
303 #[allow(missing_docs)]
304 #[doc(hidden)]
305 #[inline]
306 pub fn _from(value: u8) -> CMTDIVR {
307 match value {
308 0 => CMTDIVR::_00,
309 1 => CMTDIVR::_01,
310 2 => CMTDIVR::_10,
311 3 => CMTDIVR::_11,
312 _ => unreachable!(),
313 }
314 }
315 #[doc = "Checks if the value of the field is `_00`"]
316 #[inline]
317 pub fn is_00(&self) -> bool {
318 *self == CMTDIVR::_00
319 }
320 #[doc = "Checks if the value of the field is `_01`"]
321 #[inline]
322 pub fn is_01(&self) -> bool {
323 *self == CMTDIVR::_01
324 }
325 #[doc = "Checks if the value of the field is `_10`"]
326 #[inline]
327 pub fn is_10(&self) -> bool {
328 *self == CMTDIVR::_10
329 }
330 #[doc = "Checks if the value of the field is `_11`"]
331 #[inline]
332 pub fn is_11(&self) -> bool {
333 *self == CMTDIVR::_11
334 }
335}
336#[doc = "Possible values of the field `EOCF`"]
337#[derive(Clone, Copy, Debug, PartialEq)]
338pub enum EOCFR {
339 #[doc = "End of modulation cycle has not occured since the flag last cleared."]
340 _0,
341 #[doc = "End of modulator cycle has occurred."]
342 _1,
343}
344impl EOCFR {
345 #[doc = r" Returns `true` if the bit is clear (0)"]
346 #[inline]
347 pub fn bit_is_clear(&self) -> bool {
348 !self.bit()
349 }
350 #[doc = r" Returns `true` if the bit is set (1)"]
351 #[inline]
352 pub fn bit_is_set(&self) -> bool {
353 self.bit()
354 }
355 #[doc = r" Value of the field as raw bits"]
356 #[inline]
357 pub fn bit(&self) -> bool {
358 match *self {
359 EOCFR::_0 => false,
360 EOCFR::_1 => true,
361 }
362 }
363 #[allow(missing_docs)]
364 #[doc(hidden)]
365 #[inline]
366 pub fn _from(value: bool) -> EOCFR {
367 match value {
368 false => EOCFR::_0,
369 true => EOCFR::_1,
370 }
371 }
372 #[doc = "Checks if the value of the field is `_0`"]
373 #[inline]
374 pub fn is_0(&self) -> bool {
375 *self == EOCFR::_0
376 }
377 #[doc = "Checks if the value of the field is `_1`"]
378 #[inline]
379 pub fn is_1(&self) -> bool {
380 *self == EOCFR::_1
381 }
382}
383#[doc = "Values that can be written to the field `MCGEN`"]
384pub enum MCGENW {
385 #[doc = "Modulator and carrier generator disabled"]
386 _0,
387 #[doc = "Modulator and carrier generator enabled"]
388 _1,
389}
390impl MCGENW {
391 #[allow(missing_docs)]
392 #[doc(hidden)]
393 #[inline]
394 pub fn _bits(&self) -> bool {
395 match *self {
396 MCGENW::_0 => false,
397 MCGENW::_1 => true,
398 }
399 }
400}
401#[doc = r" Proxy"]
402pub struct _MCGENW<'a> {
403 w: &'a mut W,
404}
405impl<'a> _MCGENW<'a> {
406 #[doc = r" Writes `variant` to the field"]
407 #[inline]
408 pub fn variant(self, variant: MCGENW) -> &'a mut W {
409 {
410 self.bit(variant._bits())
411 }
412 }
413 #[doc = "Modulator and carrier generator disabled"]
414 #[inline]
415 pub fn _0(self) -> &'a mut W {
416 self.variant(MCGENW::_0)
417 }
418 #[doc = "Modulator and carrier generator enabled"]
419 #[inline]
420 pub fn _1(self) -> &'a mut W {
421 self.variant(MCGENW::_1)
422 }
423 #[doc = r" Sets the field bit"]
424 pub fn set_bit(self) -> &'a mut W {
425 self.bit(true)
426 }
427 #[doc = r" Clears the field bit"]
428 pub fn clear_bit(self) -> &'a mut W {
429 self.bit(false)
430 }
431 #[doc = r" Writes raw bits to the field"]
432 #[inline]
433 pub fn bit(self, value: bool) -> &'a mut W {
434 const MASK: bool = true;
435 const OFFSET: u8 = 0;
436 self.w.bits &= !((MASK as u8) << OFFSET);
437 self.w.bits |= ((value & MASK) as u8) << OFFSET;
438 self.w
439 }
440}
441#[doc = "Values that can be written to the field `EOCIE`"]
442pub enum EOCIEW {
443 #[doc = "CPU interrupt is disabled."]
444 _0,
445 #[doc = "CPU interrupt is enabled."]
446 _1,
447}
448impl EOCIEW {
449 #[allow(missing_docs)]
450 #[doc(hidden)]
451 #[inline]
452 pub fn _bits(&self) -> bool {
453 match *self {
454 EOCIEW::_0 => false,
455 EOCIEW::_1 => true,
456 }
457 }
458}
459#[doc = r" Proxy"]
460pub struct _EOCIEW<'a> {
461 w: &'a mut W,
462}
463impl<'a> _EOCIEW<'a> {
464 #[doc = r" Writes `variant` to the field"]
465 #[inline]
466 pub fn variant(self, variant: EOCIEW) -> &'a mut W {
467 {
468 self.bit(variant._bits())
469 }
470 }
471 #[doc = "CPU interrupt is disabled."]
472 #[inline]
473 pub fn _0(self) -> &'a mut W {
474 self.variant(EOCIEW::_0)
475 }
476 #[doc = "CPU interrupt is enabled."]
477 #[inline]
478 pub fn _1(self) -> &'a mut W {
479 self.variant(EOCIEW::_1)
480 }
481 #[doc = r" Sets the field bit"]
482 pub fn set_bit(self) -> &'a mut W {
483 self.bit(true)
484 }
485 #[doc = r" Clears the field bit"]
486 pub fn clear_bit(self) -> &'a mut W {
487 self.bit(false)
488 }
489 #[doc = r" Writes raw bits to the field"]
490 #[inline]
491 pub fn bit(self, value: bool) -> &'a mut W {
492 const MASK: bool = true;
493 const OFFSET: u8 = 1;
494 self.w.bits &= !((MASK as u8) << OFFSET);
495 self.w.bits |= ((value & MASK) as u8) << OFFSET;
496 self.w
497 }
498}
499#[doc = "Values that can be written to the field `FSK`"]
500pub enum FSKW {
501 #[doc = "The CMT operates in Time or Baseband mode."]
502 _0,
503 #[doc = "The CMT operates in FSK mode."]
504 _1,
505}
506impl FSKW {
507 #[allow(missing_docs)]
508 #[doc(hidden)]
509 #[inline]
510 pub fn _bits(&self) -> bool {
511 match *self {
512 FSKW::_0 => false,
513 FSKW::_1 => true,
514 }
515 }
516}
517#[doc = r" Proxy"]
518pub struct _FSKW<'a> {
519 w: &'a mut W,
520}
521impl<'a> _FSKW<'a> {
522 #[doc = r" Writes `variant` to the field"]
523 #[inline]
524 pub fn variant(self, variant: FSKW) -> &'a mut W {
525 {
526 self.bit(variant._bits())
527 }
528 }
529 #[doc = "The CMT operates in Time or Baseband mode."]
530 #[inline]
531 pub fn _0(self) -> &'a mut W {
532 self.variant(FSKW::_0)
533 }
534 #[doc = "The CMT operates in FSK mode."]
535 #[inline]
536 pub fn _1(self) -> &'a mut W {
537 self.variant(FSKW::_1)
538 }
539 #[doc = r" Sets the field bit"]
540 pub fn set_bit(self) -> &'a mut W {
541 self.bit(true)
542 }
543 #[doc = r" Clears the field bit"]
544 pub fn clear_bit(self) -> &'a mut W {
545 self.bit(false)
546 }
547 #[doc = r" Writes raw bits to the field"]
548 #[inline]
549 pub fn bit(self, value: bool) -> &'a mut W {
550 const MASK: bool = true;
551 const OFFSET: u8 = 2;
552 self.w.bits &= !((MASK as u8) << OFFSET);
553 self.w.bits |= ((value & MASK) as u8) << OFFSET;
554 self.w
555 }
556}
557#[doc = "Values that can be written to the field `BASE`"]
558pub enum BASEW {
559 #[doc = "Baseband mode is disabled."]
560 _0,
561 #[doc = "Baseband mode is enabled."]
562 _1,
563}
564impl BASEW {
565 #[allow(missing_docs)]
566 #[doc(hidden)]
567 #[inline]
568 pub fn _bits(&self) -> bool {
569 match *self {
570 BASEW::_0 => false,
571 BASEW::_1 => true,
572 }
573 }
574}
575#[doc = r" Proxy"]
576pub struct _BASEW<'a> {
577 w: &'a mut W,
578}
579impl<'a> _BASEW<'a> {
580 #[doc = r" Writes `variant` to the field"]
581 #[inline]
582 pub fn variant(self, variant: BASEW) -> &'a mut W {
583 {
584 self.bit(variant._bits())
585 }
586 }
587 #[doc = "Baseband mode is disabled."]
588 #[inline]
589 pub fn _0(self) -> &'a mut W {
590 self.variant(BASEW::_0)
591 }
592 #[doc = "Baseband mode is enabled."]
593 #[inline]
594 pub fn _1(self) -> &'a mut W {
595 self.variant(BASEW::_1)
596 }
597 #[doc = r" Sets the field bit"]
598 pub fn set_bit(self) -> &'a mut W {
599 self.bit(true)
600 }
601 #[doc = r" Clears the field bit"]
602 pub fn clear_bit(self) -> &'a mut W {
603 self.bit(false)
604 }
605 #[doc = r" Writes raw bits to the field"]
606 #[inline]
607 pub fn bit(self, value: bool) -> &'a mut W {
608 const MASK: bool = true;
609 const OFFSET: u8 = 3;
610 self.w.bits &= !((MASK as u8) << OFFSET);
611 self.w.bits |= ((value & MASK) as u8) << OFFSET;
612 self.w
613 }
614}
615#[doc = "Values that can be written to the field `EXSPC`"]
616pub enum EXSPCW {
617 #[doc = "Extended space is disabled."]
618 _0,
619 #[doc = "Extended space is enabled."]
620 _1,
621}
622impl EXSPCW {
623 #[allow(missing_docs)]
624 #[doc(hidden)]
625 #[inline]
626 pub fn _bits(&self) -> bool {
627 match *self {
628 EXSPCW::_0 => false,
629 EXSPCW::_1 => true,
630 }
631 }
632}
633#[doc = r" Proxy"]
634pub struct _EXSPCW<'a> {
635 w: &'a mut W,
636}
637impl<'a> _EXSPCW<'a> {
638 #[doc = r" Writes `variant` to the field"]
639 #[inline]
640 pub fn variant(self, variant: EXSPCW) -> &'a mut W {
641 {
642 self.bit(variant._bits())
643 }
644 }
645 #[doc = "Extended space is disabled."]
646 #[inline]
647 pub fn _0(self) -> &'a mut W {
648 self.variant(EXSPCW::_0)
649 }
650 #[doc = "Extended space is enabled."]
651 #[inline]
652 pub fn _1(self) -> &'a mut W {
653 self.variant(EXSPCW::_1)
654 }
655 #[doc = r" Sets the field bit"]
656 pub fn set_bit(self) -> &'a mut W {
657 self.bit(true)
658 }
659 #[doc = r" Clears the field bit"]
660 pub fn clear_bit(self) -> &'a mut W {
661 self.bit(false)
662 }
663 #[doc = r" Writes raw bits to the field"]
664 #[inline]
665 pub fn bit(self, value: bool) -> &'a mut W {
666 const MASK: bool = true;
667 const OFFSET: u8 = 4;
668 self.w.bits &= !((MASK as u8) << OFFSET);
669 self.w.bits |= ((value & MASK) as u8) << OFFSET;
670 self.w
671 }
672}
673#[doc = "Values that can be written to the field `CMTDIV`"]
674pub enum CMTDIVW {
675 #[doc = "IF * 1"]
676 _00,
677 #[doc = "IF * 2"]
678 _01,
679 #[doc = "IF * 4"]
680 _10,
681 #[doc = "IF * 8"]
682 _11,
683}
684impl CMTDIVW {
685 #[allow(missing_docs)]
686 #[doc(hidden)]
687 #[inline]
688 pub fn _bits(&self) -> u8 {
689 match *self {
690 CMTDIVW::_00 => 0,
691 CMTDIVW::_01 => 1,
692 CMTDIVW::_10 => 2,
693 CMTDIVW::_11 => 3,
694 }
695 }
696}
697#[doc = r" Proxy"]
698pub struct _CMTDIVW<'a> {
699 w: &'a mut W,
700}
701impl<'a> _CMTDIVW<'a> {
702 #[doc = r" Writes `variant` to the field"]
703 #[inline]
704 pub fn variant(self, variant: CMTDIVW) -> &'a mut W {
705 {
706 self.bits(variant._bits())
707 }
708 }
709 #[doc = "IF * 1"]
710 #[inline]
711 pub fn _00(self) -> &'a mut W {
712 self.variant(CMTDIVW::_00)
713 }
714 #[doc = "IF * 2"]
715 #[inline]
716 pub fn _01(self) -> &'a mut W {
717 self.variant(CMTDIVW::_01)
718 }
719 #[doc = "IF * 4"]
720 #[inline]
721 pub fn _10(self) -> &'a mut W {
722 self.variant(CMTDIVW::_10)
723 }
724 #[doc = "IF * 8"]
725 #[inline]
726 pub fn _11(self) -> &'a mut W {
727 self.variant(CMTDIVW::_11)
728 }
729 #[doc = r" Writes raw bits to the field"]
730 #[inline]
731 pub fn bits(self, value: u8) -> &'a mut W {
732 const MASK: u8 = 3;
733 const OFFSET: u8 = 5;
734 self.w.bits &= !((MASK as u8) << OFFSET);
735 self.w.bits |= ((value & MASK) as u8) << OFFSET;
736 self.w
737 }
738}
739impl R {
740 #[doc = r" Value of the register as raw bits"]
741 #[inline]
742 pub fn bits(&self) -> u8 {
743 self.bits
744 }
745 #[doc = "Bit 0 - Modulator and Carrier Generator Enable"]
746 #[inline]
747 pub fn mcgen(&self) -> MCGENR {
748 MCGENR::_from({
749 const MASK: bool = true;
750 const OFFSET: u8 = 0;
751 ((self.bits >> OFFSET) & MASK as u8) != 0
752 })
753 }
754 #[doc = "Bit 1 - End of Cycle Interrupt Enable"]
755 #[inline]
756 pub fn eocie(&self) -> EOCIER {
757 EOCIER::_from({
758 const MASK: bool = true;
759 const OFFSET: u8 = 1;
760 ((self.bits >> OFFSET) & MASK as u8) != 0
761 })
762 }
763 #[doc = "Bit 2 - FSK Mode Select"]
764 #[inline]
765 pub fn fsk(&self) -> FSKR {
766 FSKR::_from({
767 const MASK: bool = true;
768 const OFFSET: u8 = 2;
769 ((self.bits >> OFFSET) & MASK as u8) != 0
770 })
771 }
772 #[doc = "Bit 3 - Baseband Enable"]
773 #[inline]
774 pub fn base(&self) -> BASER {
775 BASER::_from({
776 const MASK: bool = true;
777 const OFFSET: u8 = 3;
778 ((self.bits >> OFFSET) & MASK as u8) != 0
779 })
780 }
781 #[doc = "Bit 4 - Extended Space Enable"]
782 #[inline]
783 pub fn exspc(&self) -> EXSPCR {
784 EXSPCR::_from({
785 const MASK: bool = true;
786 const OFFSET: u8 = 4;
787 ((self.bits >> OFFSET) & MASK as u8) != 0
788 })
789 }
790 #[doc = "Bits 5:6 - CMT Clock Divide Prescaler"]
791 #[inline]
792 pub fn cmtdiv(&self) -> CMTDIVR {
793 CMTDIVR::_from({
794 const MASK: u8 = 3;
795 const OFFSET: u8 = 5;
796 ((self.bits >> OFFSET) & MASK as u8) as u8
797 })
798 }
799 #[doc = "Bit 7 - End Of Cycle Status Flag"]
800 #[inline]
801 pub fn eocf(&self) -> EOCFR {
802 EOCFR::_from({
803 const MASK: bool = true;
804 const OFFSET: u8 = 7;
805 ((self.bits >> OFFSET) & MASK as u8) != 0
806 })
807 }
808}
809impl W {
810 #[doc = r" Reset value of the register"]
811 #[inline]
812 pub fn reset_value() -> W {
813 W { bits: 0 }
814 }
815 #[doc = r" Writes raw bits to the register"]
816 #[inline]
817 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
818 self.bits = bits;
819 self
820 }
821 #[doc = "Bit 0 - Modulator and Carrier Generator Enable"]
822 #[inline]
823 pub fn mcgen(&mut self) -> _MCGENW {
824 _MCGENW { w: self }
825 }
826 #[doc = "Bit 1 - End of Cycle Interrupt Enable"]
827 #[inline]
828 pub fn eocie(&mut self) -> _EOCIEW {
829 _EOCIEW { w: self }
830 }
831 #[doc = "Bit 2 - FSK Mode Select"]
832 #[inline]
833 pub fn fsk(&mut self) -> _FSKW {
834 _FSKW { w: self }
835 }
836 #[doc = "Bit 3 - Baseband Enable"]
837 #[inline]
838 pub fn base(&mut self) -> _BASEW {
839 _BASEW { w: self }
840 }
841 #[doc = "Bit 4 - Extended Space Enable"]
842 #[inline]
843 pub fn exspc(&mut self) -> _EXSPCW {
844 _EXSPCW { w: self }
845 }
846 #[doc = "Bits 5:6 - CMT Clock Divide Prescaler"]
847 #[inline]
848 pub fn cmtdiv(&mut self) -> _CMTDIVW {
849 _CMTDIVW { w: self }
850 }
851}