1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::SC2 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `REFSEL`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum REFSELR {
48 #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
49 _00,
50 #[doc = "Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU"]
51 _01,
52 #[doc = r" Reserved"]
53 _Reserved(u8),
54}
55impl REFSELR {
56 #[doc = r" Value of the field as raw bits"]
57 #[inline]
58 pub fn bits(&self) -> u8 {
59 match *self {
60 REFSELR::_00 => 0,
61 REFSELR::_01 => 1,
62 REFSELR::_Reserved(bits) => bits,
63 }
64 }
65 #[allow(missing_docs)]
66 #[doc(hidden)]
67 #[inline]
68 pub fn _from(value: u8) -> REFSELR {
69 match value {
70 0 => REFSELR::_00,
71 1 => REFSELR::_01,
72 i => REFSELR::_Reserved(i),
73 }
74 }
75 #[doc = "Checks if the value of the field is `_00`"]
76 #[inline]
77 pub fn is_00(&self) -> bool {
78 *self == REFSELR::_00
79 }
80 #[doc = "Checks if the value of the field is `_01`"]
81 #[inline]
82 pub fn is_01(&self) -> bool {
83 *self == REFSELR::_01
84 }
85}
86#[doc = "Possible values of the field `DMAEN`"]
87#[derive(Clone, Copy, Debug, PartialEq)]
88pub enum DMAENR {
89 #[doc = "DMA is disabled."]
90 _0,
91 #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n\\[COCO\\] flags is asserted."]
92 _1,
93}
94impl DMAENR {
95 #[doc = r" Returns `true` if the bit is clear (0)"]
96 #[inline]
97 pub fn bit_is_clear(&self) -> bool {
98 !self.bit()
99 }
100 #[doc = r" Returns `true` if the bit is set (1)"]
101 #[inline]
102 pub fn bit_is_set(&self) -> bool {
103 self.bit()
104 }
105 #[doc = r" Value of the field as raw bits"]
106 #[inline]
107 pub fn bit(&self) -> bool {
108 match *self {
109 DMAENR::_0 => false,
110 DMAENR::_1 => true,
111 }
112 }
113 #[allow(missing_docs)]
114 #[doc(hidden)]
115 #[inline]
116 pub fn _from(value: bool) -> DMAENR {
117 match value {
118 false => DMAENR::_0,
119 true => DMAENR::_1,
120 }
121 }
122 #[doc = "Checks if the value of the field is `_0`"]
123 #[inline]
124 pub fn is_0(&self) -> bool {
125 *self == DMAENR::_0
126 }
127 #[doc = "Checks if the value of the field is `_1`"]
128 #[inline]
129 pub fn is_1(&self) -> bool {
130 *self == DMAENR::_1
131 }
132}
133#[doc = "Possible values of the field `ACREN`"]
134#[derive(Clone, Copy, Debug, PartialEq)]
135pub enum ACRENR {
136 #[doc = "Range function disabled. Only CV1 is compared."]
137 _0,
138 #[doc = "Range function enabled. Both CV1 and CV2 are compared."]
139 _1,
140}
141impl ACRENR {
142 #[doc = r" Returns `true` if the bit is clear (0)"]
143 #[inline]
144 pub fn bit_is_clear(&self) -> bool {
145 !self.bit()
146 }
147 #[doc = r" Returns `true` if the bit is set (1)"]
148 #[inline]
149 pub fn bit_is_set(&self) -> bool {
150 self.bit()
151 }
152 #[doc = r" Value of the field as raw bits"]
153 #[inline]
154 pub fn bit(&self) -> bool {
155 match *self {
156 ACRENR::_0 => false,
157 ACRENR::_1 => true,
158 }
159 }
160 #[allow(missing_docs)]
161 #[doc(hidden)]
162 #[inline]
163 pub fn _from(value: bool) -> ACRENR {
164 match value {
165 false => ACRENR::_0,
166 true => ACRENR::_1,
167 }
168 }
169 #[doc = "Checks if the value of the field is `_0`"]
170 #[inline]
171 pub fn is_0(&self) -> bool {
172 *self == ACRENR::_0
173 }
174 #[doc = "Checks if the value of the field is `_1`"]
175 #[inline]
176 pub fn is_1(&self) -> bool {
177 *self == ACRENR::_1
178 }
179}
180#[doc = "Possible values of the field `ACFGT`"]
181#[derive(Clone, Copy, Debug, PartialEq)]
182pub enum ACFGTR {
183 #[doc = "Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2."]
184 _0,
185 #[doc = "Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2."]
186 _1,
187}
188impl ACFGTR {
189 #[doc = r" Returns `true` if the bit is clear (0)"]
190 #[inline]
191 pub fn bit_is_clear(&self) -> bool {
192 !self.bit()
193 }
194 #[doc = r" Returns `true` if the bit is set (1)"]
195 #[inline]
196 pub fn bit_is_set(&self) -> bool {
197 self.bit()
198 }
199 #[doc = r" Value of the field as raw bits"]
200 #[inline]
201 pub fn bit(&self) -> bool {
202 match *self {
203 ACFGTR::_0 => false,
204 ACFGTR::_1 => true,
205 }
206 }
207 #[allow(missing_docs)]
208 #[doc(hidden)]
209 #[inline]
210 pub fn _from(value: bool) -> ACFGTR {
211 match value {
212 false => ACFGTR::_0,
213 true => ACFGTR::_1,
214 }
215 }
216 #[doc = "Checks if the value of the field is `_0`"]
217 #[inline]
218 pub fn is_0(&self) -> bool {
219 *self == ACFGTR::_0
220 }
221 #[doc = "Checks if the value of the field is `_1`"]
222 #[inline]
223 pub fn is_1(&self) -> bool {
224 *self == ACFGTR::_1
225 }
226}
227#[doc = "Possible values of the field `ACFE`"]
228#[derive(Clone, Copy, Debug, PartialEq)]
229pub enum ACFER {
230 #[doc = "Compare function disabled."]
231 _0,
232 #[doc = "Compare function enabled."]
233 _1,
234}
235impl ACFER {
236 #[doc = r" Returns `true` if the bit is clear (0)"]
237 #[inline]
238 pub fn bit_is_clear(&self) -> bool {
239 !self.bit()
240 }
241 #[doc = r" Returns `true` if the bit is set (1)"]
242 #[inline]
243 pub fn bit_is_set(&self) -> bool {
244 self.bit()
245 }
246 #[doc = r" Value of the field as raw bits"]
247 #[inline]
248 pub fn bit(&self) -> bool {
249 match *self {
250 ACFER::_0 => false,
251 ACFER::_1 => true,
252 }
253 }
254 #[allow(missing_docs)]
255 #[doc(hidden)]
256 #[inline]
257 pub fn _from(value: bool) -> ACFER {
258 match value {
259 false => ACFER::_0,
260 true => ACFER::_1,
261 }
262 }
263 #[doc = "Checks if the value of the field is `_0`"]
264 #[inline]
265 pub fn is_0(&self) -> bool {
266 *self == ACFER::_0
267 }
268 #[doc = "Checks if the value of the field is `_1`"]
269 #[inline]
270 pub fn is_1(&self) -> bool {
271 *self == ACFER::_1
272 }
273}
274#[doc = "Possible values of the field `ADTRG`"]
275#[derive(Clone, Copy, Debug, PartialEq)]
276pub enum ADTRGR {
277 #[doc = "Software trigger selected."]
278 _0,
279 #[doc = "Hardware trigger selected."]
280 _1,
281}
282impl ADTRGR {
283 #[doc = r" Returns `true` if the bit is clear (0)"]
284 #[inline]
285 pub fn bit_is_clear(&self) -> bool {
286 !self.bit()
287 }
288 #[doc = r" Returns `true` if the bit is set (1)"]
289 #[inline]
290 pub fn bit_is_set(&self) -> bool {
291 self.bit()
292 }
293 #[doc = r" Value of the field as raw bits"]
294 #[inline]
295 pub fn bit(&self) -> bool {
296 match *self {
297 ADTRGR::_0 => false,
298 ADTRGR::_1 => true,
299 }
300 }
301 #[allow(missing_docs)]
302 #[doc(hidden)]
303 #[inline]
304 pub fn _from(value: bool) -> ADTRGR {
305 match value {
306 false => ADTRGR::_0,
307 true => ADTRGR::_1,
308 }
309 }
310 #[doc = "Checks if the value of the field is `_0`"]
311 #[inline]
312 pub fn is_0(&self) -> bool {
313 *self == ADTRGR::_0
314 }
315 #[doc = "Checks if the value of the field is `_1`"]
316 #[inline]
317 pub fn is_1(&self) -> bool {
318 *self == ADTRGR::_1
319 }
320}
321#[doc = "Possible values of the field `ADACT`"]
322#[derive(Clone, Copy, Debug, PartialEq)]
323pub enum ADACTR {
324 #[doc = "Conversion not in progress."]
325 _0,
326 #[doc = "Conversion in progress."]
327 _1,
328}
329impl ADACTR {
330 #[doc = r" Returns `true` if the bit is clear (0)"]
331 #[inline]
332 pub fn bit_is_clear(&self) -> bool {
333 !self.bit()
334 }
335 #[doc = r" Returns `true` if the bit is set (1)"]
336 #[inline]
337 pub fn bit_is_set(&self) -> bool {
338 self.bit()
339 }
340 #[doc = r" Value of the field as raw bits"]
341 #[inline]
342 pub fn bit(&self) -> bool {
343 match *self {
344 ADACTR::_0 => false,
345 ADACTR::_1 => true,
346 }
347 }
348 #[allow(missing_docs)]
349 #[doc(hidden)]
350 #[inline]
351 pub fn _from(value: bool) -> ADACTR {
352 match value {
353 false => ADACTR::_0,
354 true => ADACTR::_1,
355 }
356 }
357 #[doc = "Checks if the value of the field is `_0`"]
358 #[inline]
359 pub fn is_0(&self) -> bool {
360 *self == ADACTR::_0
361 }
362 #[doc = "Checks if the value of the field is `_1`"]
363 #[inline]
364 pub fn is_1(&self) -> bool {
365 *self == ADACTR::_1
366 }
367}
368#[doc = "Values that can be written to the field `REFSEL`"]
369pub enum REFSELW {
370 #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
371 _00,
372 #[doc = "Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU"]
373 _01,
374}
375impl REFSELW {
376 #[allow(missing_docs)]
377 #[doc(hidden)]
378 #[inline]
379 pub fn _bits(&self) -> u8 {
380 match *self {
381 REFSELW::_00 => 0,
382 REFSELW::_01 => 1,
383 }
384 }
385}
386#[doc = r" Proxy"]
387pub struct _REFSELW<'a> {
388 w: &'a mut W,
389}
390impl<'a> _REFSELW<'a> {
391 #[doc = r" Writes `variant` to the field"]
392 #[inline]
393 pub fn variant(self, variant: REFSELW) -> &'a mut W {
394 unsafe { self.bits(variant._bits()) }
395 }
396 #[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
397 #[inline]
398 pub fn _00(self) -> &'a mut W {
399 self.variant(REFSELW::_00)
400 }
401 #[doc = "Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU"]
402 #[inline]
403 pub fn _01(self) -> &'a mut W {
404 self.variant(REFSELW::_01)
405 }
406 #[doc = r" Writes raw bits to the field"]
407 #[inline]
408 pub unsafe fn bits(self, value: u8) -> &'a mut W {
409 const MASK: u8 = 3;
410 const OFFSET: u8 = 0;
411 self.w.bits &= !((MASK as u32) << OFFSET);
412 self.w.bits |= ((value & MASK) as u32) << OFFSET;
413 self.w
414 }
415}
416#[doc = "Values that can be written to the field `DMAEN`"]
417pub enum DMAENW {
418 #[doc = "DMA is disabled."]
419 _0,
420 #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n\\[COCO\\] flags is asserted."]
421 _1,
422}
423impl DMAENW {
424 #[allow(missing_docs)]
425 #[doc(hidden)]
426 #[inline]
427 pub fn _bits(&self) -> bool {
428 match *self {
429 DMAENW::_0 => false,
430 DMAENW::_1 => true,
431 }
432 }
433}
434#[doc = r" Proxy"]
435pub struct _DMAENW<'a> {
436 w: &'a mut W,
437}
438impl<'a> _DMAENW<'a> {
439 #[doc = r" Writes `variant` to the field"]
440 #[inline]
441 pub fn variant(self, variant: DMAENW) -> &'a mut W {
442 {
443 self.bit(variant._bits())
444 }
445 }
446 #[doc = "DMA is disabled."]
447 #[inline]
448 pub fn _0(self) -> &'a mut W {
449 self.variant(DMAENW::_0)
450 }
451 #[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n\\[COCO\\] flags is asserted."]
452 #[inline]
453 pub fn _1(self) -> &'a mut W {
454 self.variant(DMAENW::_1)
455 }
456 #[doc = r" Sets the field bit"]
457 pub fn set_bit(self) -> &'a mut W {
458 self.bit(true)
459 }
460 #[doc = r" Clears the field bit"]
461 pub fn clear_bit(self) -> &'a mut W {
462 self.bit(false)
463 }
464 #[doc = r" Writes raw bits to the field"]
465 #[inline]
466 pub fn bit(self, value: bool) -> &'a mut W {
467 const MASK: bool = true;
468 const OFFSET: u8 = 2;
469 self.w.bits &= !((MASK as u32) << OFFSET);
470 self.w.bits |= ((value & MASK) as u32) << OFFSET;
471 self.w
472 }
473}
474#[doc = "Values that can be written to the field `ACREN`"]
475pub enum ACRENW {
476 #[doc = "Range function disabled. Only CV1 is compared."]
477 _0,
478 #[doc = "Range function enabled. Both CV1 and CV2 are compared."]
479 _1,
480}
481impl ACRENW {
482 #[allow(missing_docs)]
483 #[doc(hidden)]
484 #[inline]
485 pub fn _bits(&self) -> bool {
486 match *self {
487 ACRENW::_0 => false,
488 ACRENW::_1 => true,
489 }
490 }
491}
492#[doc = r" Proxy"]
493pub struct _ACRENW<'a> {
494 w: &'a mut W,
495}
496impl<'a> _ACRENW<'a> {
497 #[doc = r" Writes `variant` to the field"]
498 #[inline]
499 pub fn variant(self, variant: ACRENW) -> &'a mut W {
500 {
501 self.bit(variant._bits())
502 }
503 }
504 #[doc = "Range function disabled. Only CV1 is compared."]
505 #[inline]
506 pub fn _0(self) -> &'a mut W {
507 self.variant(ACRENW::_0)
508 }
509 #[doc = "Range function enabled. Both CV1 and CV2 are compared."]
510 #[inline]
511 pub fn _1(self) -> &'a mut W {
512 self.variant(ACRENW::_1)
513 }
514 #[doc = r" Sets the field bit"]
515 pub fn set_bit(self) -> &'a mut W {
516 self.bit(true)
517 }
518 #[doc = r" Clears the field bit"]
519 pub fn clear_bit(self) -> &'a mut W {
520 self.bit(false)
521 }
522 #[doc = r" Writes raw bits to the field"]
523 #[inline]
524 pub fn bit(self, value: bool) -> &'a mut W {
525 const MASK: bool = true;
526 const OFFSET: u8 = 3;
527 self.w.bits &= !((MASK as u32) << OFFSET);
528 self.w.bits |= ((value & MASK) as u32) << OFFSET;
529 self.w
530 }
531}
532#[doc = "Values that can be written to the field `ACFGT`"]
533pub enum ACFGTW {
534 #[doc = "Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2."]
535 _0,
536 #[doc = "Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2."]
537 _1,
538}
539impl ACFGTW {
540 #[allow(missing_docs)]
541 #[doc(hidden)]
542 #[inline]
543 pub fn _bits(&self) -> bool {
544 match *self {
545 ACFGTW::_0 => false,
546 ACFGTW::_1 => true,
547 }
548 }
549}
550#[doc = r" Proxy"]
551pub struct _ACFGTW<'a> {
552 w: &'a mut W,
553}
554impl<'a> _ACFGTW<'a> {
555 #[doc = r" Writes `variant` to the field"]
556 #[inline]
557 pub fn variant(self, variant: ACFGTW) -> &'a mut W {
558 {
559 self.bit(variant._bits())
560 }
561 }
562 #[doc = "Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2."]
563 #[inline]
564 pub fn _0(self) -> &'a mut W {
565 self.variant(ACFGTW::_0)
566 }
567 #[doc = "Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2."]
568 #[inline]
569 pub fn _1(self) -> &'a mut W {
570 self.variant(ACFGTW::_1)
571 }
572 #[doc = r" Sets the field bit"]
573 pub fn set_bit(self) -> &'a mut W {
574 self.bit(true)
575 }
576 #[doc = r" Clears the field bit"]
577 pub fn clear_bit(self) -> &'a mut W {
578 self.bit(false)
579 }
580 #[doc = r" Writes raw bits to the field"]
581 #[inline]
582 pub fn bit(self, value: bool) -> &'a mut W {
583 const MASK: bool = true;
584 const OFFSET: u8 = 4;
585 self.w.bits &= !((MASK as u32) << OFFSET);
586 self.w.bits |= ((value & MASK) as u32) << OFFSET;
587 self.w
588 }
589}
590#[doc = "Values that can be written to the field `ACFE`"]
591pub enum ACFEW {
592 #[doc = "Compare function disabled."]
593 _0,
594 #[doc = "Compare function enabled."]
595 _1,
596}
597impl ACFEW {
598 #[allow(missing_docs)]
599 #[doc(hidden)]
600 #[inline]
601 pub fn _bits(&self) -> bool {
602 match *self {
603 ACFEW::_0 => false,
604 ACFEW::_1 => true,
605 }
606 }
607}
608#[doc = r" Proxy"]
609pub struct _ACFEW<'a> {
610 w: &'a mut W,
611}
612impl<'a> _ACFEW<'a> {
613 #[doc = r" Writes `variant` to the field"]
614 #[inline]
615 pub fn variant(self, variant: ACFEW) -> &'a mut W {
616 {
617 self.bit(variant._bits())
618 }
619 }
620 #[doc = "Compare function disabled."]
621 #[inline]
622 pub fn _0(self) -> &'a mut W {
623 self.variant(ACFEW::_0)
624 }
625 #[doc = "Compare function enabled."]
626 #[inline]
627 pub fn _1(self) -> &'a mut W {
628 self.variant(ACFEW::_1)
629 }
630 #[doc = r" Sets the field bit"]
631 pub fn set_bit(self) -> &'a mut W {
632 self.bit(true)
633 }
634 #[doc = r" Clears the field bit"]
635 pub fn clear_bit(self) -> &'a mut W {
636 self.bit(false)
637 }
638 #[doc = r" Writes raw bits to the field"]
639 #[inline]
640 pub fn bit(self, value: bool) -> &'a mut W {
641 const MASK: bool = true;
642 const OFFSET: u8 = 5;
643 self.w.bits &= !((MASK as u32) << OFFSET);
644 self.w.bits |= ((value & MASK) as u32) << OFFSET;
645 self.w
646 }
647}
648#[doc = "Values that can be written to the field `ADTRG`"]
649pub enum ADTRGW {
650 #[doc = "Software trigger selected."]
651 _0,
652 #[doc = "Hardware trigger selected."]
653 _1,
654}
655impl ADTRGW {
656 #[allow(missing_docs)]
657 #[doc(hidden)]
658 #[inline]
659 pub fn _bits(&self) -> bool {
660 match *self {
661 ADTRGW::_0 => false,
662 ADTRGW::_1 => true,
663 }
664 }
665}
666#[doc = r" Proxy"]
667pub struct _ADTRGW<'a> {
668 w: &'a mut W,
669}
670impl<'a> _ADTRGW<'a> {
671 #[doc = r" Writes `variant` to the field"]
672 #[inline]
673 pub fn variant(self, variant: ADTRGW) -> &'a mut W {
674 {
675 self.bit(variant._bits())
676 }
677 }
678 #[doc = "Software trigger selected."]
679 #[inline]
680 pub fn _0(self) -> &'a mut W {
681 self.variant(ADTRGW::_0)
682 }
683 #[doc = "Hardware trigger selected."]
684 #[inline]
685 pub fn _1(self) -> &'a mut W {
686 self.variant(ADTRGW::_1)
687 }
688 #[doc = r" Sets the field bit"]
689 pub fn set_bit(self) -> &'a mut W {
690 self.bit(true)
691 }
692 #[doc = r" Clears the field bit"]
693 pub fn clear_bit(self) -> &'a mut W {
694 self.bit(false)
695 }
696 #[doc = r" Writes raw bits to the field"]
697 #[inline]
698 pub fn bit(self, value: bool) -> &'a mut W {
699 const MASK: bool = true;
700 const OFFSET: u8 = 6;
701 self.w.bits &= !((MASK as u32) << OFFSET);
702 self.w.bits |= ((value & MASK) as u32) << OFFSET;
703 self.w
704 }
705}
706impl R {
707 #[doc = r" Value of the register as raw bits"]
708 #[inline]
709 pub fn bits(&self) -> u32 {
710 self.bits
711 }
712 #[doc = "Bits 0:1 - Voltage Reference Selection"]
713 #[inline]
714 pub fn refsel(&self) -> REFSELR {
715 REFSELR::_from({
716 const MASK: u8 = 3;
717 const OFFSET: u8 = 0;
718 ((self.bits >> OFFSET) & MASK as u32) as u8
719 })
720 }
721 #[doc = "Bit 2 - DMA Enable"]
722 #[inline]
723 pub fn dmaen(&self) -> DMAENR {
724 DMAENR::_from({
725 const MASK: bool = true;
726 const OFFSET: u8 = 2;
727 ((self.bits >> OFFSET) & MASK as u32) != 0
728 })
729 }
730 #[doc = "Bit 3 - Compare Function Range Enable"]
731 #[inline]
732 pub fn acren(&self) -> ACRENR {
733 ACRENR::_from({
734 const MASK: bool = true;
735 const OFFSET: u8 = 3;
736 ((self.bits >> OFFSET) & MASK as u32) != 0
737 })
738 }
739 #[doc = "Bit 4 - Compare Function Greater Than Enable"]
740 #[inline]
741 pub fn acfgt(&self) -> ACFGTR {
742 ACFGTR::_from({
743 const MASK: bool = true;
744 const OFFSET: u8 = 4;
745 ((self.bits >> OFFSET) & MASK as u32) != 0
746 })
747 }
748 #[doc = "Bit 5 - Compare Function Enable"]
749 #[inline]
750 pub fn acfe(&self) -> ACFER {
751 ACFER::_from({
752 const MASK: bool = true;
753 const OFFSET: u8 = 5;
754 ((self.bits >> OFFSET) & MASK as u32) != 0
755 })
756 }
757 #[doc = "Bit 6 - Conversion Trigger Select"]
758 #[inline]
759 pub fn adtrg(&self) -> ADTRGR {
760 ADTRGR::_from({
761 const MASK: bool = true;
762 const OFFSET: u8 = 6;
763 ((self.bits >> OFFSET) & MASK as u32) != 0
764 })
765 }
766 #[doc = "Bit 7 - Conversion Active"]
767 #[inline]
768 pub fn adact(&self) -> ADACTR {
769 ADACTR::_from({
770 const MASK: bool = true;
771 const OFFSET: u8 = 7;
772 ((self.bits >> OFFSET) & MASK as u32) != 0
773 })
774 }
775}
776impl W {
777 #[doc = r" Reset value of the register"]
778 #[inline]
779 pub fn reset_value() -> W {
780 W { bits: 0 }
781 }
782 #[doc = r" Writes raw bits to the register"]
783 #[inline]
784 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
785 self.bits = bits;
786 self
787 }
788 #[doc = "Bits 0:1 - Voltage Reference Selection"]
789 #[inline]
790 pub fn refsel(&mut self) -> _REFSELW {
791 _REFSELW { w: self }
792 }
793 #[doc = "Bit 2 - DMA Enable"]
794 #[inline]
795 pub fn dmaen(&mut self) -> _DMAENW {
796 _DMAENW { w: self }
797 }
798 #[doc = "Bit 3 - Compare Function Range Enable"]
799 #[inline]
800 pub fn acren(&mut self) -> _ACRENW {
801 _ACRENW { w: self }
802 }
803 #[doc = "Bit 4 - Compare Function Greater Than Enable"]
804 #[inline]
805 pub fn acfgt(&mut self) -> _ACFGTW {
806 _ACFGTW { w: self }
807 }
808 #[doc = "Bit 5 - Compare Function Enable"]
809 #[inline]
810 pub fn acfe(&mut self) -> _ACFEW {
811 _ACFEW { w: self }
812 }
813 #[doc = "Bit 6 - Conversion Trigger Select"]
814 #[inline]
815 pub fn adtrg(&mut self) -> _ADTRGW {
816 _ADTRGW { w: self }
817 }
818}