1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::PCR22 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `PS`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum PSR {
48 #[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
49 _0,
50 #[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
51 _1,
52}
53impl PSR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 PSR::_0 => false,
69 PSR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> PSR {
76 match value {
77 false => PSR::_0,
78 true => PSR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == PSR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == PSR::_1
90 }
91}
92#[doc = "Possible values of the field `PE`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum PER {
95 #[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
96 _0,
97 #[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
98 _1,
99}
100impl PER {
101 #[doc = r" Returns `true` if the bit is clear (0)"]
102 #[inline]
103 pub fn bit_is_clear(&self) -> bool {
104 !self.bit()
105 }
106 #[doc = r" Returns `true` if the bit is set (1)"]
107 #[inline]
108 pub fn bit_is_set(&self) -> bool {
109 self.bit()
110 }
111 #[doc = r" Value of the field as raw bits"]
112 #[inline]
113 pub fn bit(&self) -> bool {
114 match *self {
115 PER::_0 => false,
116 PER::_1 => true,
117 }
118 }
119 #[allow(missing_docs)]
120 #[doc(hidden)]
121 #[inline]
122 pub fn _from(value: bool) -> PER {
123 match value {
124 false => PER::_0,
125 true => PER::_1,
126 }
127 }
128 #[doc = "Checks if the value of the field is `_0`"]
129 #[inline]
130 pub fn is_0(&self) -> bool {
131 *self == PER::_0
132 }
133 #[doc = "Checks if the value of the field is `_1`"]
134 #[inline]
135 pub fn is_1(&self) -> bool {
136 *self == PER::_1
137 }
138}
139#[doc = "Possible values of the field `SRE`"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum SRER {
142 #[doc = "Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
143 _0,
144 #[doc = "Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output."]
145 _1,
146}
147impl SRER {
148 #[doc = r" Returns `true` if the bit is clear (0)"]
149 #[inline]
150 pub fn bit_is_clear(&self) -> bool {
151 !self.bit()
152 }
153 #[doc = r" Returns `true` if the bit is set (1)"]
154 #[inline]
155 pub fn bit_is_set(&self) -> bool {
156 self.bit()
157 }
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bit(&self) -> bool {
161 match *self {
162 SRER::_0 => false,
163 SRER::_1 => true,
164 }
165 }
166 #[allow(missing_docs)]
167 #[doc(hidden)]
168 #[inline]
169 pub fn _from(value: bool) -> SRER {
170 match value {
171 false => SRER::_0,
172 true => SRER::_1,
173 }
174 }
175 #[doc = "Checks if the value of the field is `_0`"]
176 #[inline]
177 pub fn is_0(&self) -> bool {
178 *self == SRER::_0
179 }
180 #[doc = "Checks if the value of the field is `_1`"]
181 #[inline]
182 pub fn is_1(&self) -> bool {
183 *self == SRER::_1
184 }
185}
186#[doc = "Possible values of the field `PFE`"]
187#[derive(Clone, Copy, Debug, PartialEq)]
188pub enum PFER {
189 #[doc = "Passive input filter is disabled on the corresponding pin."]
190 _0,
191 #[doc = "Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics."]
192 _1,
193}
194impl PFER {
195 #[doc = r" Returns `true` if the bit is clear (0)"]
196 #[inline]
197 pub fn bit_is_clear(&self) -> bool {
198 !self.bit()
199 }
200 #[doc = r" Returns `true` if the bit is set (1)"]
201 #[inline]
202 pub fn bit_is_set(&self) -> bool {
203 self.bit()
204 }
205 #[doc = r" Value of the field as raw bits"]
206 #[inline]
207 pub fn bit(&self) -> bool {
208 match *self {
209 PFER::_0 => false,
210 PFER::_1 => true,
211 }
212 }
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _from(value: bool) -> PFER {
217 match value {
218 false => PFER::_0,
219 true => PFER::_1,
220 }
221 }
222 #[doc = "Checks if the value of the field is `_0`"]
223 #[inline]
224 pub fn is_0(&self) -> bool {
225 *self == PFER::_0
226 }
227 #[doc = "Checks if the value of the field is `_1`"]
228 #[inline]
229 pub fn is_1(&self) -> bool {
230 *self == PFER::_1
231 }
232}
233#[doc = "Possible values of the field `ODE`"]
234#[derive(Clone, Copy, Debug, PartialEq)]
235pub enum ODER {
236 #[doc = "Open drain output is disabled on the corresponding pin."]
237 _0,
238 #[doc = "Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output."]
239 _1,
240}
241impl ODER {
242 #[doc = r" Returns `true` if the bit is clear (0)"]
243 #[inline]
244 pub fn bit_is_clear(&self) -> bool {
245 !self.bit()
246 }
247 #[doc = r" Returns `true` if the bit is set (1)"]
248 #[inline]
249 pub fn bit_is_set(&self) -> bool {
250 self.bit()
251 }
252 #[doc = r" Value of the field as raw bits"]
253 #[inline]
254 pub fn bit(&self) -> bool {
255 match *self {
256 ODER::_0 => false,
257 ODER::_1 => true,
258 }
259 }
260 #[allow(missing_docs)]
261 #[doc(hidden)]
262 #[inline]
263 pub fn _from(value: bool) -> ODER {
264 match value {
265 false => ODER::_0,
266 true => ODER::_1,
267 }
268 }
269 #[doc = "Checks if the value of the field is `_0`"]
270 #[inline]
271 pub fn is_0(&self) -> bool {
272 *self == ODER::_0
273 }
274 #[doc = "Checks if the value of the field is `_1`"]
275 #[inline]
276 pub fn is_1(&self) -> bool {
277 *self == ODER::_1
278 }
279}
280#[doc = "Possible values of the field `DSE`"]
281#[derive(Clone, Copy, Debug, PartialEq)]
282pub enum DSER {
283 #[doc = "Low drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
284 _0,
285 #[doc = "High drive strength is configured on the corresponding pin, if pin is configured as a digital output."]
286 _1,
287}
288impl DSER {
289 #[doc = r" Returns `true` if the bit is clear (0)"]
290 #[inline]
291 pub fn bit_is_clear(&self) -> bool {
292 !self.bit()
293 }
294 #[doc = r" Returns `true` if the bit is set (1)"]
295 #[inline]
296 pub fn bit_is_set(&self) -> bool {
297 self.bit()
298 }
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bit(&self) -> bool {
302 match *self {
303 DSER::_0 => false,
304 DSER::_1 => true,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: bool) -> DSER {
311 match value {
312 false => DSER::_0,
313 true => DSER::_1,
314 }
315 }
316 #[doc = "Checks if the value of the field is `_0`"]
317 #[inline]
318 pub fn is_0(&self) -> bool {
319 *self == DSER::_0
320 }
321 #[doc = "Checks if the value of the field is `_1`"]
322 #[inline]
323 pub fn is_1(&self) -> bool {
324 *self == DSER::_1
325 }
326}
327#[doc = "Possible values of the field `MUX`"]
328#[derive(Clone, Copy, Debug, PartialEq)]
329pub enum MUXR {
330 #[doc = "Pin disabled (analog)."]
331 _000,
332 #[doc = "Alternative 1 (GPIO)."]
333 _001,
334 #[doc = "Alternative 2 (chip-specific)."]
335 _010,
336 #[doc = "Alternative 3 (chip-specific)."]
337 _011,
338 #[doc = "Alternative 4 (chip-specific)."]
339 _100,
340 #[doc = "Alternative 5 (chip-specific)."]
341 _101,
342 #[doc = "Alternative 6 (chip-specific)."]
343 _110,
344 #[doc = "Alternative 7 (chip-specific)."]
345 _111,
346}
347impl MUXR {
348 #[doc = r" Value of the field as raw bits"]
349 #[inline]
350 pub fn bits(&self) -> u8 {
351 match *self {
352 MUXR::_000 => 0,
353 MUXR::_001 => 1,
354 MUXR::_010 => 2,
355 MUXR::_011 => 3,
356 MUXR::_100 => 4,
357 MUXR::_101 => 5,
358 MUXR::_110 => 6,
359 MUXR::_111 => 7,
360 }
361 }
362 #[allow(missing_docs)]
363 #[doc(hidden)]
364 #[inline]
365 pub fn _from(value: u8) -> MUXR {
366 match value {
367 0 => MUXR::_000,
368 1 => MUXR::_001,
369 2 => MUXR::_010,
370 3 => MUXR::_011,
371 4 => MUXR::_100,
372 5 => MUXR::_101,
373 6 => MUXR::_110,
374 7 => MUXR::_111,
375 _ => unreachable!(),
376 }
377 }
378 #[doc = "Checks if the value of the field is `_000`"]
379 #[inline]
380 pub fn is_000(&self) -> bool {
381 *self == MUXR::_000
382 }
383 #[doc = "Checks if the value of the field is `_001`"]
384 #[inline]
385 pub fn is_001(&self) -> bool {
386 *self == MUXR::_001
387 }
388 #[doc = "Checks if the value of the field is `_010`"]
389 #[inline]
390 pub fn is_010(&self) -> bool {
391 *self == MUXR::_010
392 }
393 #[doc = "Checks if the value of the field is `_011`"]
394 #[inline]
395 pub fn is_011(&self) -> bool {
396 *self == MUXR::_011
397 }
398 #[doc = "Checks if the value of the field is `_100`"]
399 #[inline]
400 pub fn is_100(&self) -> bool {
401 *self == MUXR::_100
402 }
403 #[doc = "Checks if the value of the field is `_101`"]
404 #[inline]
405 pub fn is_101(&self) -> bool {
406 *self == MUXR::_101
407 }
408 #[doc = "Checks if the value of the field is `_110`"]
409 #[inline]
410 pub fn is_110(&self) -> bool {
411 *self == MUXR::_110
412 }
413 #[doc = "Checks if the value of the field is `_111`"]
414 #[inline]
415 pub fn is_111(&self) -> bool {
416 *self == MUXR::_111
417 }
418}
419#[doc = "Possible values of the field `LK`"]
420#[derive(Clone, Copy, Debug, PartialEq)]
421pub enum LKR {
422 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
423 _0,
424 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
425 _1,
426}
427impl LKR {
428 #[doc = r" Returns `true` if the bit is clear (0)"]
429 #[inline]
430 pub fn bit_is_clear(&self) -> bool {
431 !self.bit()
432 }
433 #[doc = r" Returns `true` if the bit is set (1)"]
434 #[inline]
435 pub fn bit_is_set(&self) -> bool {
436 self.bit()
437 }
438 #[doc = r" Value of the field as raw bits"]
439 #[inline]
440 pub fn bit(&self) -> bool {
441 match *self {
442 LKR::_0 => false,
443 LKR::_1 => true,
444 }
445 }
446 #[allow(missing_docs)]
447 #[doc(hidden)]
448 #[inline]
449 pub fn _from(value: bool) -> LKR {
450 match value {
451 false => LKR::_0,
452 true => LKR::_1,
453 }
454 }
455 #[doc = "Checks if the value of the field is `_0`"]
456 #[inline]
457 pub fn is_0(&self) -> bool {
458 *self == LKR::_0
459 }
460 #[doc = "Checks if the value of the field is `_1`"]
461 #[inline]
462 pub fn is_1(&self) -> bool {
463 *self == LKR::_1
464 }
465}
466#[doc = "Possible values of the field `IRQC`"]
467#[derive(Clone, Copy, Debug, PartialEq)]
468pub enum IRQCR {
469 #[doc = "Interrupt/DMA request disabled."]
470 _0000,
471 #[doc = "DMA request on rising edge."]
472 _0001,
473 #[doc = "DMA request on falling edge."]
474 _0010,
475 #[doc = "DMA request on either edge."]
476 _0011,
477 #[doc = "Interrupt when logic 0."]
478 _1000,
479 #[doc = "Interrupt on rising-edge."]
480 _1001,
481 #[doc = "Interrupt on falling-edge."]
482 _1010,
483 #[doc = "Interrupt on either edge."]
484 _1011,
485 #[doc = "Interrupt when logic 1."]
486 _1100,
487 #[doc = r" Reserved"]
488 _Reserved(u8),
489}
490impl IRQCR {
491 #[doc = r" Value of the field as raw bits"]
492 #[inline]
493 pub fn bits(&self) -> u8 {
494 match *self {
495 IRQCR::_0000 => 0,
496 IRQCR::_0001 => 1,
497 IRQCR::_0010 => 2,
498 IRQCR::_0011 => 3,
499 IRQCR::_1000 => 8,
500 IRQCR::_1001 => 9,
501 IRQCR::_1010 => 10,
502 IRQCR::_1011 => 11,
503 IRQCR::_1100 => 12,
504 IRQCR::_Reserved(bits) => bits,
505 }
506 }
507 #[allow(missing_docs)]
508 #[doc(hidden)]
509 #[inline]
510 pub fn _from(value: u8) -> IRQCR {
511 match value {
512 0 => IRQCR::_0000,
513 1 => IRQCR::_0001,
514 2 => IRQCR::_0010,
515 3 => IRQCR::_0011,
516 8 => IRQCR::_1000,
517 9 => IRQCR::_1001,
518 10 => IRQCR::_1010,
519 11 => IRQCR::_1011,
520 12 => IRQCR::_1100,
521 i => IRQCR::_Reserved(i),
522 }
523 }
524 #[doc = "Checks if the value of the field is `_0000`"]
525 #[inline]
526 pub fn is_0000(&self) -> bool {
527 *self == IRQCR::_0000
528 }
529 #[doc = "Checks if the value of the field is `_0001`"]
530 #[inline]
531 pub fn is_0001(&self) -> bool {
532 *self == IRQCR::_0001
533 }
534 #[doc = "Checks if the value of the field is `_0010`"]
535 #[inline]
536 pub fn is_0010(&self) -> bool {
537 *self == IRQCR::_0010
538 }
539 #[doc = "Checks if the value of the field is `_0011`"]
540 #[inline]
541 pub fn is_0011(&self) -> bool {
542 *self == IRQCR::_0011
543 }
544 #[doc = "Checks if the value of the field is `_1000`"]
545 #[inline]
546 pub fn is_1000(&self) -> bool {
547 *self == IRQCR::_1000
548 }
549 #[doc = "Checks if the value of the field is `_1001`"]
550 #[inline]
551 pub fn is_1001(&self) -> bool {
552 *self == IRQCR::_1001
553 }
554 #[doc = "Checks if the value of the field is `_1010`"]
555 #[inline]
556 pub fn is_1010(&self) -> bool {
557 *self == IRQCR::_1010
558 }
559 #[doc = "Checks if the value of the field is `_1011`"]
560 #[inline]
561 pub fn is_1011(&self) -> bool {
562 *self == IRQCR::_1011
563 }
564 #[doc = "Checks if the value of the field is `_1100`"]
565 #[inline]
566 pub fn is_1100(&self) -> bool {
567 *self == IRQCR::_1100
568 }
569}
570#[doc = "Possible values of the field `ISF`"]
571#[derive(Clone, Copy, Debug, PartialEq)]
572pub enum ISFR {
573 #[doc = "Configured interrupt is not detected."]
574 _0,
575 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
576 _1,
577}
578impl ISFR {
579 #[doc = r" Returns `true` if the bit is clear (0)"]
580 #[inline]
581 pub fn bit_is_clear(&self) -> bool {
582 !self.bit()
583 }
584 #[doc = r" Returns `true` if the bit is set (1)"]
585 #[inline]
586 pub fn bit_is_set(&self) -> bool {
587 self.bit()
588 }
589 #[doc = r" Value of the field as raw bits"]
590 #[inline]
591 pub fn bit(&self) -> bool {
592 match *self {
593 ISFR::_0 => false,
594 ISFR::_1 => true,
595 }
596 }
597 #[allow(missing_docs)]
598 #[doc(hidden)]
599 #[inline]
600 pub fn _from(value: bool) -> ISFR {
601 match value {
602 false => ISFR::_0,
603 true => ISFR::_1,
604 }
605 }
606 #[doc = "Checks if the value of the field is `_0`"]
607 #[inline]
608 pub fn is_0(&self) -> bool {
609 *self == ISFR::_0
610 }
611 #[doc = "Checks if the value of the field is `_1`"]
612 #[inline]
613 pub fn is_1(&self) -> bool {
614 *self == ISFR::_1
615 }
616}
617#[doc = "Values that can be written to the field `MUX`"]
618pub enum MUXW {
619 #[doc = "Pin disabled (analog)."]
620 _000,
621 #[doc = "Alternative 1 (GPIO)."]
622 _001,
623 #[doc = "Alternative 2 (chip-specific)."]
624 _010,
625 #[doc = "Alternative 3 (chip-specific)."]
626 _011,
627 #[doc = "Alternative 4 (chip-specific)."]
628 _100,
629 #[doc = "Alternative 5 (chip-specific)."]
630 _101,
631 #[doc = "Alternative 6 (chip-specific)."]
632 _110,
633 #[doc = "Alternative 7 (chip-specific)."]
634 _111,
635}
636impl MUXW {
637 #[allow(missing_docs)]
638 #[doc(hidden)]
639 #[inline]
640 pub fn _bits(&self) -> u8 {
641 match *self {
642 MUXW::_000 => 0,
643 MUXW::_001 => 1,
644 MUXW::_010 => 2,
645 MUXW::_011 => 3,
646 MUXW::_100 => 4,
647 MUXW::_101 => 5,
648 MUXW::_110 => 6,
649 MUXW::_111 => 7,
650 }
651 }
652}
653#[doc = r" Proxy"]
654pub struct _MUXW<'a> {
655 w: &'a mut W,
656}
657impl<'a> _MUXW<'a> {
658 #[doc = r" Writes `variant` to the field"]
659 #[inline]
660 pub fn variant(self, variant: MUXW) -> &'a mut W {
661 {
662 self.bits(variant._bits())
663 }
664 }
665 #[doc = "Pin disabled (analog)."]
666 #[inline]
667 pub fn _000(self) -> &'a mut W {
668 self.variant(MUXW::_000)
669 }
670 #[doc = "Alternative 1 (GPIO)."]
671 #[inline]
672 pub fn _001(self) -> &'a mut W {
673 self.variant(MUXW::_001)
674 }
675 #[doc = "Alternative 2 (chip-specific)."]
676 #[inline]
677 pub fn _010(self) -> &'a mut W {
678 self.variant(MUXW::_010)
679 }
680 #[doc = "Alternative 3 (chip-specific)."]
681 #[inline]
682 pub fn _011(self) -> &'a mut W {
683 self.variant(MUXW::_011)
684 }
685 #[doc = "Alternative 4 (chip-specific)."]
686 #[inline]
687 pub fn _100(self) -> &'a mut W {
688 self.variant(MUXW::_100)
689 }
690 #[doc = "Alternative 5 (chip-specific)."]
691 #[inline]
692 pub fn _101(self) -> &'a mut W {
693 self.variant(MUXW::_101)
694 }
695 #[doc = "Alternative 6 (chip-specific)."]
696 #[inline]
697 pub fn _110(self) -> &'a mut W {
698 self.variant(MUXW::_110)
699 }
700 #[doc = "Alternative 7 (chip-specific)."]
701 #[inline]
702 pub fn _111(self) -> &'a mut W {
703 self.variant(MUXW::_111)
704 }
705 #[doc = r" Writes raw bits to the field"]
706 #[inline]
707 pub fn bits(self, value: u8) -> &'a mut W {
708 const MASK: u8 = 7;
709 const OFFSET: u8 = 8;
710 self.w.bits &= !((MASK as u32) << OFFSET);
711 self.w.bits |= ((value & MASK) as u32) << OFFSET;
712 self.w
713 }
714}
715#[doc = "Values that can be written to the field `LK`"]
716pub enum LKW {
717 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
718 _0,
719 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
720 _1,
721}
722impl LKW {
723 #[allow(missing_docs)]
724 #[doc(hidden)]
725 #[inline]
726 pub fn _bits(&self) -> bool {
727 match *self {
728 LKW::_0 => false,
729 LKW::_1 => true,
730 }
731 }
732}
733#[doc = r" Proxy"]
734pub struct _LKW<'a> {
735 w: &'a mut W,
736}
737impl<'a> _LKW<'a> {
738 #[doc = r" Writes `variant` to the field"]
739 #[inline]
740 pub fn variant(self, variant: LKW) -> &'a mut W {
741 {
742 self.bit(variant._bits())
743 }
744 }
745 #[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
746 #[inline]
747 pub fn _0(self) -> &'a mut W {
748 self.variant(LKW::_0)
749 }
750 #[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
751 #[inline]
752 pub fn _1(self) -> &'a mut W {
753 self.variant(LKW::_1)
754 }
755 #[doc = r" Sets the field bit"]
756 pub fn set_bit(self) -> &'a mut W {
757 self.bit(true)
758 }
759 #[doc = r" Clears the field bit"]
760 pub fn clear_bit(self) -> &'a mut W {
761 self.bit(false)
762 }
763 #[doc = r" Writes raw bits to the field"]
764 #[inline]
765 pub fn bit(self, value: bool) -> &'a mut W {
766 const MASK: bool = true;
767 const OFFSET: u8 = 15;
768 self.w.bits &= !((MASK as u32) << OFFSET);
769 self.w.bits |= ((value & MASK) as u32) << OFFSET;
770 self.w
771 }
772}
773#[doc = "Values that can be written to the field `IRQC`"]
774pub enum IRQCW {
775 #[doc = "Interrupt/DMA request disabled."]
776 _0000,
777 #[doc = "DMA request on rising edge."]
778 _0001,
779 #[doc = "DMA request on falling edge."]
780 _0010,
781 #[doc = "DMA request on either edge."]
782 _0011,
783 #[doc = "Interrupt when logic 0."]
784 _1000,
785 #[doc = "Interrupt on rising-edge."]
786 _1001,
787 #[doc = "Interrupt on falling-edge."]
788 _1010,
789 #[doc = "Interrupt on either edge."]
790 _1011,
791 #[doc = "Interrupt when logic 1."]
792 _1100,
793}
794impl IRQCW {
795 #[allow(missing_docs)]
796 #[doc(hidden)]
797 #[inline]
798 pub fn _bits(&self) -> u8 {
799 match *self {
800 IRQCW::_0000 => 0,
801 IRQCW::_0001 => 1,
802 IRQCW::_0010 => 2,
803 IRQCW::_0011 => 3,
804 IRQCW::_1000 => 8,
805 IRQCW::_1001 => 9,
806 IRQCW::_1010 => 10,
807 IRQCW::_1011 => 11,
808 IRQCW::_1100 => 12,
809 }
810 }
811}
812#[doc = r" Proxy"]
813pub struct _IRQCW<'a> {
814 w: &'a mut W,
815}
816impl<'a> _IRQCW<'a> {
817 #[doc = r" Writes `variant` to the field"]
818 #[inline]
819 pub fn variant(self, variant: IRQCW) -> &'a mut W {
820 unsafe { self.bits(variant._bits()) }
821 }
822 #[doc = "Interrupt/DMA request disabled."]
823 #[inline]
824 pub fn _0000(self) -> &'a mut W {
825 self.variant(IRQCW::_0000)
826 }
827 #[doc = "DMA request on rising edge."]
828 #[inline]
829 pub fn _0001(self) -> &'a mut W {
830 self.variant(IRQCW::_0001)
831 }
832 #[doc = "DMA request on falling edge."]
833 #[inline]
834 pub fn _0010(self) -> &'a mut W {
835 self.variant(IRQCW::_0010)
836 }
837 #[doc = "DMA request on either edge."]
838 #[inline]
839 pub fn _0011(self) -> &'a mut W {
840 self.variant(IRQCW::_0011)
841 }
842 #[doc = "Interrupt when logic 0."]
843 #[inline]
844 pub fn _1000(self) -> &'a mut W {
845 self.variant(IRQCW::_1000)
846 }
847 #[doc = "Interrupt on rising-edge."]
848 #[inline]
849 pub fn _1001(self) -> &'a mut W {
850 self.variant(IRQCW::_1001)
851 }
852 #[doc = "Interrupt on falling-edge."]
853 #[inline]
854 pub fn _1010(self) -> &'a mut W {
855 self.variant(IRQCW::_1010)
856 }
857 #[doc = "Interrupt on either edge."]
858 #[inline]
859 pub fn _1011(self) -> &'a mut W {
860 self.variant(IRQCW::_1011)
861 }
862 #[doc = "Interrupt when logic 1."]
863 #[inline]
864 pub fn _1100(self) -> &'a mut W {
865 self.variant(IRQCW::_1100)
866 }
867 #[doc = r" Writes raw bits to the field"]
868 #[inline]
869 pub unsafe fn bits(self, value: u8) -> &'a mut W {
870 const MASK: u8 = 15;
871 const OFFSET: u8 = 16;
872 self.w.bits &= !((MASK as u32) << OFFSET);
873 self.w.bits |= ((value & MASK) as u32) << OFFSET;
874 self.w
875 }
876}
877#[doc = "Values that can be written to the field `ISF`"]
878pub enum ISFW {
879 #[doc = "Configured interrupt is not detected."]
880 _0,
881 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
882 _1,
883}
884impl ISFW {
885 #[allow(missing_docs)]
886 #[doc(hidden)]
887 #[inline]
888 pub fn _bits(&self) -> bool {
889 match *self {
890 ISFW::_0 => false,
891 ISFW::_1 => true,
892 }
893 }
894}
895#[doc = r" Proxy"]
896pub struct _ISFW<'a> {
897 w: &'a mut W,
898}
899impl<'a> _ISFW<'a> {
900 #[doc = r" Writes `variant` to the field"]
901 #[inline]
902 pub fn variant(self, variant: ISFW) -> &'a mut W {
903 {
904 self.bit(variant._bits())
905 }
906 }
907 #[doc = "Configured interrupt is not detected."]
908 #[inline]
909 pub fn _0(self) -> &'a mut W {
910 self.variant(ISFW::_0)
911 }
912 #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
913 #[inline]
914 pub fn _1(self) -> &'a mut W {
915 self.variant(ISFW::_1)
916 }
917 #[doc = r" Sets the field bit"]
918 pub fn set_bit(self) -> &'a mut W {
919 self.bit(true)
920 }
921 #[doc = r" Clears the field bit"]
922 pub fn clear_bit(self) -> &'a mut W {
923 self.bit(false)
924 }
925 #[doc = r" Writes raw bits to the field"]
926 #[inline]
927 pub fn bit(self, value: bool) -> &'a mut W {
928 const MASK: bool = true;
929 const OFFSET: u8 = 24;
930 self.w.bits &= !((MASK as u32) << OFFSET);
931 self.w.bits |= ((value & MASK) as u32) << OFFSET;
932 self.w
933 }
934}
935impl R {
936 #[doc = r" Value of the register as raw bits"]
937 #[inline]
938 pub fn bits(&self) -> u32 {
939 self.bits
940 }
941 #[doc = "Bit 0 - Pull Select"]
942 #[inline]
943 pub fn ps(&self) -> PSR {
944 PSR::_from({
945 const MASK: bool = true;
946 const OFFSET: u8 = 0;
947 ((self.bits >> OFFSET) & MASK as u32) != 0
948 })
949 }
950 #[doc = "Bit 1 - Pull Enable"]
951 #[inline]
952 pub fn pe(&self) -> PER {
953 PER::_from({
954 const MASK: bool = true;
955 const OFFSET: u8 = 1;
956 ((self.bits >> OFFSET) & MASK as u32) != 0
957 })
958 }
959 #[doc = "Bit 2 - Slew Rate Enable"]
960 #[inline]
961 pub fn sre(&self) -> SRER {
962 SRER::_from({
963 const MASK: bool = true;
964 const OFFSET: u8 = 2;
965 ((self.bits >> OFFSET) & MASK as u32) != 0
966 })
967 }
968 #[doc = "Bit 4 - Passive Filter Enable"]
969 #[inline]
970 pub fn pfe(&self) -> PFER {
971 PFER::_from({
972 const MASK: bool = true;
973 const OFFSET: u8 = 4;
974 ((self.bits >> OFFSET) & MASK as u32) != 0
975 })
976 }
977 #[doc = "Bit 5 - Open Drain Enable"]
978 #[inline]
979 pub fn ode(&self) -> ODER {
980 ODER::_from({
981 const MASK: bool = true;
982 const OFFSET: u8 = 5;
983 ((self.bits >> OFFSET) & MASK as u32) != 0
984 })
985 }
986 #[doc = "Bit 6 - Drive Strength Enable"]
987 #[inline]
988 pub fn dse(&self) -> DSER {
989 DSER::_from({
990 const MASK: bool = true;
991 const OFFSET: u8 = 6;
992 ((self.bits >> OFFSET) & MASK as u32) != 0
993 })
994 }
995 #[doc = "Bits 8:10 - Pin Mux Control"]
996 #[inline]
997 pub fn mux(&self) -> MUXR {
998 MUXR::_from({
999 const MASK: u8 = 7;
1000 const OFFSET: u8 = 8;
1001 ((self.bits >> OFFSET) & MASK as u32) as u8
1002 })
1003 }
1004 #[doc = "Bit 15 - Lock Register"]
1005 #[inline]
1006 pub fn lk(&self) -> LKR {
1007 LKR::_from({
1008 const MASK: bool = true;
1009 const OFFSET: u8 = 15;
1010 ((self.bits >> OFFSET) & MASK as u32) != 0
1011 })
1012 }
1013 #[doc = "Bits 16:19 - Interrupt Configuration"]
1014 #[inline]
1015 pub fn irqc(&self) -> IRQCR {
1016 IRQCR::_from({
1017 const MASK: u8 = 15;
1018 const OFFSET: u8 = 16;
1019 ((self.bits >> OFFSET) & MASK as u32) as u8
1020 })
1021 }
1022 #[doc = "Bit 24 - Interrupt Status Flag"]
1023 #[inline]
1024 pub fn isf(&self) -> ISFR {
1025 ISFR::_from({
1026 const MASK: bool = true;
1027 const OFFSET: u8 = 24;
1028 ((self.bits >> OFFSET) & MASK as u32) != 0
1029 })
1030 }
1031}
1032impl W {
1033 #[doc = r" Reset value of the register"]
1034 #[inline]
1035 pub fn reset_value() -> W {
1036 W { bits: 0 }
1037 }
1038 #[doc = r" Writes raw bits to the register"]
1039 #[inline]
1040 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1041 self.bits = bits;
1042 self
1043 }
1044 #[doc = "Bits 8:10 - Pin Mux Control"]
1045 #[inline]
1046 pub fn mux(&mut self) -> _MUXW {
1047 _MUXW { w: self }
1048 }
1049 #[doc = "Bit 15 - Lock Register"]
1050 #[inline]
1051 pub fn lk(&mut self) -> _LKW {
1052 _LKW { w: self }
1053 }
1054 #[doc = "Bits 16:19 - Interrupt Configuration"]
1055 #[inline]
1056 pub fn irqc(&mut self) -> _IRQCW {
1057 _IRQCW { w: self }
1058 }
1059 #[doc = "Bit 24 - Interrupt Status Flag"]
1060 #[inline]
1061 pub fn isf(&mut self) -> _ISFW {
1062 _ISFW { w: self }
1063 }
1064}