1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::RCR3 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct WDFLR {
47 bits: u8,
48}
49impl WDFLR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = "Possible values of the field `RCE0`"]
57#[derive(Clone, Copy, Debug, PartialEq)]
58pub enum RCE0R {
59 #[doc = "Receive data channel N is disabled."]
60 _0,
61 #[doc = "Receive data channel N is enabled."]
62 _1,
63}
64impl RCE0R {
65 #[doc = r" Returns `true` if the bit is clear (0)"]
66 #[inline]
67 pub fn bit_is_clear(&self) -> bool {
68 !self.bit()
69 }
70 #[doc = r" Returns `true` if the bit is set (1)"]
71 #[inline]
72 pub fn bit_is_set(&self) -> bool {
73 self.bit()
74 }
75 #[doc = r" Value of the field as raw bits"]
76 #[inline]
77 pub fn bit(&self) -> bool {
78 match *self {
79 RCE0R::_0 => false,
80 RCE0R::_1 => true,
81 }
82 }
83 #[allow(missing_docs)]
84 #[doc(hidden)]
85 #[inline]
86 pub fn _from(value: bool) -> RCE0R {
87 match value {
88 false => RCE0R::_0,
89 true => RCE0R::_1,
90 }
91 }
92 #[doc = "Checks if the value of the field is `_0`"]
93 #[inline]
94 pub fn is_0(&self) -> bool {
95 *self == RCE0R::_0
96 }
97 #[doc = "Checks if the value of the field is `_1`"]
98 #[inline]
99 pub fn is_1(&self) -> bool {
100 *self == RCE0R::_1
101 }
102}
103#[doc = "Possible values of the field `RCE1`"]
104#[derive(Clone, Copy, Debug, PartialEq)]
105pub enum RCE1R {
106 #[doc = "Receive data channel N is disabled."]
107 _0,
108 #[doc = "Receive data channel N is enabled."]
109 _1,
110}
111impl RCE1R {
112 #[doc = r" Returns `true` if the bit is clear (0)"]
113 #[inline]
114 pub fn bit_is_clear(&self) -> bool {
115 !self.bit()
116 }
117 #[doc = r" Returns `true` if the bit is set (1)"]
118 #[inline]
119 pub fn bit_is_set(&self) -> bool {
120 self.bit()
121 }
122 #[doc = r" Value of the field as raw bits"]
123 #[inline]
124 pub fn bit(&self) -> bool {
125 match *self {
126 RCE1R::_0 => false,
127 RCE1R::_1 => true,
128 }
129 }
130 #[allow(missing_docs)]
131 #[doc(hidden)]
132 #[inline]
133 pub fn _from(value: bool) -> RCE1R {
134 match value {
135 false => RCE1R::_0,
136 true => RCE1R::_1,
137 }
138 }
139 #[doc = "Checks if the value of the field is `_0`"]
140 #[inline]
141 pub fn is_0(&self) -> bool {
142 *self == RCE1R::_0
143 }
144 #[doc = "Checks if the value of the field is `_1`"]
145 #[inline]
146 pub fn is_1(&self) -> bool {
147 *self == RCE1R::_1
148 }
149}
150#[doc = r" Proxy"]
151pub struct _WDFLW<'a> {
152 w: &'a mut W,
153}
154impl<'a> _WDFLW<'a> {
155 #[doc = r" Writes raw bits to the field"]
156 #[inline]
157 pub unsafe fn bits(self, value: u8) -> &'a mut W {
158 const MASK: u8 = 31;
159 const OFFSET: u8 = 0;
160 self.w.bits &= !((MASK as u32) << OFFSET);
161 self.w.bits |= ((value & MASK) as u32) << OFFSET;
162 self.w
163 }
164}
165#[doc = "Values that can be written to the field `RCE0`"]
166pub enum RCE0W {
167 #[doc = "Receive data channel N is disabled."]
168 _0,
169 #[doc = "Receive data channel N is enabled."]
170 _1,
171}
172impl RCE0W {
173 #[allow(missing_docs)]
174 #[doc(hidden)]
175 #[inline]
176 pub fn _bits(&self) -> bool {
177 match *self {
178 RCE0W::_0 => false,
179 RCE0W::_1 => true,
180 }
181 }
182}
183#[doc = r" Proxy"]
184pub struct _RCE0W<'a> {
185 w: &'a mut W,
186}
187impl<'a> _RCE0W<'a> {
188 #[doc = r" Writes `variant` to the field"]
189 #[inline]
190 pub fn variant(self, variant: RCE0W) -> &'a mut W {
191 {
192 self.bit(variant._bits())
193 }
194 }
195 #[doc = "Receive data channel N is disabled."]
196 #[inline]
197 pub fn _0(self) -> &'a mut W {
198 self.variant(RCE0W::_0)
199 }
200 #[doc = "Receive data channel N is enabled."]
201 #[inline]
202 pub fn _1(self) -> &'a mut W {
203 self.variant(RCE0W::_1)
204 }
205 #[doc = r" Sets the field bit"]
206 pub fn set_bit(self) -> &'a mut W {
207 self.bit(true)
208 }
209 #[doc = r" Clears the field bit"]
210 pub fn clear_bit(self) -> &'a mut W {
211 self.bit(false)
212 }
213 #[doc = r" Writes raw bits to the field"]
214 #[inline]
215 pub fn bit(self, value: bool) -> &'a mut W {
216 const MASK: bool = true;
217 const OFFSET: u8 = 16;
218 self.w.bits &= !((MASK as u32) << OFFSET);
219 self.w.bits |= ((value & MASK) as u32) << OFFSET;
220 self.w
221 }
222}
223#[doc = "Values that can be written to the field `RCE1`"]
224pub enum RCE1W {
225 #[doc = "Receive data channel N is disabled."]
226 _0,
227 #[doc = "Receive data channel N is enabled."]
228 _1,
229}
230impl RCE1W {
231 #[allow(missing_docs)]
232 #[doc(hidden)]
233 #[inline]
234 pub fn _bits(&self) -> bool {
235 match *self {
236 RCE1W::_0 => false,
237 RCE1W::_1 => true,
238 }
239 }
240}
241#[doc = r" Proxy"]
242pub struct _RCE1W<'a> {
243 w: &'a mut W,
244}
245impl<'a> _RCE1W<'a> {
246 #[doc = r" Writes `variant` to the field"]
247 #[inline]
248 pub fn variant(self, variant: RCE1W) -> &'a mut W {
249 {
250 self.bit(variant._bits())
251 }
252 }
253 #[doc = "Receive data channel N is disabled."]
254 #[inline]
255 pub fn _0(self) -> &'a mut W {
256 self.variant(RCE1W::_0)
257 }
258 #[doc = "Receive data channel N is enabled."]
259 #[inline]
260 pub fn _1(self) -> &'a mut W {
261 self.variant(RCE1W::_1)
262 }
263 #[doc = r" Sets the field bit"]
264 pub fn set_bit(self) -> &'a mut W {
265 self.bit(true)
266 }
267 #[doc = r" Clears the field bit"]
268 pub fn clear_bit(self) -> &'a mut W {
269 self.bit(false)
270 }
271 #[doc = r" Writes raw bits to the field"]
272 #[inline]
273 pub fn bit(self, value: bool) -> &'a mut W {
274 const MASK: bool = true;
275 const OFFSET: u8 = 17;
276 self.w.bits &= !((MASK as u32) << OFFSET);
277 self.w.bits |= ((value & MASK) as u32) << OFFSET;
278 self.w
279 }
280}
281impl R {
282 #[doc = r" Value of the register as raw bits"]
283 #[inline]
284 pub fn bits(&self) -> u32 {
285 self.bits
286 }
287 #[doc = "Bits 0:4 - Word Flag Configuration"]
288 #[inline]
289 pub fn wdfl(&self) -> WDFLR {
290 let bits = {
291 const MASK: u8 = 31;
292 const OFFSET: u8 = 0;
293 ((self.bits >> OFFSET) & MASK as u32) as u8
294 };
295 WDFLR { bits }
296 }
297 #[doc = "Bit 16 - Receive Channel Enable"]
298 #[inline]
299 pub fn rce0(&self) -> RCE0R {
300 RCE0R::_from({
301 const MASK: bool = true;
302 const OFFSET: u8 = 16;
303 ((self.bits >> OFFSET) & MASK as u32) != 0
304 })
305 }
306 #[doc = "Bit 17 - Receive Channel Enable"]
307 #[inline]
308 pub fn rce1(&self) -> RCE1R {
309 RCE1R::_from({
310 const MASK: bool = true;
311 const OFFSET: u8 = 17;
312 ((self.bits >> OFFSET) & MASK as u32) != 0
313 })
314 }
315}
316impl W {
317 #[doc = r" Reset value of the register"]
318 #[inline]
319 pub fn reset_value() -> W {
320 W { bits: 0 }
321 }
322 #[doc = r" Writes raw bits to the register"]
323 #[inline]
324 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
325 self.bits = bits;
326 self
327 }
328 #[doc = "Bits 0:4 - Word Flag Configuration"]
329 #[inline]
330 pub fn wdfl(&mut self) -> _WDFLW {
331 _WDFLW { w: self }
332 }
333 #[doc = "Bit 16 - Receive Channel Enable"]
334 #[inline]
335 pub fn rce0(&mut self) -> _RCE0W {
336 _RCE0W { w: self }
337 }
338 #[doc = "Bit 17 - Receive Channel Enable"]
339 #[inline]
340 pub fn rce1(&mut self) -> _RCE1W {
341 _RCE1W { w: self }
342 }
343}