k510_pac/sysctl/
sys_ctl_int2_en.rs

1#[doc = "Register `SYS_CTL_INT2_EN` reader"]
2pub struct R(crate::R<SYS_CTL_INT2_EN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYS_CTL_INT2_EN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYS_CTL_INT2_EN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYS_CTL_INT2_EN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYS_CTL_INT2_EN` writer"]
17pub struct W(crate::W<SYS_CTL_INT2_EN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYS_CTL_INT2_EN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYS_CTL_INT2_EN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYS_CTL_INT2_EN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "ddrc dfs fail interrupt enable bit\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum DDRC_DFS_FAIL_IEN_A {
40    #[doc = "0: Disable interrupt"]
41    DISABLE = 0,
42    #[doc = "1: Enable interrupt"]
43    ENABLE = 1,
44}
45impl From<DDRC_DFS_FAIL_IEN_A> for bool {
46    #[inline(always)]
47    fn from(variant: DDRC_DFS_FAIL_IEN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `ddrc_dfs_fail_ien` reader - ddrc dfs fail interrupt enable bit"]
52pub type DDRC_DFS_FAIL_IEN_R = crate::BitReader<DDRC_DFS_FAIL_IEN_A>;
53impl DDRC_DFS_FAIL_IEN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> DDRC_DFS_FAIL_IEN_A {
57        match self.bits {
58            false => DDRC_DFS_FAIL_IEN_A::DISABLE,
59            true => DDRC_DFS_FAIL_IEN_A::ENABLE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DISABLE`"]
63    #[inline(always)]
64    pub fn is_disable(&self) -> bool {
65        *self == DDRC_DFS_FAIL_IEN_A::DISABLE
66    }
67    #[doc = "Checks if the value of the field is `ENABLE`"]
68    #[inline(always)]
69    pub fn is_enable(&self) -> bool {
70        *self == DDRC_DFS_FAIL_IEN_A::ENABLE
71    }
72}
73#[doc = "Field `ddrc_dfs_fail_ien` writer - ddrc dfs fail interrupt enable bit"]
74pub type DDRC_DFS_FAIL_IEN_W<'a> =
75    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, DDRC_DFS_FAIL_IEN_A, 7>;
76impl<'a> DDRC_DFS_FAIL_IEN_W<'a> {
77    #[doc = "Disable interrupt"]
78    #[inline(always)]
79    pub fn disable(self) -> &'a mut W {
80        self.variant(DDRC_DFS_FAIL_IEN_A::DISABLE)
81    }
82    #[doc = "Enable interrupt"]
83    #[inline(always)]
84    pub fn enable(self) -> &'a mut W {
85        self.variant(DDRC_DFS_FAIL_IEN_A::ENABLE)
86    }
87}
88#[doc = "ddrc dfs success interrupt enable bit\n\nValue on reset: 0"]
89#[derive(Clone, Copy, Debug, PartialEq)]
90pub enum DDRC_DFS_SUCCESS_IEN_A {
91    #[doc = "0: Disable interrupt"]
92    DISABLE = 0,
93    #[doc = "1: Enable interrupt"]
94    ENABLE = 1,
95}
96impl From<DDRC_DFS_SUCCESS_IEN_A> for bool {
97    #[inline(always)]
98    fn from(variant: DDRC_DFS_SUCCESS_IEN_A) -> Self {
99        variant as u8 != 0
100    }
101}
102#[doc = "Field `ddrc_dfs_success_ien` reader - ddrc dfs success interrupt enable bit"]
103pub type DDRC_DFS_SUCCESS_IEN_R = crate::BitReader<DDRC_DFS_SUCCESS_IEN_A>;
104impl DDRC_DFS_SUCCESS_IEN_R {
105    #[doc = "Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> DDRC_DFS_SUCCESS_IEN_A {
108        match self.bits {
109            false => DDRC_DFS_SUCCESS_IEN_A::DISABLE,
110            true => DDRC_DFS_SUCCESS_IEN_A::ENABLE,
111        }
112    }
113    #[doc = "Checks if the value of the field is `DISABLE`"]
114    #[inline(always)]
115    pub fn is_disable(&self) -> bool {
116        *self == DDRC_DFS_SUCCESS_IEN_A::DISABLE
117    }
118    #[doc = "Checks if the value of the field is `ENABLE`"]
119    #[inline(always)]
120    pub fn is_enable(&self) -> bool {
121        *self == DDRC_DFS_SUCCESS_IEN_A::ENABLE
122    }
123}
124#[doc = "Field `ddrc_dfs_success_ien` writer - ddrc dfs success interrupt enable bit"]
125pub type DDRC_DFS_SUCCESS_IEN_W<'a> =
126    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, DDRC_DFS_SUCCESS_IEN_A, 6>;
127impl<'a> DDRC_DFS_SUCCESS_IEN_W<'a> {
128    #[doc = "Disable interrupt"]
129    #[inline(always)]
130    pub fn disable(self) -> &'a mut W {
131        self.variant(DDRC_DFS_SUCCESS_IEN_A::DISABLE)
132    }
133    #[doc = "Enable interrupt"]
134    #[inline(always)]
135    pub fn enable(self) -> &'a mut W {
136        self.variant(DDRC_DFS_SUCCESS_IEN_A::ENABLE)
137    }
138}
139#[doc = "SoC core wake up from DEEPSLEEP mode interrupt enable bit\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum SOC_DSLP_WAKUP_IEN_A {
142    #[doc = "0: Disable interrupt"]
143    DISABLE = 0,
144    #[doc = "1: Enable interrupt"]
145    ENABLE = 1,
146}
147impl From<SOC_DSLP_WAKUP_IEN_A> for bool {
148    #[inline(always)]
149    fn from(variant: SOC_DSLP_WAKUP_IEN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153#[doc = "Field `soc_dslp_wakup_ien` reader - SoC core wake up from DEEPSLEEP mode interrupt enable bit"]
154pub type SOC_DSLP_WAKUP_IEN_R = crate::BitReader<SOC_DSLP_WAKUP_IEN_A>;
155impl SOC_DSLP_WAKUP_IEN_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> SOC_DSLP_WAKUP_IEN_A {
159        match self.bits {
160            false => SOC_DSLP_WAKUP_IEN_A::DISABLE,
161            true => SOC_DSLP_WAKUP_IEN_A::ENABLE,
162        }
163    }
164    #[doc = "Checks if the value of the field is `DISABLE`"]
165    #[inline(always)]
166    pub fn is_disable(&self) -> bool {
167        *self == SOC_DSLP_WAKUP_IEN_A::DISABLE
168    }
169    #[doc = "Checks if the value of the field is `ENABLE`"]
170    #[inline(always)]
171    pub fn is_enable(&self) -> bool {
172        *self == SOC_DSLP_WAKUP_IEN_A::ENABLE
173    }
174}
175#[doc = "Field `soc_dslp_wakup_ien` writer - SoC core wake up from DEEPSLEEP mode interrupt enable bit"]
176pub type SOC_DSLP_WAKUP_IEN_W<'a> =
177    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, SOC_DSLP_WAKUP_IEN_A, 5>;
178impl<'a> SOC_DSLP_WAKUP_IEN_W<'a> {
179    #[doc = "Disable interrupt"]
180    #[inline(always)]
181    pub fn disable(self) -> &'a mut W {
182        self.variant(SOC_DSLP_WAKUP_IEN_A::DISABLE)
183    }
184    #[doc = "Enable interrupt"]
185    #[inline(always)]
186    pub fn enable(self) -> &'a mut W {
187        self.variant(SOC_DSLP_WAKUP_IEN_A::ENABLE)
188    }
189}
190#[doc = "SoC core wake up from SLEEP1 mode interrupt enable bit\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq)]
192pub enum SOC_SLP1_WAKUP_IEN_A {
193    #[doc = "0: Disable interrupt"]
194    DISABLE = 0,
195    #[doc = "1: Enable interrupt"]
196    ENABLE = 1,
197}
198impl From<SOC_SLP1_WAKUP_IEN_A> for bool {
199    #[inline(always)]
200    fn from(variant: SOC_SLP1_WAKUP_IEN_A) -> Self {
201        variant as u8 != 0
202    }
203}
204#[doc = "Field `soc_slp1_wakup_ien` reader - SoC core wake up from SLEEP1 mode interrupt enable bit"]
205pub type SOC_SLP1_WAKUP_IEN_R = crate::BitReader<SOC_SLP1_WAKUP_IEN_A>;
206impl SOC_SLP1_WAKUP_IEN_R {
207    #[doc = "Get enumerated values variant"]
208    #[inline(always)]
209    pub fn variant(&self) -> SOC_SLP1_WAKUP_IEN_A {
210        match self.bits {
211            false => SOC_SLP1_WAKUP_IEN_A::DISABLE,
212            true => SOC_SLP1_WAKUP_IEN_A::ENABLE,
213        }
214    }
215    #[doc = "Checks if the value of the field is `DISABLE`"]
216    #[inline(always)]
217    pub fn is_disable(&self) -> bool {
218        *self == SOC_SLP1_WAKUP_IEN_A::DISABLE
219    }
220    #[doc = "Checks if the value of the field is `ENABLE`"]
221    #[inline(always)]
222    pub fn is_enable(&self) -> bool {
223        *self == SOC_SLP1_WAKUP_IEN_A::ENABLE
224    }
225}
226#[doc = "Field `soc_slp1_wakup_ien` writer - SoC core wake up from SLEEP1 mode interrupt enable bit"]
227pub type SOC_SLP1_WAKUP_IEN_W<'a> =
228    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, SOC_SLP1_WAKUP_IEN_A, 4>;
229impl<'a> SOC_SLP1_WAKUP_IEN_W<'a> {
230    #[doc = "Disable interrupt"]
231    #[inline(always)]
232    pub fn disable(self) -> &'a mut W {
233        self.variant(SOC_SLP1_WAKUP_IEN_A::DISABLE)
234    }
235    #[doc = "Enable interrupt"]
236    #[inline(always)]
237    pub fn enable(self) -> &'a mut W {
238        self.variant(SOC_SLP1_WAKUP_IEN_A::ENABLE)
239    }
240}
241#[doc = "SoC core wake up from SLEEP0 mode interrupt enable bit\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq)]
243pub enum SOC_SLP0_WAKUP_IEN_A {
244    #[doc = "0: Disable interrupt"]
245    DISABLE = 0,
246    #[doc = "1: Enable interrupt"]
247    ENABLE = 1,
248}
249impl From<SOC_SLP0_WAKUP_IEN_A> for bool {
250    #[inline(always)]
251    fn from(variant: SOC_SLP0_WAKUP_IEN_A) -> Self {
252        variant as u8 != 0
253    }
254}
255#[doc = "Field `soc_slp0_wakup_ien` reader - SoC core wake up from SLEEP0 mode interrupt enable bit"]
256pub type SOC_SLP0_WAKUP_IEN_R = crate::BitReader<SOC_SLP0_WAKUP_IEN_A>;
257impl SOC_SLP0_WAKUP_IEN_R {
258    #[doc = "Get enumerated values variant"]
259    #[inline(always)]
260    pub fn variant(&self) -> SOC_SLP0_WAKUP_IEN_A {
261        match self.bits {
262            false => SOC_SLP0_WAKUP_IEN_A::DISABLE,
263            true => SOC_SLP0_WAKUP_IEN_A::ENABLE,
264        }
265    }
266    #[doc = "Checks if the value of the field is `DISABLE`"]
267    #[inline(always)]
268    pub fn is_disable(&self) -> bool {
269        *self == SOC_SLP0_WAKUP_IEN_A::DISABLE
270    }
271    #[doc = "Checks if the value of the field is `ENABLE`"]
272    #[inline(always)]
273    pub fn is_enable(&self) -> bool {
274        *self == SOC_SLP0_WAKUP_IEN_A::ENABLE
275    }
276}
277#[doc = "Field `soc_slp0_wakup_ien` writer - SoC core wake up from SLEEP0 mode interrupt enable bit"]
278pub type SOC_SLP0_WAKUP_IEN_W<'a> =
279    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, SOC_SLP0_WAKUP_IEN_A, 3>;
280impl<'a> SOC_SLP0_WAKUP_IEN_W<'a> {
281    #[doc = "Disable interrupt"]
282    #[inline(always)]
283    pub fn disable(self) -> &'a mut W {
284        self.variant(SOC_SLP0_WAKUP_IEN_A::DISABLE)
285    }
286    #[doc = "Enable interrupt"]
287    #[inline(always)]
288    pub fn enable(self) -> &'a mut W {
289        self.variant(SOC_SLP0_WAKUP_IEN_A::ENABLE)
290    }
291}
292#[doc = "SoC core entering DEEPSLEEP mode interrupt enable bit\n\nValue on reset: 0"]
293#[derive(Clone, Copy, Debug, PartialEq)]
294pub enum SOC_GO_DSLP_IEN_A {
295    #[doc = "0: Disable interrupt"]
296    DISABLE = 0,
297    #[doc = "1: Enable interrupt"]
298    ENABLE = 1,
299}
300impl From<SOC_GO_DSLP_IEN_A> for bool {
301    #[inline(always)]
302    fn from(variant: SOC_GO_DSLP_IEN_A) -> Self {
303        variant as u8 != 0
304    }
305}
306#[doc = "Field `soc_go_dslp_ien` reader - SoC core entering DEEPSLEEP mode interrupt enable bit"]
307pub type SOC_GO_DSLP_IEN_R = crate::BitReader<SOC_GO_DSLP_IEN_A>;
308impl SOC_GO_DSLP_IEN_R {
309    #[doc = "Get enumerated values variant"]
310    #[inline(always)]
311    pub fn variant(&self) -> SOC_GO_DSLP_IEN_A {
312        match self.bits {
313            false => SOC_GO_DSLP_IEN_A::DISABLE,
314            true => SOC_GO_DSLP_IEN_A::ENABLE,
315        }
316    }
317    #[doc = "Checks if the value of the field is `DISABLE`"]
318    #[inline(always)]
319    pub fn is_disable(&self) -> bool {
320        *self == SOC_GO_DSLP_IEN_A::DISABLE
321    }
322    #[doc = "Checks if the value of the field is `ENABLE`"]
323    #[inline(always)]
324    pub fn is_enable(&self) -> bool {
325        *self == SOC_GO_DSLP_IEN_A::ENABLE
326    }
327}
328#[doc = "Field `soc_go_dslp_ien` writer - SoC core entering DEEPSLEEP mode interrupt enable bit"]
329pub type SOC_GO_DSLP_IEN_W<'a> =
330    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, SOC_GO_DSLP_IEN_A, 2>;
331impl<'a> SOC_GO_DSLP_IEN_W<'a> {
332    #[doc = "Disable interrupt"]
333    #[inline(always)]
334    pub fn disable(self) -> &'a mut W {
335        self.variant(SOC_GO_DSLP_IEN_A::DISABLE)
336    }
337    #[doc = "Enable interrupt"]
338    #[inline(always)]
339    pub fn enable(self) -> &'a mut W {
340        self.variant(SOC_GO_DSLP_IEN_A::ENABLE)
341    }
342}
343#[doc = "SoC core entering SLEEP1 mode interrupt enable bit\n\nValue on reset: 0"]
344#[derive(Clone, Copy, Debug, PartialEq)]
345pub enum SOC_GO_SLP1_IEN_A {
346    #[doc = "0: Disable interrupt"]
347    DISABLE = 0,
348    #[doc = "1: Enable interrupt"]
349    ENABLE = 1,
350}
351impl From<SOC_GO_SLP1_IEN_A> for bool {
352    #[inline(always)]
353    fn from(variant: SOC_GO_SLP1_IEN_A) -> Self {
354        variant as u8 != 0
355    }
356}
357#[doc = "Field `soc_go_slp1_ien` reader - SoC core entering SLEEP1 mode interrupt enable bit"]
358pub type SOC_GO_SLP1_IEN_R = crate::BitReader<SOC_GO_SLP1_IEN_A>;
359impl SOC_GO_SLP1_IEN_R {
360    #[doc = "Get enumerated values variant"]
361    #[inline(always)]
362    pub fn variant(&self) -> SOC_GO_SLP1_IEN_A {
363        match self.bits {
364            false => SOC_GO_SLP1_IEN_A::DISABLE,
365            true => SOC_GO_SLP1_IEN_A::ENABLE,
366        }
367    }
368    #[doc = "Checks if the value of the field is `DISABLE`"]
369    #[inline(always)]
370    pub fn is_disable(&self) -> bool {
371        *self == SOC_GO_SLP1_IEN_A::DISABLE
372    }
373    #[doc = "Checks if the value of the field is `ENABLE`"]
374    #[inline(always)]
375    pub fn is_enable(&self) -> bool {
376        *self == SOC_GO_SLP1_IEN_A::ENABLE
377    }
378}
379#[doc = "Field `soc_go_slp1_ien` writer - SoC core entering SLEEP1 mode interrupt enable bit"]
380pub type SOC_GO_SLP1_IEN_W<'a> =
381    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, SOC_GO_SLP1_IEN_A, 1>;
382impl<'a> SOC_GO_SLP1_IEN_W<'a> {
383    #[doc = "Disable interrupt"]
384    #[inline(always)]
385    pub fn disable(self) -> &'a mut W {
386        self.variant(SOC_GO_SLP1_IEN_A::DISABLE)
387    }
388    #[doc = "Enable interrupt"]
389    #[inline(always)]
390    pub fn enable(self) -> &'a mut W {
391        self.variant(SOC_GO_SLP1_IEN_A::ENABLE)
392    }
393}
394#[doc = "SoC core entering SLEEP0 mode interrupt enable bit\n\nValue on reset: 0"]
395#[derive(Clone, Copy, Debug, PartialEq)]
396pub enum SOC_GO_SLP0_IEN_A {
397    #[doc = "0: Disable interrupt"]
398    DISABLE = 0,
399    #[doc = "1: Enable interrupt"]
400    ENABLE = 1,
401}
402impl From<SOC_GO_SLP0_IEN_A> for bool {
403    #[inline(always)]
404    fn from(variant: SOC_GO_SLP0_IEN_A) -> Self {
405        variant as u8 != 0
406    }
407}
408#[doc = "Field `soc_go_slp0_ien` reader - SoC core entering SLEEP0 mode interrupt enable bit"]
409pub type SOC_GO_SLP0_IEN_R = crate::BitReader<SOC_GO_SLP0_IEN_A>;
410impl SOC_GO_SLP0_IEN_R {
411    #[doc = "Get enumerated values variant"]
412    #[inline(always)]
413    pub fn variant(&self) -> SOC_GO_SLP0_IEN_A {
414        match self.bits {
415            false => SOC_GO_SLP0_IEN_A::DISABLE,
416            true => SOC_GO_SLP0_IEN_A::ENABLE,
417        }
418    }
419    #[doc = "Checks if the value of the field is `DISABLE`"]
420    #[inline(always)]
421    pub fn is_disable(&self) -> bool {
422        *self == SOC_GO_SLP0_IEN_A::DISABLE
423    }
424    #[doc = "Checks if the value of the field is `ENABLE`"]
425    #[inline(always)]
426    pub fn is_enable(&self) -> bool {
427        *self == SOC_GO_SLP0_IEN_A::ENABLE
428    }
429}
430#[doc = "Field `soc_go_slp0_ien` writer - SoC core entering SLEEP0 mode interrupt enable bit"]
431pub type SOC_GO_SLP0_IEN_W<'a> =
432    crate::BitWriter<'a, u32, SYS_CTL_INT2_EN_SPEC, SOC_GO_SLP0_IEN_A, 0>;
433impl<'a> SOC_GO_SLP0_IEN_W<'a> {
434    #[doc = "Disable interrupt"]
435    #[inline(always)]
436    pub fn disable(self) -> &'a mut W {
437        self.variant(SOC_GO_SLP0_IEN_A::DISABLE)
438    }
439    #[doc = "Enable interrupt"]
440    #[inline(always)]
441    pub fn enable(self) -> &'a mut W {
442        self.variant(SOC_GO_SLP0_IEN_A::ENABLE)
443    }
444}
445impl R {
446    #[doc = "Bit 7 - ddrc dfs fail interrupt enable bit"]
447    #[inline(always)]
448    pub fn ddrc_dfs_fail_ien(&self) -> DDRC_DFS_FAIL_IEN_R {
449        DDRC_DFS_FAIL_IEN_R::new(((self.bits >> 7) & 1) != 0)
450    }
451    #[doc = "Bit 6 - ddrc dfs success interrupt enable bit"]
452    #[inline(always)]
453    pub fn ddrc_dfs_success_ien(&self) -> DDRC_DFS_SUCCESS_IEN_R {
454        DDRC_DFS_SUCCESS_IEN_R::new(((self.bits >> 6) & 1) != 0)
455    }
456    #[doc = "Bit 5 - SoC core wake up from DEEPSLEEP mode interrupt enable bit"]
457    #[inline(always)]
458    pub fn soc_dslp_wakup_ien(&self) -> SOC_DSLP_WAKUP_IEN_R {
459        SOC_DSLP_WAKUP_IEN_R::new(((self.bits >> 5) & 1) != 0)
460    }
461    #[doc = "Bit 4 - SoC core wake up from SLEEP1 mode interrupt enable bit"]
462    #[inline(always)]
463    pub fn soc_slp1_wakup_ien(&self) -> SOC_SLP1_WAKUP_IEN_R {
464        SOC_SLP1_WAKUP_IEN_R::new(((self.bits >> 4) & 1) != 0)
465    }
466    #[doc = "Bit 3 - SoC core wake up from SLEEP0 mode interrupt enable bit"]
467    #[inline(always)]
468    pub fn soc_slp0_wakup_ien(&self) -> SOC_SLP0_WAKUP_IEN_R {
469        SOC_SLP0_WAKUP_IEN_R::new(((self.bits >> 3) & 1) != 0)
470    }
471    #[doc = "Bit 2 - SoC core entering DEEPSLEEP mode interrupt enable bit"]
472    #[inline(always)]
473    pub fn soc_go_dslp_ien(&self) -> SOC_GO_DSLP_IEN_R {
474        SOC_GO_DSLP_IEN_R::new(((self.bits >> 2) & 1) != 0)
475    }
476    #[doc = "Bit 1 - SoC core entering SLEEP1 mode interrupt enable bit"]
477    #[inline(always)]
478    pub fn soc_go_slp1_ien(&self) -> SOC_GO_SLP1_IEN_R {
479        SOC_GO_SLP1_IEN_R::new(((self.bits >> 1) & 1) != 0)
480    }
481    #[doc = "Bit 0 - SoC core entering SLEEP0 mode interrupt enable bit"]
482    #[inline(always)]
483    pub fn soc_go_slp0_ien(&self) -> SOC_GO_SLP0_IEN_R {
484        SOC_GO_SLP0_IEN_R::new((self.bits & 1) != 0)
485    }
486}
487impl W {
488    #[doc = "Bit 7 - ddrc dfs fail interrupt enable bit"]
489    #[inline(always)]
490    pub fn ddrc_dfs_fail_ien(&mut self) -> DDRC_DFS_FAIL_IEN_W {
491        DDRC_DFS_FAIL_IEN_W::new(self)
492    }
493    #[doc = "Bit 6 - ddrc dfs success interrupt enable bit"]
494    #[inline(always)]
495    pub fn ddrc_dfs_success_ien(&mut self) -> DDRC_DFS_SUCCESS_IEN_W {
496        DDRC_DFS_SUCCESS_IEN_W::new(self)
497    }
498    #[doc = "Bit 5 - SoC core wake up from DEEPSLEEP mode interrupt enable bit"]
499    #[inline(always)]
500    pub fn soc_dslp_wakup_ien(&mut self) -> SOC_DSLP_WAKUP_IEN_W {
501        SOC_DSLP_WAKUP_IEN_W::new(self)
502    }
503    #[doc = "Bit 4 - SoC core wake up from SLEEP1 mode interrupt enable bit"]
504    #[inline(always)]
505    pub fn soc_slp1_wakup_ien(&mut self) -> SOC_SLP1_WAKUP_IEN_W {
506        SOC_SLP1_WAKUP_IEN_W::new(self)
507    }
508    #[doc = "Bit 3 - SoC core wake up from SLEEP0 mode interrupt enable bit"]
509    #[inline(always)]
510    pub fn soc_slp0_wakup_ien(&mut self) -> SOC_SLP0_WAKUP_IEN_W {
511        SOC_SLP0_WAKUP_IEN_W::new(self)
512    }
513    #[doc = "Bit 2 - SoC core entering DEEPSLEEP mode interrupt enable bit"]
514    #[inline(always)]
515    pub fn soc_go_dslp_ien(&mut self) -> SOC_GO_DSLP_IEN_W {
516        SOC_GO_DSLP_IEN_W::new(self)
517    }
518    #[doc = "Bit 1 - SoC core entering SLEEP1 mode interrupt enable bit"]
519    #[inline(always)]
520    pub fn soc_go_slp1_ien(&mut self) -> SOC_GO_SLP1_IEN_W {
521        SOC_GO_SLP1_IEN_W::new(self)
522    }
523    #[doc = "Bit 0 - SoC core entering SLEEP0 mode interrupt enable bit"]
524    #[inline(always)]
525    pub fn soc_go_slp0_ien(&mut self) -> SOC_GO_SLP0_IEN_W {
526        SOC_GO_SLP0_IEN_W::new(self)
527    }
528    #[doc = "Writes raw bits to the register."]
529    #[inline(always)]
530    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
531        self.0.bits(bits);
532        self
533    }
534}
535#[doc = "Sysctl module interrupt 2 interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sys_ctl_int2_en](index.html) module"]
536pub struct SYS_CTL_INT2_EN_SPEC;
537impl crate::RegisterSpec for SYS_CTL_INT2_EN_SPEC {
538    type Ux = u32;
539}
540#[doc = "`read()` method returns [sys_ctl_int2_en::R](R) reader structure"]
541impl crate::Readable for SYS_CTL_INT2_EN_SPEC {
542    type Reader = R;
543}
544#[doc = "`write(|w| ..)` method takes [sys_ctl_int2_en::W](W) writer structure"]
545impl crate::Writable for SYS_CTL_INT2_EN_SPEC {
546    type Writer = W;
547}
548#[doc = "`reset()` method sets SYS_CTL_INT2_EN to value 0"]
549impl crate::Resettable for SYS_CTL_INT2_EN_SPEC {
550    #[inline(always)]
551    fn reset_value() -> Self::Ux {
552        0
553    }
554}
k510_pac/sysctl/sys_ctl_int2_en.rs

k510_pac/sysctl/
sys_ctl_int2_en.rs
