k510_pac/gpio/
gpio_intmask.rs

1#[doc = "Register `GPIO_INTMASK` reader"]
2pub struct R(crate::R<GPIO_INTMASK_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GPIO_INTMASK_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GPIO_INTMASK_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GPIO_INTMASK_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GPIO_INTMASK` writer"]
17pub struct W(crate::W<GPIO_INTMASK_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GPIO_INTMASK_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GPIO_INTMASK_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GPIO_INTMASK_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u32)]
40pub enum GPIO_INTMASK_A {
41    #[doc = "0: Interrupt bits are unmasked"]
42    DISABLE = 0,
43    #[doc = "1: Mask interrupt"]
44    ENABLE = 1,
45}
46impl From<GPIO_INTMASK_A> for u32 {
47    #[inline(always)]
48    fn from(variant: GPIO_INTMASK_A) -> Self {
49        variant as _
50    }
51}
52#[doc = "Field `GPIO_INTMASK` reader - Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking."]
53pub type GPIO_INTMASK_R = crate::FieldReader<u32, GPIO_INTMASK_A>;
54impl GPIO_INTMASK_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<GPIO_INTMASK_A> {
58        match self.bits {
59            0 => Some(GPIO_INTMASK_A::DISABLE),
60            1 => Some(GPIO_INTMASK_A::ENABLE),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `DISABLE`"]
65    #[inline(always)]
66    pub fn is_disable(&self) -> bool {
67        *self == GPIO_INTMASK_A::DISABLE
68    }
69    #[doc = "Checks if the value of the field is `ENABLE`"]
70    #[inline(always)]
71    pub fn is_enable(&self) -> bool {
72        *self == GPIO_INTMASK_A::ENABLE
73    }
74}
75#[doc = "Field `GPIO_INTMASK` writer - Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking."]
76pub type GPIO_INTMASK_W<'a> =
77    crate::FieldWriter<'a, u32, GPIO_INTMASK_SPEC, u32, GPIO_INTMASK_A, 32, 0>;
78impl<'a> GPIO_INTMASK_W<'a> {
79    #[doc = "Interrupt bits are unmasked"]
80    #[inline(always)]
81    pub fn disable(self) -> &'a mut W {
82        self.variant(GPIO_INTMASK_A::DISABLE)
83    }
84    #[doc = "Mask interrupt"]
85    #[inline(always)]
86    pub fn enable(self) -> &'a mut W {
87        self.variant(GPIO_INTMASK_A::ENABLE)
88    }
89}
90impl R {
91    #[doc = "Bits 0:31 - Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking."]
92    #[inline(always)]
93    pub fn gpio_intmask(&self) -> GPIO_INTMASK_R {
94        GPIO_INTMASK_R::new(self.bits)
95    }
96}
97impl W {
98    #[doc = "Bits 0:31 - Controls whether an interrupt on Port A can create an interrupt for the interrupt controller by not masking it. By default, all interrupts bits are unmasked. Whenever a 1 is written to a bit in this register, it masks the interrupt generation capability for this signal; otherwise interrupts are allowed through. The unmasked status can be read as well as the resultant status after masking."]
99    #[inline(always)]
100    pub fn gpio_intmask(&mut self) -> GPIO_INTMASK_W {
101        GPIO_INTMASK_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "interrupt mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_intmask](index.html) module"]
111pub struct GPIO_INTMASK_SPEC;
112impl crate::RegisterSpec for GPIO_INTMASK_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [gpio_intmask::R](R) reader structure"]
116impl crate::Readable for GPIO_INTMASK_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [gpio_intmask::W](W) writer structure"]
120impl crate::Writable for GPIO_INTMASK_SPEC {
121    type Writer = W;
122}
123#[doc = "`reset()` method sets GPIO_INTMASK to value 0"]
124impl crate::Resettable for GPIO_INTMASK_SPEC {
125    #[inline(always)]
126    fn reset_value() -> Self::Ux {
127        0
128    }
129}
k510_pac/gpio/gpio_intmask.rs

k510_pac/gpio/
gpio_intmask.rs
