[−][src]Type Definition k210_pac::sysctl::CLK_EN_CENT
type CLK_EN_CENT = Reg<u32, _CLK_EN_CENT>;
Central clock enable
This register you can read, reset, write, write_with_zero, modify. See API.
For information about avaliable fields see clk_en_cent module
Trait Implementations
impl Readable for CLK_EN_CENT[src]
read() method returns clk_en_cent::R reader structure
impl Writable for CLK_EN_CENT[src]
write(|w| ..) method takes clk_en_cent::W writer structure
impl ResetValue for CLK_EN_CENT[src]
Register clk_en_cent reset()'s with value 0