[−][src]Struct k210_pac::spi3::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ctrlr0: CTRLR0,
    pub ctrlr1: CTRLR1,
    pub ssienr: SSIENR,
    pub mwcr: MWCR,
    pub ser: SER,
    pub baudr: BAUDR,
    pub txftlr: TXFTLR,
    pub rxftlr: RXFTLR,
    pub txflr: TXFLR,
    pub rxflr: RXFLR,
    pub sr: SR,
    pub imr: IMR,
    pub isr: ISR,
    pub risr: RISR,
    pub txoicr: TXOICR,
    pub rxoicr: RXOICR,
    pub rxuicr: RXUICR,
    pub msticr: MSTICR,
    pub icr: ICR,
    pub dmacr: DMACR,
    pub dmatdlr: DMATDLR,
    pub dmardlr: DMARDLR,
    pub idr: IDR,
    pub ssic_version_id: SSIC_VERSION_ID,
    pub dr: [DR; 36],
    pub rx_sample_delay: RX_SAMPLE_DELAY,
    pub spi_ctrlr0: SPI_CTRLR0,
    pub xip_mode_bits: XIP_MODE_BITS,
    pub xip_incr_inst: XIP_INCR_INST,
    pub xip_wrap_inst: XIP_WRAP_INST,
    pub xip_ctrl: XIP_CTRL,
    pub xip_ser: XIP_SER,
    pub xrxoicr: XRXOICR,
    pub xip_cnt_time_out: XIP_CNT_TIME_OUT,
    pub endian: ENDIAN,
    // some fields omitted
}

Register block

Fields

ctrlr0: CTRLR0

0x00 - Control Register 0

ctrlr1: CTRLR1

0x04 - Control Register 1

ssienr: SSIENR

0x08 - Enable Register

mwcr: MWCR

0x0c - Microwire Control Register

ser: SER

0x10 - Slave Enable Register

baudr: BAUDR

0x14 - Baud Rate Select

txftlr: TXFTLR

0x18 - Transmit FIFO Threshold Level

rxftlr: RXFTLR

0x1c - Receive FIFO Threshold Level

txflr: TXFLR

0x20 - Transmit FIFO Level Register

rxflr: RXFLR

0x24 - Receive FIFO Level Register

sr: SR

0x28 - Status Register

imr: IMR

0x2c - Interrupt Mask Register

isr: ISR

0x30 - Interrupt Status Register

risr: RISR

0x34 - Raw Interrupt Status Register

txoicr: TXOICR

0x38 - Transmit FIFO Overflow Interrupt Clear Register

rxoicr: RXOICR

0x3c - Receive FIFO Overflow Interrupt Clear Register

rxuicr: RXUICR

0x40 - Receive FIFO Underflow Interrupt Clear Register

msticr: MSTICR

0x44 - Multi-Master Interrupt Clear Register

icr: ICR

0x48 - Interrupt Clear Register

dmacr: DMACR

0x4c - DMA Control Register

dmatdlr: DMATDLR

0x50 - DMA Transmit Data Level

dmardlr: DMARDLR

0x54 - DMA Receive Data Level

idr: IDR

0x58 - Identification Register

ssic_version_id: SSIC_VERSION_ID

0x5c - DWC_ssi component version

dr: [DR; 36]

0x60 - Data Register

rx_sample_delay: RX_SAMPLE_DELAY

0xf0 - RX Sample Delay Register

spi_ctrlr0: SPI_CTRLR0

0xf4 - SPI Control Register

xip_mode_bits: XIP_MODE_BITS

0xfc - XIP Mode bits

xip_incr_inst: XIP_INCR_INST

0x100 - XIP INCR transfer opcode

xip_wrap_inst: XIP_WRAP_INST

0x104 - XIP WRAP transfer opcode

xip_ctrl: XIP_CTRL

0x108 - XIP Control Register

xip_ser: XIP_SER

0x10c - XIP Slave Enable Register

xrxoicr: XRXOICR

0x110 - XIP Receive FIFO Overflow Interrupt Clear Register

xip_cnt_time_out: XIP_CNT_TIME_OUT

0x114 - XIP time out register for continuous transfers

endian: ENDIAN

0x118 - ENDIAN

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