[−][src]Type Definition k210_pac::sysctl::CLK_EN_PERI
type CLK_EN_PERI = Reg<u32, _CLK_EN_PERI>;
Peripheral clock enable
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see clk_en_peri module
Trait Implementations
impl Readable for CLK_EN_PERI
[src]
read()
method returns clk_en_peri::R reader structure
impl Writable for CLK_EN_PERI
[src]
write(|w| ..)
method takes clk_en_peri::W writer structure
impl ResetValue for CLK_EN_PERI
[src]
Register clk_en_peri reset()
's with value 0