1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384
#[doc = "Reader of register ADC_CTRL2"] pub type R = crate::R<u32, super::ADC_CTRL2>; #[doc = "Writer for register ADC_CTRL2"] pub type W = crate::W<u32, super::ADC_CTRL2>; #[doc = "Register ADC_CTRL2 `reset()`'s with value 0"] impl crate::ResetValue for super::ADC_CTRL2 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `CLKEN_ADC8`"] pub type CLKEN_ADC8_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLKEN_ADC8`"] pub struct CLKEN_ADC8_W<'a> { w: &'a mut W, } impl<'a> CLKEN_ADC8_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `DIVEN_ADC8`"] pub type DIVEN_ADC8_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DIVEN_ADC8`"] pub struct DIVEN_ADC8_W<'a> { w: &'a mut W, } impl<'a> DIVEN_ADC8_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `DIV_ADC8`"] pub type DIV_ADC8_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DIV_ADC8`"] pub struct DIV_ADC8_W<'a> { w: &'a mut W, } impl<'a> DIV_ADC8_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3f << 2)) | (((value as u32) & 0x3f) << 2); self.w } } #[doc = "Reader of field `CLKEN_ADC9`"] pub type CLKEN_ADC9_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLKEN_ADC9`"] pub struct CLKEN_ADC9_W<'a> { w: &'a mut W, } impl<'a> CLKEN_ADC9_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `DIVEN_ADC9`"] pub type DIVEN_ADC9_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DIVEN_ADC9`"] pub struct DIVEN_ADC9_W<'a> { w: &'a mut W, } impl<'a> DIVEN_ADC9_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } #[doc = "Reader of field `DIV_ADC9`"] pub type DIV_ADC9_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DIV_ADC9`"] pub struct DIV_ADC9_W<'a> { w: &'a mut W, } impl<'a> DIV_ADC9_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3f << 10)) | (((value as u32) & 0x3f) << 10); self.w } } #[doc = "Reader of field `CLKEN_ADC10`"] pub type CLKEN_ADC10_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLKEN_ADC10`"] pub struct CLKEN_ADC10_W<'a> { w: &'a mut W, } impl<'a> CLKEN_ADC10_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `DIVEN_ADC10`"] pub type DIVEN_ADC10_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DIVEN_ADC10`"] pub struct DIVEN_ADC10_W<'a> { w: &'a mut W, } impl<'a> DIVEN_ADC10_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `DIV_ADC10`"] pub type DIV_ADC10_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DIV_ADC10`"] pub struct DIV_ADC10_W<'a> { w: &'a mut W, } impl<'a> DIV_ADC10_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3f << 18)) | (((value as u32) & 0x3f) << 18); self.w } } #[doc = "Reader of field `CLKEN_ADC11`"] pub type CLKEN_ADC11_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CLKEN_ADC11`"] pub struct CLKEN_ADC11_W<'a> { w: &'a mut W, } impl<'a> CLKEN_ADC11_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } #[doc = "Reader of field `DIVEN_ADC11`"] pub type DIVEN_ADC11_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DIVEN_ADC11`"] pub struct DIVEN_ADC11_W<'a> { w: &'a mut W, } impl<'a> DIVEN_ADC11_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); self.w } } #[doc = "Reader of field `DIV_ADC11`"] pub type DIV_ADC11_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DIV_ADC11`"] pub struct DIV_ADC11_W<'a> { w: &'a mut W, } impl<'a> DIV_ADC11_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x3f << 26)) | (((value as u32) & 0x3f) << 26); self.w } } impl R { #[doc = "Bit 0 - Enable clk ADC8"] #[inline(always)] pub fn clken_adc8(&self) -> CLKEN_ADC8_R { CLKEN_ADC8_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - Enable divider clk ADC8"] #[inline(always)] pub fn diven_adc8(&self) -> DIVEN_ADC8_R { DIVEN_ADC8_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bits 2:7 - Divider clk ADC8"] #[inline(always)] pub fn div_adc8(&self) -> DIV_ADC8_R { DIV_ADC8_R::new(((self.bits >> 2) & 0x3f) as u8) } #[doc = "Bit 8 - Enable clk ADC9"] #[inline(always)] pub fn clken_adc9(&self) -> CLKEN_ADC9_R { CLKEN_ADC9_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 9 - Enable divider clk ADC9"] #[inline(always)] pub fn diven_adc9(&self) -> DIVEN_ADC9_R { DIVEN_ADC9_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bits 10:15 - Divider clk ADC9"] #[inline(always)] pub fn div_adc9(&self) -> DIV_ADC9_R { DIV_ADC9_R::new(((self.bits >> 10) & 0x3f) as u8) } #[doc = "Bit 16 - Enable clk ADC10"] #[inline(always)] pub fn clken_adc10(&self) -> CLKEN_ADC10_R { CLKEN_ADC10_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 17 - Enable divider clk ADC10"] #[inline(always)] pub fn diven_adc10(&self) -> DIVEN_ADC10_R { DIVEN_ADC10_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bits 18:23 - Divider clk ADC10"] #[inline(always)] pub fn div_adc10(&self) -> DIV_ADC10_R { DIV_ADC10_R::new(((self.bits >> 18) & 0x3f) as u8) } #[doc = "Bit 24 - Enable clk ADC11"] #[inline(always)] pub fn clken_adc11(&self) -> CLKEN_ADC11_R { CLKEN_ADC11_R::new(((self.bits >> 24) & 0x01) != 0) } #[doc = "Bit 25 - Enable divider clk ADC11"] #[inline(always)] pub fn diven_adc11(&self) -> DIVEN_ADC11_R { DIVEN_ADC11_R::new(((self.bits >> 25) & 0x01) != 0) } #[doc = "Bits 26:31 - Divider clk ADC11"] #[inline(always)] pub fn div_adc11(&self) -> DIV_ADC11_R { DIV_ADC11_R::new(((self.bits >> 26) & 0x3f) as u8) } } impl W { #[doc = "Bit 0 - Enable clk ADC8"] #[inline(always)] pub fn clken_adc8(&mut self) -> CLKEN_ADC8_W { CLKEN_ADC8_W { w: self } } #[doc = "Bit 1 - Enable divider clk ADC8"] #[inline(always)] pub fn diven_adc8(&mut self) -> DIVEN_ADC8_W { DIVEN_ADC8_W { w: self } } #[doc = "Bits 2:7 - Divider clk ADC8"] #[inline(always)] pub fn div_adc8(&mut self) -> DIV_ADC8_W { DIV_ADC8_W { w: self } } #[doc = "Bit 8 - Enable clk ADC9"] #[inline(always)] pub fn clken_adc9(&mut self) -> CLKEN_ADC9_W { CLKEN_ADC9_W { w: self } } #[doc = "Bit 9 - Enable divider clk ADC9"] #[inline(always)] pub fn diven_adc9(&mut self) -> DIVEN_ADC9_W { DIVEN_ADC9_W { w: self } } #[doc = "Bits 10:15 - Divider clk ADC9"] #[inline(always)] pub fn div_adc9(&mut self) -> DIV_ADC9_W { DIV_ADC9_W { w: self } } #[doc = "Bit 16 - Enable clk ADC10"] #[inline(always)] pub fn clken_adc10(&mut self) -> CLKEN_ADC10_W { CLKEN_ADC10_W { w: self } } #[doc = "Bit 17 - Enable divider clk ADC10"] #[inline(always)] pub fn diven_adc10(&mut self) -> DIVEN_ADC10_W { DIVEN_ADC10_W { w: self } } #[doc = "Bits 18:23 - Divider clk ADC10"] #[inline(always)] pub fn div_adc10(&mut self) -> DIV_ADC10_W { DIV_ADC10_W { w: self } } #[doc = "Bit 24 - Enable clk ADC11"] #[inline(always)] pub fn clken_adc11(&mut self) -> CLKEN_ADC11_W { CLKEN_ADC11_W { w: self } } #[doc = "Bit 25 - Enable divider clk ADC11"] #[inline(always)] pub fn diven_adc11(&mut self) -> DIVEN_ADC11_W { DIVEN_ADC11_W { w: self } } #[doc = "Bits 26:31 - Divider clk ADC11"] #[inline(always)] pub fn div_adc11(&mut self) -> DIV_ADC11_W { DIV_ADC11_W { w: self } } }