[−][src]Module k1921vk01t_pac::nt_common_reg
Common block registers
Modules
| adc_ctrl0 | ADC 0-3 clock control register |
| adc_ctrl1 | ADC 4-7 clock control register |
| adc_ctrl2 | ADC control register 2 |
| apb_clk | Peripheral clock control register |
| ext_mem_cfg | External memory configuration register |
| flash_full_erase | Full erase flash (user and boot) register |
| gpioden0 | Port A,B digital enable register |
| gpioden1 | Port C,D digital enable register |
| gpioden2 | Port E,F digital enable register |
| gpioden3 | Port G,H digital enable register |
| gpiodena | Port A digital enable register |
| gpiodenb | Port B digital enable register |
| gpiodenc | Port C digital enable register |
| gpiodend | Port D digital enable register |
| gpiodene | Port E digital enable register |
| gpiodenf | Port F digital enable register |
| gpiodeng | Port G digital enable register |
| gpiodenh | Port H digital enable register |
| gpiodsctl0 | Port A,B strength control register |
| gpiodsctl1 | Port C,D strength control register |
| gpiodsctl2 | Port E,F strength control register |
| gpiodsctl3 | Port G,H strength control register |
| gpiodsctla | Port A strength control register |
| gpiodsctlb | Port B strength control register |
| gpiodsctlc | Port C strength control register |
| gpiodsctld | Port D strength control register |
| gpiodsctle | Port E strength control register |
| gpiodsctlf | Port F strength control register |
| gpiodsctlg | Port G strength control register |
| gpiodsctlh | Port H strength control register |
| gpioodctl0 | Port A,B open-drain enable register |
| gpioodctl1 | Port C,D open-drain enable register |
| gpioodctl2 | Port E,F open-drain enable register |
| gpioodctl3 | Port G,H open-drain enable register |
| gpioodctla | Port A open-drain enable register |
| gpioodctlb | Port B open-drain enable register |
| gpioodctlc | Port C open-drain enable register |
| gpioodctld | Port D open-drain enable register |
| gpioodctle | Port E open-drain enable register |
| gpioodctlf | Port F open-drain enable register |
| gpioodctlg | Port G open-drain enable register |
| gpioodctlh | Port H open-drain enable register |
| gpiopctla | Port A alternative function selection register |
| gpiopctlb | Port B alternative function selection register |
| gpiopctlc | Port C alternative function selection register |
| gpiopctld | Port D alternative function selection register |
| gpiopctle | Port E alternative function selection register |
| gpiopctlf | Port F alternative function selection register |
| gpiopctlg | Port G alternative function selection register |
| gpiopctlh | Port H alternative function selection register |
| gpiopuctl0 | Port A,B pull-up enable register |
| gpiopuctl1 | Port C,D pull-up enable register |
| gpiopuctl2 | Port E,F pull-up enable register |
| gpiopuctl3 | Port G,H pull-up enable register |
| gpiopuctla | Port A pull-up enable register |
| gpiopuctlb | Port B pull-up enable register |
| gpiopuctlc | Port C pull-up enable register |
| gpiopuctld | Port D pull-up enable register |
| gpiopuctle | Port E pull-up enable register |
| gpiopuctlf | Port F pull-up enable register |
| gpiopuctlg | Port G pull-up enable register |
| gpiopuctlh | Port H pull-up enable register |
| gpioqe0 | Register filter settings input ports A, B |
| gpioqe1 | Register filter settings input ports C, D |
| gpioqe2 | Register filter settings input ports E, F |
| gpioqe3 | Register filter settings input ports G, H |
| gpioqm0 | Register filter settings input ports A, B |
| gpioqm1 | Register filter settings input ports C, D |
| gpioqm2 | Register filter settings input ports E, F |
| gpioqm3 | Register filter settings input ports G, H |
| gpioqpad | Register filter settings input ports A, B, C, D |
| gpioqpeh | Register filter settings input ports E, F, G, H |
| gpiose0 | Control register resynchronization input ports A, B |
| gpiose1 | Control register resynchronization input ports C, D |
| gpiose2 | Control register resynchronization input ports E, F |
| gpiose3 | Control register resynchronization input ports G, H |
| per_rst0 | Peripheral reset register 0 |
| per_rst1 | Peripheral reset register 1 |
| pll_ctrl | PLL control register |
| pll_nf | PLL feedback divider register |
| pll_nr | PLL reference divider register |
| pll_od | PLL output divider register |
| pwm_ctrl | PWM sync control register |
| pwm_sync | PWM prescalers sync register |
| spi_clk | SPI clock control register |
| sys_clk | System clock control register |
| uart_clk | UART clock control register |
| uart_spi_clk_sel | Select source clk UART and SSP register |
| usb_ctrl | Customize the USB PHY |
Structs
| RegisterBlock | Register block |
Type Definitions
| ADC_CTRL0 | ADC 0-3 clock control register |
| ADC_CTRL1 | ADC 4-7 clock control register |
| ADC_CTRL2 | ADC control register 2 |
| APB_CLK | Peripheral clock control register |
| EXT_MEM_CFG | External memory configuration register |
| FLASH_FULL_ERASE | Full erase flash (user and boot) register |
| GPIODEN0 | Port A,B digital enable register |
| GPIODEN1 | Port C,D digital enable register |
| GPIODEN2 | Port E,F digital enable register |
| GPIODEN3 | Port G,H digital enable register |
| GPIODENA | Port A digital enable register |
| GPIODENB | Port B digital enable register |
| GPIODENC | Port C digital enable register |
| GPIODEND | Port D digital enable register |
| GPIODENE | Port E digital enable register |
| GPIODENF | Port F digital enable register |
| GPIODENG | Port G digital enable register |
| GPIODENH | Port H digital enable register |
| GPIODSCTL0 | Port A,B strength control register |
| GPIODSCTL1 | Port C,D strength control register |
| GPIODSCTL2 | Port E,F strength control register |
| GPIODSCTL3 | Port G,H strength control register |
| GPIODSCTLA | Port A strength control register |
| GPIODSCTLB | Port B strength control register |
| GPIODSCTLC | Port C strength control register |
| GPIODSCTLD | Port D strength control register |
| GPIODSCTLE | Port E strength control register |
| GPIODSCTLF | Port F strength control register |
| GPIODSCTLG | Port G strength control register |
| GPIODSCTLH | Port H strength control register |
| GPIOODCTL0 | Port A,B open-drain enable register |
| GPIOODCTL1 | Port C,D open-drain enable register |
| GPIOODCTL2 | Port E,F open-drain enable register |
| GPIOODCTL3 | Port G,H open-drain enable register |
| GPIOODCTLA | Port A open-drain enable register |
| GPIOODCTLB | Port B open-drain enable register |
| GPIOODCTLC | Port C open-drain enable register |
| GPIOODCTLD | Port D open-drain enable register |
| GPIOODCTLE | Port E open-drain enable register |
| GPIOODCTLF | Port F open-drain enable register |
| GPIOODCTLG | Port G open-drain enable register |
| GPIOODCTLH | Port H open-drain enable register |
| GPIOPCTLA | Port A alternative function selection register |
| GPIOPCTLB | Port B alternative function selection register |
| GPIOPCTLC | Port C alternative function selection register |
| GPIOPCTLD | Port D alternative function selection register |
| GPIOPCTLE | Port E alternative function selection register |
| GPIOPCTLF | Port F alternative function selection register |
| GPIOPCTLG | Port G alternative function selection register |
| GPIOPCTLH | Port H alternative function selection register |
| GPIOPUCTL0 | Port A,B pull-up enable register |
| GPIOPUCTL1 | Port C,D pull-up enable register |
| GPIOPUCTL2 | Port E,F pull-up enable register |
| GPIOPUCTL3 | Port G,H pull-up enable register |
| GPIOPUCTLA | Port A pull-up enable register |
| GPIOPUCTLB | Port B pull-up enable register |
| GPIOPUCTLC | Port C pull-up enable register |
| GPIOPUCTLD | Port D pull-up enable register |
| GPIOPUCTLE | Port E pull-up enable register |
| GPIOPUCTLF | Port F pull-up enable register |
| GPIOPUCTLG | Port G pull-up enable register |
| GPIOPUCTLH | Port H pull-up enable register |
| GPIOQE0 | Register filter settings input ports A, B |
| GPIOQE1 | Register filter settings input ports C, D |
| GPIOQE2 | Register filter settings input ports E, F |
| GPIOQE3 | Register filter settings input ports G, H |
| GPIOQM0 | Register filter settings input ports A, B |
| GPIOQM1 | Register filter settings input ports C, D |
| GPIOQM2 | Register filter settings input ports E, F |
| GPIOQM3 | Register filter settings input ports G, H |
| GPIOQPAD | Register filter settings input ports A, B, C, D |
| GPIOQPEH | Register filter settings input ports E, F, G, H |
| GPIOSE0 | Control register resynchronization input ports A, B |
| GPIOSE1 | Control register resynchronization input ports C, D |
| GPIOSE2 | Control register resynchronization input ports E, F |
| GPIOSE3 | Control register resynchronization input ports G, H |
| PER_RST0 | Peripheral reset register 0 |
| PER_RST1 | Peripheral reset register 1 |
| PLL_CTRL | PLL control register |
| PLL_NF | PLL feedback divider register |
| PLL_NR | PLL reference divider register |
| PLL_OD | PLL output divider register |
| PWM_CTRL | PWM sync control register |
| PWM_SYNC | PWM prescalers sync register |
| SPI_CLK | SPI clock control register |
| SYS_CLK | System clock control register |
| UART_CLK | UART clock control register |
| UART_SPI_CLK_SEL | Select source clk UART and SSP register |
| USB_CTRL | Customize the USB PHY |