[][src]Type Definition k1921vk01t_pac::nt_adc::isc::W

type W = W<u32, ISC>;

Writer for register ISC

Methods

impl W[src]

pub fn in0(&mut self) -> IN0_W[src]

Bit 0 - Sequencer 0 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in1(&mut self) -> IN1_W[src]

Bit 1 - Sequencer 1 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in2(&mut self) -> IN2_W[src]

Bit 2 - Sequencer 2 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in3(&mut self) -> IN3_W[src]

Bit 3 - Sequencer 3 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in4(&mut self) -> IN4_W[src]

Bit 4 - Sequencer 4 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in5(&mut self) -> IN5_W[src]

Bit 5 - Sequencer 5 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in6(&mut self) -> IN6_W[src]

Bit 6 - Sequencer 6 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn in7(&mut self) -> IN7_W[src]

Bit 7 - Sequencer 7 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin0(&mut self) -> DCIN0_W[src]

Bit 8 - DCMP 0 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin1(&mut self) -> DCIN1_W[src]

Bit 9 - DCMP 1 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin2(&mut self) -> DCIN2_W[src]

Bit 10 - DCMP 2 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin3(&mut self) -> DCIN3_W[src]

Bit 11 - DCMP 3 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin4(&mut self) -> DCIN4_W[src]

Bit 12 - DCMP 4 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin5(&mut self) -> DCIN5_W[src]

Bit 13 - DCMP 5 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin6(&mut self) -> DCIN6_W[src]

Bit 14 - DCMP 6 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin7(&mut self) -> DCIN7_W[src]

Bit 15 - DCMP 7 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin8(&mut self) -> DCIN8_W[src]

Bit 16 - DCMP 8 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin9(&mut self) -> DCIN9_W[src]

Bit 17 - DCMP 9 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin10(&mut self) -> DCIN10_W[src]

Bit 18 - DCMP 10 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin11(&mut self) -> DCIN11_W[src]

Bit 19 - DCMP 11 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin12(&mut self) -> DCIN12_W[src]

Bit 20 - DCMP 12 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin13(&mut self) -> DCIN13_W[src]

Bit 21 - DCMP 13 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin14(&mut self) -> DCIN14_W[src]

Bit 22 - DCMP 14 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin15(&mut self) -> DCIN15_W[src]

Bit 23 - DCMP 15 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin16(&mut self) -> DCIN16_W[src]

Bit 24 - DCMP 16 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin17(&mut self) -> DCIN17_W[src]

Bit 25 - DCMP 17 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin18(&mut self) -> DCIN18_W[src]

Bit 26 - DCMP 18 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin19(&mut self) -> DCIN19_W[src]

Bit 27 - DCMP 19 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin20(&mut self) -> DCIN20_W[src]

Bit 28 - DCMP 20 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin21(&mut self) -> DCIN21_W[src]

Bit 29 - DCMP 21 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin22(&mut self) -> DCIN22_W[src]

Bit 30 - DCMP 22 masked interrupt status / Write 1 to clear (also clear raw status)

pub fn dcin23(&mut self) -> DCIN23_W[src]

Bit 31 - DCMP 23 masked interrupt status / Write 1 to clear (also clear raw status)