Expand description
RISC-V instruction set support for the JIT assembler.
This module provides RISC-V specific instruction encoding and a macro-based DSL for generating RISC-V machine code at runtime.
Re-exports§
pub use instruction::Register;pub use instruction::Csr;pub use instruction::Instruction;pub use instruction::reg;pub use instruction::csr;pub use builder::Riscv64InstructionBuilder;