jh71xx_hal/gpio/
functions.rs

1//! GPIO function multiplexer (FMUX)
2
3pub trait Function {
4    const GROUP: GpioGroup;
5    const INDEX: u8;
6}
7
8/// Represents the GPIO signal group for configurable functions.
9#[repr(u8)]
10#[derive(Clone, Copy, Debug, Default, PartialEq)]
11pub enum GpioGroup {
12    #[default]
13    Gpo,
14    Gpen,
15    Gpi,
16    AonGpo,
17    AonGpen,
18    AonGpi,
19}
20
21impl GpioGroup {
22    /// Creates a new [GpioGroup].
23    pub const fn new() -> Self {
24        Self::Gpo
25    }
26}
27
28/// Configurable GPO function indices.
29///
30/// GPO (DOUT) function signals can be configured for GPIO pins 0-63.
31pub struct GpoFunction;
32
33impl GpoFunction {
34    pub const U0_WAVE511_O_UART_TXSOUT: u8 = 2;
35    pub const U0_CAN_CTRL_STBY: u8 = 3;
36    pub const U0_CAN_CTRL_TST_NEXT_BIT: u8 = 4;
37    pub const U0_CAN_CTRL_TST_SAMPLE_POINT: u8 = 5;
38    pub const U0_CAN_CTRL_TXD: u8 = 6;
39    pub const U0_CDN_USB_DRIVE_VBUS_IO: u8 = 7;
40    pub const U0_CDNS_QSPI_CSN1: u8 = 8;
41    pub const U0_CDNS_SPDIF_SPDIFO: u8 = 9;
42    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT: u8 = 10;
43    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT: u8 = 11;
44    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT: u8 = 12;
45    pub const U0_DSKIT_WDT_WDOGRES: u8 = 13;
46    pub const U0_DW_I2C_IC_CLK_OUT_A: u8 = 14;
47    pub const U0_DW_I2C_IC_DATA_OUT_A: u8 = 15;
48    pub const U0_DW_SDIO_BACK_END_POWER: u8 = 16;
49    pub const U0_DW_SDIO_CARD_POWER_EN: u8 = 17;
50    pub const U0_DW_SDIO_CCMD_OD_PULLUP_EN_N: u8 = 18;
51    pub const U0_DW_SDIO_RST_N: u8 = 19;
52    pub const U0_DW_UART_SOUT: u8 = 20;
53    pub const U0_HIFI4_JTDO: u8 = 21;
54    pub const U0_JTAG_CERTIFICATION_TDO: u8 = 22;
55    pub const U0_PDM_4MIC_DMIC_MCLK: u8 = 23;
56    pub const U0_PWM_8CH_PTC_PWM_0: u8 = 24;
57    pub const U0_PWM_8CH_PTC_PWM_1: u8 = 25;
58    pub const U0_PWM_8CH_PTC_PWM_2: u8 = 26;
59    pub const U0_PWM_8CH_PTC_PWM_3: u8 = 27;
60    pub const U0_PWMDAC_PWMDAC_LEFT_OUTPUT: u8 = 28;
61    pub const U0_PWMDAC_PWMDAC_RIGHT_OUTPUT: u8 = 29;
62    pub const U0_SSP_SPI_SSPCLKOUT: u8 = 30;
63    pub const U0_SSP_SPI_SSPFSSOUT: u8 = 31;
64    pub const U0_SSP_SPI_SSPTXD: u8 = 32;
65    pub const U0_SYS_CRG_CLK_GMAC_PHY: u8 = 33;
66    pub const U0_SYS_CRG_I2SRX_BCLK_MST: u8 = 34;
67    pub const U0_SYS_CRG_I2SRX_LRCK_MST: u8 = 35;
68    pub const U0_SYS_CRG_I2STX_BCLK_MST: u8 = 36;
69    pub const U0_SYS_CRG_I2STX_LRCK_MST: u8 = 37;
70    pub const U0_SYS_CRG_MCLK_OUT: u8 = 38;
71    pub const U0_SYS_CRG_TDM_CLK_MST: u8 = 39;
72    pub const U0_TDM16SLOT_PCM_SYNCOUT: u8 = 40;
73    pub const U0_TDM16SLOT_PCM_TXD: u8 = 41;
74    pub const U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0: u8 = 42;
75    pub const U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1: u8 = 43;
76    pub const U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2: u8 = 44;
77    pub const U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3: u8 = 45;
78    pub const U0_U7MC_SFT7110_TRACE_COM_PIB_TREF: u8 = 46;
79    pub const U1_CAN_CTRL_STBY: u8 = 47;
80    pub const U1_CAN_CTRL_TST_NEXT_BIT: u8 = 48;
81    pub const U1_CAN_CTRL_TST_SAMPLE_POINT: u8 = 49;
82    pub const U1_CAN_CTRL_TXD: u8 = 50;
83    pub const U1_DW_I2C_IC_CLK_OUT_A: u8 = 51;
84    pub const U1_DW_I2C_IC_DATA_OUT_A: u8 = 52;
85    pub const U1_DW_SDIO_BACK_END_POWER: u8 = 53;
86    pub const U1_DW_SDIO_CARD_POWER_EN: u8 = 54;
87    pub const U1_DW_SDIO_CCLK_OUT: u8 = 55;
88    pub const U1_DW_SDIO_CCMD_OD_PULLUP_EN_N: u8 = 56;
89    pub const U1_DW_SDIO_CCMD_OUT: u8 = 57;
90    pub const U1_DW_SDIO_CDATA_OUT_0: u8 = 58;
91    pub const U1_DW_SDIO_CDATA_OUT_1: u8 = 59;
92    pub const U1_DW_SDIO_CDATA_OUT_2: u8 = 60;
93    pub const U1_DW_SDIO_CDATA_OUT_3: u8 = 61;
94    pub const U1_DW_SDIO_CDATA_OUT_4: u8 = 62;
95    pub const U1_DW_SDIO_CDATA_OUT_5: u8 = 63;
96    pub const U1_DW_SDIO_CDATA_OUT_6: u8 = 64;
97    pub const U1_DW_SDIO_CDATA_OUT_7: u8 = 65;
98    pub const U1_DW_SDIO_RST_N: u8 = 66;
99    pub const U1_DW_UART_RTS_N: u8 = 67;
100    pub const U1_DW_UART_SOUT: u8 = 68;
101    pub const U1_I2STX_4CH_SDO0: u8 = 69;
102    pub const U1_I2STX_4CH_SDO1: u8 = 70;
103    pub const U1_I2STX_4CH_SDO2: u8 = 71;
104    pub const U1_I2STX_4CH_SDO3: u8 = 72;
105    pub const U1_SSP_SPI_SSPCLKOUT: u8 = 73;
106    pub const U1_SSP_SPI_SSPFSSOUT: u8 = 74;
107    pub const U1_SSP_SPI_SSPTXD: u8 = 75;
108    pub const U2_DW_I2C_IC_CLK_OUT_A: u8 = 76;
109    pub const U2_DW_I2C_IC_DATA_OUT_A: u8 = 77;
110    pub const U2_DW_UART_RTS_N: u8 = 78;
111    pub const U2_DW_UART_SOUT: u8 = 79;
112    pub const U2_SSP_SPI_SSPCLKOUT: u8 = 80;
113    pub const U2_SSP_SPI_SSPFSSOUT: u8 = 81;
114    pub const U2_SSP_SPI_SSPTXD: u8 = 82;
115    pub const U3_DW_I2C_IC_CLK_OUT_A: u8 = 83;
116    pub const U3_DW_I2C_IC_DATA_OUT_A: u8 = 84;
117    pub const U3_DW_UART_SOUT: u8 = 85;
118    pub const U3_SSP_SPI_SSPCLKOUT: u8 = 86;
119    pub const U3_SSP_SPI_SSPFSSOUT: u8 = 87;
120    pub const U3_SSP_SPI_SSPTXD: u8 = 88;
121    pub const U4_DW_I2C_IC_CLK_OUT_A: u8 = 89;
122    pub const U4_DW_I2C_IC_DATA_OUT_A: u8 = 90;
123    pub const U4_DW_UART_RTS_N: u8 = 91;
124    pub const U4_DW_UART_SOUT: u8 = 92;
125    pub const U4_SSP_SPI_SSPCLKOUT: u8 = 93;
126    pub const U4_SSP_SPI_SSPFSSOUT: u8 = 94;
127    pub const U4_SSP_SPI_SSPTXD: u8 = 95;
128    pub const U5_DW_I2C_IC_CLK_OUT_A: u8 = 96;
129    pub const U5_DW_I2C_IC_DATA_OUT_A: u8 = 97;
130    pub const U5_DW_UART_RTS_N: u8 = 98;
131    pub const U5_DW_UART_SOUT: u8 = 99;
132    pub const U5_SSP_SPI_SSPCLKOUT: u8 = 100;
133    pub const U5_SSP_SPI_SSPFSSOUT: u8 = 101;
134    pub const U5_SSP_SPI_SSPTXD: u8 = 102;
135    pub const U6_DW_I2C_IC_CLK_OUT_A: u8 = 103;
136    pub const U6_DW_I2C_IC_DATA_OUT_A: u8 = 104;
137    pub const U6_SSP_SPI_SSPCLKOUT: u8 = 105;
138    pub const U6_SSP_SPI_SSPFSSOUT: u8 = 106;
139    pub const U6_SSP_SPI_SSPTXD: u8 = 107;
140}
141
142/// Configurable GPEN function indices.
143///
144/// GPEN (DOEN) function signals can be configured for GPIO pins 0-63.
145pub struct GpenFunction;
146
147impl GpenFunction {
148    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN: u8 = 2;
149    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN: u8 = 3;
150    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN: u8 = 4;
151    pub const U0_DW_I2C_IC_CLK_OE: u8 = 5;
152    pub const U0_DW_I2C_IC_DATA_OE: u8 = 6;
153    pub const U0_HIFI4_JTDOEN: u8 = 7;
154    pub const U0_JTAG_CERTIFICATION_TDO_OE: u8 = 8;
155    pub const U0_PWM_8CH_PTC_OE_N_0: u8 = 9;
156    pub const U0_PWM_8CH_PTC_OE_N_1: u8 = 10;
157    pub const U0_PWM_8CH_PTC_OE_N_2: u8 = 11;
158    pub const U0_PWM_8CH_PTC_OE_N_3: u8 = 12;
159    pub const U0_SSP_SPI_NSSPCTLOE: u8 = 13;
160    pub const U0_SSP_SPI_NSSPOE: u8 = 14;
161    pub const U0_TDM16SLOT_NPCM_SYNCOE: u8 = 15;
162    pub const U0_TDM16SLOT_NPCM_TXDOE: u8 = 16;
163    pub const U1_DW_I2C_IC_CLK_OE: u8 = 17;
164    pub const U1_DW_I2C_IC_DATA_OE: u8 = 18;
165    pub const U1_DW_SDIO_CCMD_OUT_EN: u8 = 19;
166    pub const U1_DW_SDIO_CDATA_OUT_EN_0: u8 = 20;
167    pub const U1_DW_SDIO_CDATA_OUT_EN_1: u8 = 21;
168    pub const U1_DW_SDIO_CDATA_OUT_EN_2: u8 = 22;
169    pub const U1_DW_SDIO_CDATA_OUT_EN_3: u8 = 23;
170    pub const U1_DW_SDIO_CDATA_OUT_EN_4: u8 = 24;
171    pub const U1_DW_SDIO_CDATA_OUT_EN_5: u8 = 25;
172    pub const U1_DW_SDIO_CDATA_OUT_EN_6: u8 = 26;
173    pub const U1_DW_SDIO_CDATA_OUT_EN_7: u8 = 27;
174    pub const U1_SSP_SPI_NSSPCTLOE: u8 = 28;
175    pub const U1_SSP_SPI_NSSPOE: u8 = 29;
176    pub const U2_DW_I2C_IC_CLK_OE: u8 = 30;
177    pub const U2_DW_I2C_IC_DATA_OE: u8 = 31;
178    pub const U2_SSP_SPI_NSSPCTLOE: u8 = 32;
179    pub const U2_SSP_SPI_NSSPOE: u8 = 33;
180    pub const U3_DW_I2C_IC_CLK_OE: u8 = 34;
181    pub const U3_DW_I2C_IC_DATA_OE: u8 = 35;
182    pub const U3_SSP_SPI_NSSPCTLOE: u8 = 36;
183    pub const U3_SSP_SPI_NSSPOE: u8 = 37;
184    pub const U4_DW_I2C_IC_CLK_OE: u8 = 38;
185    pub const U4_DW_I2C_IC_DATA_OE: u8 = 39;
186    pub const U4_SSP_SPI_NSSPCTLOE: u8 = 40;
187    pub const U4_SSP_SPI_NSSPOE: u8 = 41;
188    pub const U5_DW_I2C_IC_CLK_OE: u8 = 42;
189    pub const U5_DW_I2C_IC_DATA_OE: u8 = 43;
190    pub const U5_SSP_SPI_NSSPCTLOE: u8 = 44;
191    pub const U5_SSP_SPI_NSSPOE: u8 = 45;
192    pub const U6_DW_I2C_IC_CLK_OE: u8 = 46;
193    pub const U6_DW_I2C_IC_DATA_OE: u8 = 47;
194    pub const U6_SSP_SPI_NSSPCTLOE: u8 = 48;
195    pub const U6_SSP_SPI_NSSPOE: u8 = 49;
196}
197
198/// Configurable GPEN function indices.
199///
200/// GPI function signals can be configured for GPIO pins 2-63 (GPIO0-GPIO1 are reserved).
201pub struct GpiFunction;
202
203impl GpiFunction {
204    pub const U0_WAVE511_I_UART_RXSIN: u8 = 0;
205    pub const U0_CAN_CTRL_RXD: u8 = 1;
206    pub const U0_CDN_USB_OVERCURRENT_N_IO: u8 = 2;
207    pub const U0_CDNS_SPDIF_SPDIFI: u8 = 3;
208    pub const U0_CLKRST_SRC_BYPASS_JTAG_TRSTN: u8 = 4;
209    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN: u8 = 5;
210    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN: u8 = 6;
211    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN: u8 = 7;
212    pub const U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD: u8 = 8;
213    pub const U0_DW_I2C_IC_CLK_IN_A: u8 = 9;
214    pub const U0_DW_I2C_IC_DATA_IN_A: u8 = 10;
215    pub const U0_DW_SDIO_CARD_DETECT_N: u8 = 11;
216    pub const U0_DW_SDIO_CARD_INT_N: u8 = 12;
217    pub const U0_DW_SDIO_CARD_WRITE_PRT: u8 = 13;
218    pub const U0_DW_UART_SIN: u8 = 14;
219    pub const U0_HIFI4_JTCK: u8 = 15;
220    pub const U0_HIFI4_JTDI: u8 = 16;
221    pub const U0_HIFI4_JTMS: u8 = 17;
222    pub const U0_HIFI4_JTRSTN: u8 = 18;
223    pub const U0_JTAG_CERTIFICATION_TDI: u8 = 19;
224    pub const U0_JTAG_CERTIFICATION_TMS: u8 = 20;
225    pub const U0_PDM_4MIC_DMIC0_DIN: u8 = 21;
226    pub const U0_PDM_4MIC_DMIC1_DIN: u8 = 22;
227    pub const U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0: u8 = 23;
228    pub const U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1: u8 = 24;
229    pub const U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2: u8 = 25;
230    pub const U0_SSP_SPI_SSPCLKIN: u8 = 26;
231    pub const U0_SSP_SPI_SSPFSSIN: u8 = 27;
232    pub const U0_SSP_SPI_SSPRXD: u8 = 28;
233    pub const U0_SYS_CRG_CLK_JTAG_TCK: u8 = 29;
234    pub const U0_SYS_CRG_EXT_MCLK: u8 = 30;
235    pub const U0_SYS_CRG_I2SRX_BCLK_SLV: u8 = 31;
236    pub const U0_SYS_CRG_I2SRX_LRCK_SLV: u8 = 32;
237    pub const U0_SYS_CRG_I2STX_BCLK_SLV: u8 = 33;
238    pub const U0_SYS_CRG_I2STX_LRCK_SLV: u8 = 34;
239    pub const U0_SYS_CRG_TDM_CLK_SLV: u8 = 35;
240    pub const U0_TDM16SLOT_PCM_RXD: u8 = 36;
241    pub const U0_TDM16SLOT_PCM_SYNCIN: u8 = 37;
242    pub const U1_CAN_CTRL_RXD: u8 = 38;
243    pub const U1_DW_I2C_IC_CLK_IN_A: u8 = 39;
244    pub const U1_DW_I2C_IC_DATA_IN_A: u8 = 40;
245    pub const U1_DW_SDIO_CARD_DETECT_N: u8 = 41;
246    pub const U1_DW_SDIO_CARD_INT_N: u8 = 42;
247    pub const U1_DW_SDIO_CARD_WRITE_PRT: u8 = 43;
248    pub const U1_DW_SDIO_CCMD_IN: u8 = 44;
249    pub const U1_DW_SDIO_CDATA_IN_0: u8 = 45;
250    pub const U1_DW_SDIO_CDATA_IN_1: u8 = 46;
251    pub const U1_DW_SDIO_CDATA_IN_2: u8 = 47;
252    pub const U1_DW_SDIO_CDATA_IN_3: u8 = 48;
253    pub const U1_DW_SDIO_CDATA_IN_4: u8 = 49;
254    pub const U1_DW_SDIO_CDATA_IN_5: u8 = 50;
255    pub const U1_DW_SDIO_CDATA_IN_6: u8 = 51;
256    pub const U1_DW_SDIO_CDATA_IN_7: u8 = 52;
257    pub const U1_DW_SDIO_DATA_STROBE: u8 = 53;
258    pub const U1_DW_UART_CTS_N: u8 = 54;
259    pub const U1_DW_UART_SIN: u8 = 55;
260    pub const U1_SSP_SPI_SSPCLKIN: u8 = 56;
261    pub const U1_SSP_SPI_SSPFSSIN: u8 = 57;
262    pub const U1_SSP_SPI_SSPRXD: u8 = 58;
263    pub const U2_DW_I2C_IC_CLK_IN_A: u8 = 59;
264    pub const U2_DW_I2C_IC_DATA_IN_A: u8 = 60;
265    pub const U2_DW_UART_CTS_N: u8 = 61;
266    pub const U2_DW_UART_SIN: u8 = 62;
267    pub const U2_SSP_SPI_SSPCLKIN: u8 = 63;
268    pub const U2_SSP_SPI_SSPFSSIN: u8 = 64;
269    pub const U2_SSP_SPI_SSPRXD: u8 = 65;
270    pub const U3_DW_I2C_IC_CLK_IN_A: u8 = 66;
271    pub const U3_DW_I2C_IC_DATA_IN_A: u8 = 67;
272    pub const U3_DW_UART_SIN: u8 = 68;
273    pub const U3_SSP_SPI_SSPCLKIN: u8 = 69;
274    pub const U3_SSP_SPI_SSPFSSIN: u8 = 70;
275    pub const U3_SSP_SPI_SSPRXD: u8 = 71;
276    pub const U4_DW_I2C_IC_CLK_IN_A: u8 = 72;
277    pub const U4_DW_I2C_IC_DATA_IN_A: u8 = 73;
278    pub const U4_DW_UART_CTS_N: u8 = 74;
279    pub const U4_DW_UART_SIN: u8 = 75;
280    pub const U4_SSP_SPI_SSPCLKIN: u8 = 76;
281    pub const U4_SSP_SPI_SSPFSSIN: u8 = 77;
282    pub const U4_SSP_SPI_SSPRXD: u8 = 78;
283    pub const U5_DW_I2C_IC_CLK_IN_A: u8 = 79;
284    pub const U5_DW_I2C_IC_DATA_IN_A: u8 = 80;
285    pub const U5_DW_UART_CTS_N: u8 = 81;
286    pub const U5_DW_UART_SIN: u8 = 82;
287    pub const U5_SSP_SPI_SSPCLKIN: u8 = 83;
288    pub const U5_SSP_SPI_SSPFSSIN: u8 = 84;
289    pub const U5_SSP_SPI_SSPRXD: u8 = 85;
290    pub const U6_DW_I2C_IC_CLK_IN_A: u8 = 86;
291    pub const U6_DW_I2C_IC_DATA_IN_A: u8 = 87;
292    pub const U6_SSP_SPI_SSPCLKIN: u8 = 88;
293    pub const U6_SSP_SPI_SSPFSSIN: u8 = 89;
294    pub const U6_SSP_SPI_SSPRXD: u8 = 90;
295}
296
297/// Configurable AON GPO function indices.
298///
299/// AON GPO (Always-on DOUT) function signals can be configured for GPIO pins 0-63.
300pub struct AonGpoFunction;
301
302impl AonGpoFunction {
303    pub const U0_AON_CRG_CLK_32K_OUT: u8 = 2;
304    pub const U0_PWM_8CH_PTC_PWM_4: u8 = 3;
305    pub const U0_PWM_8CH_PTC_PWM_5: u8 = 4;
306    pub const U0_PWM_8CH_PTC_PWM_6: u8 = 5;
307    pub const U0_PWM_8CH_PTC_PWM_7: u8 = 6;
308    pub const U0_SYS_CRG_CLK_GCLK0: u8 = 7;
309    pub const U0_SYS_CRG_CLK_GCLK1: u8 = 8;
310    pub const U0_SYS_CRG_CLK_GCLK2: u8 = 9;
311}
312
313/// Configurable AON GPEN function indices.
314///
315/// AON GPEN (Always-on DOEN) function signals can be configured for GPIO pins 0-63.
316pub struct AonGpenFunction;
317
318impl AonGpenFunction {
319    pub const U0_PWM_8CH_PTC_OE_N_4: u8 = 2;
320    pub const U0_PWM_8CH_PTC_OE_N_5: u8 = 3;
321    pub const U0_PWM_8CH_PTC_OE_N_6: u8 = 4;
322    pub const U0_PWM_8CH_PTC_OE_N_7: u8 = 5;
323}
324
325/// Configurable AON GPI function indices.
326///
327/// AON GPI (Always-on DIN) function signals can be configured for GPIO pins 2-63 (GPIO0-GPIO1 are reserved).
328pub struct AonGpiFunction;
329
330impl AonGpiFunction {
331    pub const U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0: u8 = 0;
332    pub const U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1: u8 = 1;
333    pub const U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2: u8 = 2;
334    pub const U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3: u8 = 3;
335}
jh71xx_hal/gpio/functions.rs

jh71xx_hal/gpio/
functions.rs
