jh7110_vf2_13b_pac/sys_syscon/
sys_syscfg_33.rs

1#[doc = "Register `sys_syscfg_33` reader"]
2pub type R = crate::R<SYS_SYSCFG_33_SPEC>;
3#[doc = "Register `sys_syscfg_33` writer"]
4pub type W = crate::W<SYS_SYSCFG_33_SPEC>;
5#[doc = "Field `reset_vector_4_32` reader - U0 U74MC Reset Vector 4: 32"]
6pub type RESET_VECTOR_4_32_R = crate::BitReader;
7#[doc = "Field `reset_vector_4_32` writer - U0 U74MC Reset Vector 4: 32"]
8pub type RESET_VECTOR_4_32_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `reset_vector_4_33` reader - U0 U74MC Reset Vector 4: 33"]
10pub type RESET_VECTOR_4_33_R = crate::BitReader;
11#[doc = "Field `reset_vector_4_33` writer - U0 U74MC Reset Vector 4: 33"]
12pub type RESET_VECTOR_4_33_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `reset_vector_4_34` reader - U0 U74MC Reset Vector 4: 34"]
14pub type RESET_VECTOR_4_34_R = crate::BitReader;
15#[doc = "Field `reset_vector_4_34` writer - U0 U74MC Reset Vector 4: 34"]
16pub type RESET_VECTOR_4_34_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `reset_vector_4_35` reader - U0 U74MC Reset Vector 4: 35"]
18pub type RESET_VECTOR_4_35_R = crate::BitReader;
19#[doc = "Field `reset_vector_4_35` writer - U0 U74MC Reset Vector 4: 35"]
20pub type RESET_VECTOR_4_35_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `u0_suppress_fetch_1` reader - u0_suppress_fetch_1"]
22pub type U0_SUPPRESS_FETCH_1_R = crate::BitReader;
23#[doc = "Field `u0_suppress_fetch_1` writer - u0_suppress_fetch_1"]
24pub type U0_SUPPRESS_FETCH_1_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `u0_suppress_fetch_2` reader - u0_suppress_fetch_2"]
26pub type U0_SUPPRESS_FETCH_2_R = crate::BitReader;
27#[doc = "Field `u0_suppress_fetch_2` writer - u0_suppress_fetch_2"]
28pub type U0_SUPPRESS_FETCH_2_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `u0_suppress_fetch_3` reader - u0_suppress_fetch_3"]
30pub type U0_SUPPRESS_FETCH_3_R = crate::BitReader;
31#[doc = "Field `u0_suppress_fetch_3` writer - u0_suppress_fetch_3"]
32pub type U0_SUPPRESS_FETCH_3_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `u0_suppress_fetch_4` reader - u0_suppress_fetch_4"]
34pub type U0_SUPPRESS_FETCH_4_R = crate::BitReader;
35#[doc = "Field `u0_suppress_fetch_4` writer - u0_suppress_fetch_4"]
36pub type U0_SUPPRESS_FETCH_4_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `u0_wfi_from_tile_0` reader - u0_wfi_from_tile_0"]
38pub type U0_WFI_FROM_TILE_0_R = crate::BitReader;
39#[doc = "Field `u0_wfi_from_tile_0` writer - u0_wfi_from_tile_0"]
40pub type U0_WFI_FROM_TILE_0_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `u0_wfi_from_tile_1` reader - u0_wfi_from_tile_1"]
42pub type U0_WFI_FROM_TILE_1_R = crate::BitReader;
43#[doc = "Field `u0_wfi_from_tile_1` writer - u0_wfi_from_tile_1"]
44pub type U0_WFI_FROM_TILE_1_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `u0_wfi_from_tile_2` reader - u0_wfi_from_tile_2"]
46pub type U0_WFI_FROM_TILE_2_R = crate::BitReader;
47#[doc = "Field `u0_wfi_from_tile_2` writer - u0_wfi_from_tile_2"]
48pub type U0_WFI_FROM_TILE_2_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `u0_wfi_from_tile_3` reader - u0_wfi_from_tile_3"]
50pub type U0_WFI_FROM_TILE_3_R = crate::BitReader;
51#[doc = "Field `u0_wfi_from_tile_3` writer - u0_wfi_from_tile_3"]
52pub type U0_WFI_FROM_TILE_3_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `u0_wfi_from_tile_4` reader - u0_wfi_from_tile_4"]
54pub type U0_WFI_FROM_TILE_4_R = crate::BitReader;
55#[doc = "Field `u0_wfi_from_tile_4` writer - u0_wfi_from_tile_4"]
56pub type U0_WFI_FROM_TILE_4_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `u0_vdec_intsram_sram_config_slp` reader - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."]
58pub type U0_VDEC_INTSRAM_SRAM_CONFIG_SLP_R = crate::BitReader;
59#[doc = "Field `u0_vdec_intsram_sram_config_slp` writer - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."]
60pub type U0_VDEC_INTSRAM_SRAM_CONFIG_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `u0_vdec_intsram_sram_config_sd` reader - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."]
62pub type U0_VDEC_INTSRAM_SRAM_CONFIG_SD_R = crate::BitReader;
63#[doc = "Field `u0_vdec_intsram_sram_config_sd` writer - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."]
64pub type U0_VDEC_INTSRAM_SRAM_CONFIG_SD_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `u0_vdec_intsram_sram_config_rtsel` reader - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."]
66pub type U0_VDEC_INTSRAM_SRAM_CONFIG_RTSEL_R = crate::FieldReader;
67#[doc = "Field `u0_vdec_intsram_sram_config_rtsel` writer - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."]
68pub type U0_VDEC_INTSRAM_SRAM_CONFIG_RTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
69#[doc = "Field `u0_vdec_intsram_sram_config_ptsel` reader - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."]
70pub type U0_VDEC_INTSRAM_SRAM_CONFIG_PTSEL_R = crate::FieldReader;
71#[doc = "Field `u0_vdec_intsram_sram_config_ptsel` writer - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."]
72pub type U0_VDEC_INTSRAM_SRAM_CONFIG_PTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
73#[doc = "Field `u0_vdec_intsram_sram_config_trb` reader - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."]
74pub type U0_VDEC_INTSRAM_SRAM_CONFIG_TRB_R = crate::FieldReader;
75#[doc = "Field `u0_vdec_intsram_sram_config_trb` writer - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."]
76pub type U0_VDEC_INTSRAM_SRAM_CONFIG_TRB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
77#[doc = "Field `u0_vdec_intsram_sram_config_wtsel` reader - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."]
78pub type U0_VDEC_INTSRAM_SRAM_CONFIG_WTSEL_R = crate::FieldReader;
79#[doc = "Field `u0_vdec_intsram_sram_config_wtsel` writer - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."]
80pub type U0_VDEC_INTSRAM_SRAM_CONFIG_WTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
81#[doc = "Field `u0_vdec_intsram_sram_config_vs` reader - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."]
82pub type U0_VDEC_INTSRAM_SRAM_CONFIG_VS_R = crate::BitReader;
83#[doc = "Field `u0_vdec_intsram_sram_config_vs` writer - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."]
84pub type U0_VDEC_INTSRAM_SRAM_CONFIG_VS_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `u0_vdec_intsram_sram_config_vg` reader - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."]
86pub type U0_VDEC_INTSRAM_SRAM_CONFIG_VG_R = crate::BitReader;
87#[doc = "Field `u0_vdec_intsram_sram_config_vg` writer - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."]
88pub type U0_VDEC_INTSRAM_SRAM_CONFIG_VG_W<'a, REG> = crate::BitWriter<'a, REG>;
89impl R {
90    #[doc = "Bit 0 - U0 U74MC Reset Vector 4: 32"]
91    #[inline(always)]
92    pub fn reset_vector_4_32(&self) -> RESET_VECTOR_4_32_R {
93        RESET_VECTOR_4_32_R::new((self.bits & 1) != 0)
94    }
95    #[doc = "Bit 1 - U0 U74MC Reset Vector 4: 33"]
96    #[inline(always)]
97    pub fn reset_vector_4_33(&self) -> RESET_VECTOR_4_33_R {
98        RESET_VECTOR_4_33_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    #[doc = "Bit 2 - U0 U74MC Reset Vector 4: 34"]
101    #[inline(always)]
102    pub fn reset_vector_4_34(&self) -> RESET_VECTOR_4_34_R {
103        RESET_VECTOR_4_34_R::new(((self.bits >> 2) & 1) != 0)
104    }
105    #[doc = "Bit 3 - U0 U74MC Reset Vector 4: 35"]
106    #[inline(always)]
107    pub fn reset_vector_4_35(&self) -> RESET_VECTOR_4_35_R {
108        RESET_VECTOR_4_35_R::new(((self.bits >> 3) & 1) != 0)
109    }
110    #[doc = "Bit 4 - u0_suppress_fetch_1"]
111    #[inline(always)]
112    pub fn u0_suppress_fetch_1(&self) -> U0_SUPPRESS_FETCH_1_R {
113        U0_SUPPRESS_FETCH_1_R::new(((self.bits >> 4) & 1) != 0)
114    }
115    #[doc = "Bit 5 - u0_suppress_fetch_2"]
116    #[inline(always)]
117    pub fn u0_suppress_fetch_2(&self) -> U0_SUPPRESS_FETCH_2_R {
118        U0_SUPPRESS_FETCH_2_R::new(((self.bits >> 5) & 1) != 0)
119    }
120    #[doc = "Bit 6 - u0_suppress_fetch_3"]
121    #[inline(always)]
122    pub fn u0_suppress_fetch_3(&self) -> U0_SUPPRESS_FETCH_3_R {
123        U0_SUPPRESS_FETCH_3_R::new(((self.bits >> 6) & 1) != 0)
124    }
125    #[doc = "Bit 7 - u0_suppress_fetch_4"]
126    #[inline(always)]
127    pub fn u0_suppress_fetch_4(&self) -> U0_SUPPRESS_FETCH_4_R {
128        U0_SUPPRESS_FETCH_4_R::new(((self.bits >> 7) & 1) != 0)
129    }
130    #[doc = "Bit 8 - u0_wfi_from_tile_0"]
131    #[inline(always)]
132    pub fn u0_wfi_from_tile_0(&self) -> U0_WFI_FROM_TILE_0_R {
133        U0_WFI_FROM_TILE_0_R::new(((self.bits >> 8) & 1) != 0)
134    }
135    #[doc = "Bit 9 - u0_wfi_from_tile_1"]
136    #[inline(always)]
137    pub fn u0_wfi_from_tile_1(&self) -> U0_WFI_FROM_TILE_1_R {
138        U0_WFI_FROM_TILE_1_R::new(((self.bits >> 9) & 1) != 0)
139    }
140    #[doc = "Bit 10 - u0_wfi_from_tile_2"]
141    #[inline(always)]
142    pub fn u0_wfi_from_tile_2(&self) -> U0_WFI_FROM_TILE_2_R {
143        U0_WFI_FROM_TILE_2_R::new(((self.bits >> 10) & 1) != 0)
144    }
145    #[doc = "Bit 11 - u0_wfi_from_tile_3"]
146    #[inline(always)]
147    pub fn u0_wfi_from_tile_3(&self) -> U0_WFI_FROM_TILE_3_R {
148        U0_WFI_FROM_TILE_3_R::new(((self.bits >> 11) & 1) != 0)
149    }
150    #[doc = "Bit 12 - u0_wfi_from_tile_4"]
151    #[inline(always)]
152    pub fn u0_wfi_from_tile_4(&self) -> U0_WFI_FROM_TILE_4_R {
153        U0_WFI_FROM_TILE_4_R::new(((self.bits >> 12) & 1) != 0)
154    }
155    #[doc = "Bit 13 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."]
156    #[inline(always)]
157    pub fn u0_vdec_intsram_sram_config_slp(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_SLP_R {
158        U0_VDEC_INTSRAM_SRAM_CONFIG_SLP_R::new(((self.bits >> 13) & 1) != 0)
159    }
160    #[doc = "Bit 14 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."]
161    #[inline(always)]
162    pub fn u0_vdec_intsram_sram_config_sd(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_SD_R {
163        U0_VDEC_INTSRAM_SRAM_CONFIG_SD_R::new(((self.bits >> 14) & 1) != 0)
164    }
165    #[doc = "Bits 15:16 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."]
166    #[inline(always)]
167    pub fn u0_vdec_intsram_sram_config_rtsel(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_RTSEL_R {
168        U0_VDEC_INTSRAM_SRAM_CONFIG_RTSEL_R::new(((self.bits >> 15) & 3) as u8)
169    }
170    #[doc = "Bits 17:18 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."]
171    #[inline(always)]
172    pub fn u0_vdec_intsram_sram_config_ptsel(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_PTSEL_R {
173        U0_VDEC_INTSRAM_SRAM_CONFIG_PTSEL_R::new(((self.bits >> 17) & 3) as u8)
174    }
175    #[doc = "Bits 19:20 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."]
176    #[inline(always)]
177    pub fn u0_vdec_intsram_sram_config_trb(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_TRB_R {
178        U0_VDEC_INTSRAM_SRAM_CONFIG_TRB_R::new(((self.bits >> 19) & 3) as u8)
179    }
180    #[doc = "Bits 21:22 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."]
181    #[inline(always)]
182    pub fn u0_vdec_intsram_sram_config_wtsel(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_WTSEL_R {
183        U0_VDEC_INTSRAM_SRAM_CONFIG_WTSEL_R::new(((self.bits >> 21) & 3) as u8)
184    }
185    #[doc = "Bit 23 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."]
186    #[inline(always)]
187    pub fn u0_vdec_intsram_sram_config_vs(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_VS_R {
188        U0_VDEC_INTSRAM_SRAM_CONFIG_VS_R::new(((self.bits >> 23) & 1) != 0)
189    }
190    #[doc = "Bit 24 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."]
191    #[inline(always)]
192    pub fn u0_vdec_intsram_sram_config_vg(&self) -> U0_VDEC_INTSRAM_SRAM_CONFIG_VG_R {
193        U0_VDEC_INTSRAM_SRAM_CONFIG_VG_R::new(((self.bits >> 24) & 1) != 0)
194    }
195}
196impl W {
197    #[doc = "Bit 0 - U0 U74MC Reset Vector 4: 32"]
198    #[inline(always)]
199    #[must_use]
200    pub fn reset_vector_4_32(&mut self) -> RESET_VECTOR_4_32_W<SYS_SYSCFG_33_SPEC> {
201        RESET_VECTOR_4_32_W::new(self, 0)
202    }
203    #[doc = "Bit 1 - U0 U74MC Reset Vector 4: 33"]
204    #[inline(always)]
205    #[must_use]
206    pub fn reset_vector_4_33(&mut self) -> RESET_VECTOR_4_33_W<SYS_SYSCFG_33_SPEC> {
207        RESET_VECTOR_4_33_W::new(self, 1)
208    }
209    #[doc = "Bit 2 - U0 U74MC Reset Vector 4: 34"]
210    #[inline(always)]
211    #[must_use]
212    pub fn reset_vector_4_34(&mut self) -> RESET_VECTOR_4_34_W<SYS_SYSCFG_33_SPEC> {
213        RESET_VECTOR_4_34_W::new(self, 2)
214    }
215    #[doc = "Bit 3 - U0 U74MC Reset Vector 4: 35"]
216    #[inline(always)]
217    #[must_use]
218    pub fn reset_vector_4_35(&mut self) -> RESET_VECTOR_4_35_W<SYS_SYSCFG_33_SPEC> {
219        RESET_VECTOR_4_35_W::new(self, 3)
220    }
221    #[doc = "Bit 4 - u0_suppress_fetch_1"]
222    #[inline(always)]
223    #[must_use]
224    pub fn u0_suppress_fetch_1(&mut self) -> U0_SUPPRESS_FETCH_1_W<SYS_SYSCFG_33_SPEC> {
225        U0_SUPPRESS_FETCH_1_W::new(self, 4)
226    }
227    #[doc = "Bit 5 - u0_suppress_fetch_2"]
228    #[inline(always)]
229    #[must_use]
230    pub fn u0_suppress_fetch_2(&mut self) -> U0_SUPPRESS_FETCH_2_W<SYS_SYSCFG_33_SPEC> {
231        U0_SUPPRESS_FETCH_2_W::new(self, 5)
232    }
233    #[doc = "Bit 6 - u0_suppress_fetch_3"]
234    #[inline(always)]
235    #[must_use]
236    pub fn u0_suppress_fetch_3(&mut self) -> U0_SUPPRESS_FETCH_3_W<SYS_SYSCFG_33_SPEC> {
237        U0_SUPPRESS_FETCH_3_W::new(self, 6)
238    }
239    #[doc = "Bit 7 - u0_suppress_fetch_4"]
240    #[inline(always)]
241    #[must_use]
242    pub fn u0_suppress_fetch_4(&mut self) -> U0_SUPPRESS_FETCH_4_W<SYS_SYSCFG_33_SPEC> {
243        U0_SUPPRESS_FETCH_4_W::new(self, 7)
244    }
245    #[doc = "Bit 8 - u0_wfi_from_tile_0"]
246    #[inline(always)]
247    #[must_use]
248    pub fn u0_wfi_from_tile_0(&mut self) -> U0_WFI_FROM_TILE_0_W<SYS_SYSCFG_33_SPEC> {
249        U0_WFI_FROM_TILE_0_W::new(self, 8)
250    }
251    #[doc = "Bit 9 - u0_wfi_from_tile_1"]
252    #[inline(always)]
253    #[must_use]
254    pub fn u0_wfi_from_tile_1(&mut self) -> U0_WFI_FROM_TILE_1_W<SYS_SYSCFG_33_SPEC> {
255        U0_WFI_FROM_TILE_1_W::new(self, 9)
256    }
257    #[doc = "Bit 10 - u0_wfi_from_tile_2"]
258    #[inline(always)]
259    #[must_use]
260    pub fn u0_wfi_from_tile_2(&mut self) -> U0_WFI_FROM_TILE_2_W<SYS_SYSCFG_33_SPEC> {
261        U0_WFI_FROM_TILE_2_W::new(self, 10)
262    }
263    #[doc = "Bit 11 - u0_wfi_from_tile_3"]
264    #[inline(always)]
265    #[must_use]
266    pub fn u0_wfi_from_tile_3(&mut self) -> U0_WFI_FROM_TILE_3_W<SYS_SYSCFG_33_SPEC> {
267        U0_WFI_FROM_TILE_3_W::new(self, 11)
268    }
269    #[doc = "Bit 12 - u0_wfi_from_tile_4"]
270    #[inline(always)]
271    #[must_use]
272    pub fn u0_wfi_from_tile_4(&mut self) -> U0_WFI_FROM_TILE_4_W<SYS_SYSCFG_33_SPEC> {
273        U0_WFI_FROM_TILE_4_W::new(self, 12)
274    }
275    #[doc = "Bit 13 - SRAM/ROM configuration. SLP: sleep enable, high active, default is low."]
276    #[inline(always)]
277    #[must_use]
278    pub fn u0_vdec_intsram_sram_config_slp(
279        &mut self,
280    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_SLP_W<SYS_SYSCFG_33_SPEC> {
281        U0_VDEC_INTSRAM_SRAM_CONFIG_SLP_W::new(self, 13)
282    }
283    #[doc = "Bit 14 - SRAM/ROM configuration. SD: shutdown enable, high active, default is low."]
284    #[inline(always)]
285    #[must_use]
286    pub fn u0_vdec_intsram_sram_config_sd(
287        &mut self,
288    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_SD_W<SYS_SYSCFG_33_SPEC> {
289        U0_VDEC_INTSRAM_SRAM_CONFIG_SD_W::new(self, 14)
290    }
291    #[doc = "Bits 15:16 - SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01."]
292    #[inline(always)]
293    #[must_use]
294    pub fn u0_vdec_intsram_sram_config_rtsel(
295        &mut self,
296    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_RTSEL_W<SYS_SYSCFG_33_SPEC> {
297        U0_VDEC_INTSRAM_SRAM_CONFIG_RTSEL_W::new(self, 15)
298    }
299    #[doc = "Bits 17:18 - SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01."]
300    #[inline(always)]
301    #[must_use]
302    pub fn u0_vdec_intsram_sram_config_ptsel(
303        &mut self,
304    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_PTSEL_W<SYS_SYSCFG_33_SPEC> {
305        U0_VDEC_INTSRAM_SRAM_CONFIG_PTSEL_W::new(self, 17)
306    }
307    #[doc = "Bits 19:20 - SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01."]
308    #[inline(always)]
309    #[must_use]
310    pub fn u0_vdec_intsram_sram_config_trb(
311        &mut self,
312    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_TRB_W<SYS_SYSCFG_33_SPEC> {
313        U0_VDEC_INTSRAM_SRAM_CONFIG_TRB_W::new(self, 19)
314    }
315    #[doc = "Bits 21:22 - SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01."]
316    #[inline(always)]
317    #[must_use]
318    pub fn u0_vdec_intsram_sram_config_wtsel(
319        &mut self,
320    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_WTSEL_W<SYS_SYSCFG_33_SPEC> {
321        U0_VDEC_INTSRAM_SRAM_CONFIG_WTSEL_W::new(self, 21)
322    }
323    #[doc = "Bit 23 - SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1."]
324    #[inline(always)]
325    #[must_use]
326    pub fn u0_vdec_intsram_sram_config_vs(
327        &mut self,
328    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_VS_W<SYS_SYSCFG_33_SPEC> {
329        U0_VDEC_INTSRAM_SRAM_CONFIG_VS_W::new(self, 23)
330    }
331    #[doc = "Bit 24 - SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1."]
332    #[inline(always)]
333    #[must_use]
334    pub fn u0_vdec_intsram_sram_config_vg(
335        &mut self,
336    ) -> U0_VDEC_INTSRAM_SRAM_CONFIG_VG_W<SYS_SYSCFG_33_SPEC> {
337        U0_VDEC_INTSRAM_SRAM_CONFIG_VG_W::new(self, 24)
338    }
339    #[doc = r" Writes raw bits to the register."]
340    #[doc = r""]
341    #[doc = r" # Safety"]
342    #[doc = r""]
343    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
344    #[inline(always)]
345    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
346        self.bits = bits;
347        self
348    }
349}
350#[doc = "SYS SYSCONSAIF SYSCFG 132\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_syscfg_33::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_syscfg_33::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
351pub struct SYS_SYSCFG_33_SPEC;
352impl crate::RegisterSpec for SYS_SYSCFG_33_SPEC {
353    type Ux = u32;
354}
355#[doc = "`read()` method returns [`sys_syscfg_33::R`](R) reader structure"]
356impl crate::Readable for SYS_SYSCFG_33_SPEC {}
357#[doc = "`write(|w| ..)` method takes [`sys_syscfg_33::W`](W) writer structure"]
358impl crate::Writable for SYS_SYSCFG_33_SPEC {
359    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
360    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
361}
362#[doc = "`reset()` method sets sys_syscfg_33 to value 0"]
363impl crate::Resettable for SYS_SYSCFG_33_SPEC {
364    const RESET_VALUE: Self::Ux = 0;
365}
jh7110_vf2_13b_pac/sys_syscon/sys_syscfg_33.rs

jh7110_vf2_13b_pac/sys_syscon/
sys_syscfg_33.rs
