jh7110_vf2_13b_pac/uart2/
usr.rs

1#[doc = "Register `usr` reader"]
2pub type R = crate::R<USR_SPEC>;
3#[doc = "Register `usr` writer"]
4pub type W = crate::W<USR_SPEC>;
5#[doc = "Field `busy` reader - UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock."]
6pub type BUSY_R = crate::BitReader;
7#[doc = "Field `tfnf` reader - Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full."]
8pub type TFNF_R = crate::BitReader;
9#[doc = "Field `tfe` reader - Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty."]
10pub type TFE_R = crate::BitReader;
11#[doc = "Field `rfne` reader - Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty."]
12pub type RFNE_R = crate::BitReader;
13#[doc = "Field `rff` reader - Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full."]
14pub type RFF_R = crate::BitReader;
15impl R {
16    #[doc = "Bit 0 - UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock."]
17    #[inline(always)]
18    pub fn busy(&self) -> BUSY_R {
19        BUSY_R::new((self.bits & 1) != 0)
20    }
21    #[doc = "Bit 1 - Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full."]
22    #[inline(always)]
23    pub fn tfnf(&self) -> TFNF_R {
24        TFNF_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    #[doc = "Bit 2 - Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty."]
27    #[inline(always)]
28    pub fn tfe(&self) -> TFE_R {
29        TFE_R::new(((self.bits >> 2) & 1) != 0)
30    }
31    #[doc = "Bit 3 - Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty."]
32    #[inline(always)]
33    pub fn rfne(&self) -> RFNE_R {
34        RFNE_R::new(((self.bits >> 3) & 1) != 0)
35    }
36    #[doc = "Bit 4 - Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full."]
37    #[inline(always)]
38    pub fn rff(&self) -> RFF_R {
39        RFF_R::new(((self.bits >> 4) & 1) != 0)
40    }
41}
42impl W {
43    #[doc = r" Writes raw bits to the register."]
44    #[doc = r""]
45    #[doc = r" # Safety"]
46    #[doc = r""]
47    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
48    #[inline(always)]
49    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
50        self.bits = bits;
51        self
52    }
53}
54#[doc = "UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct USR_SPEC;
56impl crate::RegisterSpec for USR_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`usr::R`](R) reader structure"]
60impl crate::Readable for USR_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`usr::W`](W) writer structure"]
62impl crate::Writable for USR_SPEC {
63    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
64    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
65}
66#[doc = "`reset()` method sets usr to value 0"]
67impl crate::Resettable for USR_SPEC {
68    const RESET_VALUE: Self::Ux = 0;
69}
jh7110_vf2_13b_pac/uart2/usr.rs

jh7110_vf2_13b_pac/uart2/
usr.rs
