jh7110_vf2_12a_pac/sys_syscon/
sys_syscfg_9.rs

1#[doc = "Register `sys_syscfg_9` reader"]
2pub type R = crate::R<SYS_SYSCFG_9_SPEC>;
3#[doc = "Register `sys_syscfg_9` writer"]
4pub type W = crate::W<SYS_SYSCFG_9_SPEC>;
5#[doc = "Field `pll0_prediv` reader - pll0_prediv"]
6pub type PLL0_PREDIV_R = crate::FieldReader;
7#[doc = "Field `pll0_prediv` writer - pll0_prediv"]
8pub type PLL0_PREDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `pll0_testen` reader - pll0_testen"]
10pub type PLL0_TESTEN_R = crate::BitReader;
11#[doc = "Field `pll0_testen` writer - pll0_testen"]
12pub type PLL0_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `pll0_testsel` reader - pll0_testsel"]
14pub type PLL0_TESTSEL_R = crate::FieldReader;
15#[doc = "Field `pll0_testsel` writer - pll0_testsel"]
16pub type PLL0_TESTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `pll1_cpi_bias` reader - pll1_cpi_bias"]
18pub type PLL1_CPI_BIAS_R = crate::FieldReader;
19#[doc = "Field `pll1_cpi_bias` writer - pll1_cpi_bias"]
20pub type PLL1_CPI_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `pll1_cpp_bias` reader - pll1_cpp_bias"]
22pub type PLL1_CPP_BIAS_R = crate::FieldReader;
23#[doc = "Field `pll1_cpp_bias` writer - pll1_cpp_bias"]
24pub type PLL1_CPP_BIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `pll1_dacpd` reader - pll1_dacpd"]
26pub type PLL1_DACPD_R = crate::BitReader;
27#[doc = "Field `pll1_dacpd` writer - pll1_dacpd"]
28pub type PLL1_DACPD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `pll1_dsmpd` reader - pll1_dsmpd"]
30pub type PLL1_DSMPD_R = crate::BitReader;
31#[doc = "Field `pll1_dsmpd` writer - pll1_dsmpd"]
32pub type PLL1_DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `pll1_fbdiv` reader - pll1_fbdiv"]
34pub type PLL1_FBDIV_R = crate::FieldReader<u16>;
35#[doc = "Field `pll1_fbdiv` writer - pll1_fbdiv"]
36pub type PLL1_FBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
37impl R {
38    #[doc = "Bits 0:5 - pll0_prediv"]
39    #[inline(always)]
40    pub fn pll0_prediv(&self) -> PLL0_PREDIV_R {
41        PLL0_PREDIV_R::new((self.bits & 0x3f) as u8)
42    }
43    #[doc = "Bit 6 - pll0_testen"]
44    #[inline(always)]
45    pub fn pll0_testen(&self) -> PLL0_TESTEN_R {
46        PLL0_TESTEN_R::new(((self.bits >> 6) & 1) != 0)
47    }
48    #[doc = "Bits 7:8 - pll0_testsel"]
49    #[inline(always)]
50    pub fn pll0_testsel(&self) -> PLL0_TESTSEL_R {
51        PLL0_TESTSEL_R::new(((self.bits >> 7) & 3) as u8)
52    }
53    #[doc = "Bits 9:11 - pll1_cpi_bias"]
54    #[inline(always)]
55    pub fn pll1_cpi_bias(&self) -> PLL1_CPI_BIAS_R {
56        PLL1_CPI_BIAS_R::new(((self.bits >> 9) & 7) as u8)
57    }
58    #[doc = "Bits 12:14 - pll1_cpp_bias"]
59    #[inline(always)]
60    pub fn pll1_cpp_bias(&self) -> PLL1_CPP_BIAS_R {
61        PLL1_CPP_BIAS_R::new(((self.bits >> 12) & 7) as u8)
62    }
63    #[doc = "Bit 15 - pll1_dacpd"]
64    #[inline(always)]
65    pub fn pll1_dacpd(&self) -> PLL1_DACPD_R {
66        PLL1_DACPD_R::new(((self.bits >> 15) & 1) != 0)
67    }
68    #[doc = "Bit 16 - pll1_dsmpd"]
69    #[inline(always)]
70    pub fn pll1_dsmpd(&self) -> PLL1_DSMPD_R {
71        PLL1_DSMPD_R::new(((self.bits >> 16) & 1) != 0)
72    }
73    #[doc = "Bits 17:28 - pll1_fbdiv"]
74    #[inline(always)]
75    pub fn pll1_fbdiv(&self) -> PLL1_FBDIV_R {
76        PLL1_FBDIV_R::new(((self.bits >> 17) & 0x0fff) as u16)
77    }
78}
79impl W {
80    #[doc = "Bits 0:5 - pll0_prediv"]
81    #[inline(always)]
82    #[must_use]
83    pub fn pll0_prediv(&mut self) -> PLL0_PREDIV_W<SYS_SYSCFG_9_SPEC> {
84        PLL0_PREDIV_W::new(self, 0)
85    }
86    #[doc = "Bit 6 - pll0_testen"]
87    #[inline(always)]
88    #[must_use]
89    pub fn pll0_testen(&mut self) -> PLL0_TESTEN_W<SYS_SYSCFG_9_SPEC> {
90        PLL0_TESTEN_W::new(self, 6)
91    }
92    #[doc = "Bits 7:8 - pll0_testsel"]
93    #[inline(always)]
94    #[must_use]
95    pub fn pll0_testsel(&mut self) -> PLL0_TESTSEL_W<SYS_SYSCFG_9_SPEC> {
96        PLL0_TESTSEL_W::new(self, 7)
97    }
98    #[doc = "Bits 9:11 - pll1_cpi_bias"]
99    #[inline(always)]
100    #[must_use]
101    pub fn pll1_cpi_bias(&mut self) -> PLL1_CPI_BIAS_W<SYS_SYSCFG_9_SPEC> {
102        PLL1_CPI_BIAS_W::new(self, 9)
103    }
104    #[doc = "Bits 12:14 - pll1_cpp_bias"]
105    #[inline(always)]
106    #[must_use]
107    pub fn pll1_cpp_bias(&mut self) -> PLL1_CPP_BIAS_W<SYS_SYSCFG_9_SPEC> {
108        PLL1_CPP_BIAS_W::new(self, 12)
109    }
110    #[doc = "Bit 15 - pll1_dacpd"]
111    #[inline(always)]
112    #[must_use]
113    pub fn pll1_dacpd(&mut self) -> PLL1_DACPD_W<SYS_SYSCFG_9_SPEC> {
114        PLL1_DACPD_W::new(self, 15)
115    }
116    #[doc = "Bit 16 - pll1_dsmpd"]
117    #[inline(always)]
118    #[must_use]
119    pub fn pll1_dsmpd(&mut self) -> PLL1_DSMPD_W<SYS_SYSCFG_9_SPEC> {
120        PLL1_DSMPD_W::new(self, 16)
121    }
122    #[doc = "Bits 17:28 - pll1_fbdiv"]
123    #[inline(always)]
124    #[must_use]
125    pub fn pll1_fbdiv(&mut self) -> PLL1_FBDIV_W<SYS_SYSCFG_9_SPEC> {
126        PLL1_FBDIV_W::new(self, 17)
127    }
128    #[doc = r" Writes raw bits to the register."]
129    #[doc = r""]
130    #[doc = r" # Safety"]
131    #[doc = r""]
132    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
133    #[inline(always)]
134    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
135        self.bits = bits;
136        self
137    }
138}
139#[doc = "SYS SYSCONSAIF SYSCFG 36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_syscfg_9::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_syscfg_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
140pub struct SYS_SYSCFG_9_SPEC;
141impl crate::RegisterSpec for SYS_SYSCFG_9_SPEC {
142    type Ux = u32;
143}
144#[doc = "`read()` method returns [`sys_syscfg_9::R`](R) reader structure"]
145impl crate::Readable for SYS_SYSCFG_9_SPEC {}
146#[doc = "`write(|w| ..)` method takes [`sys_syscfg_9::W`](W) writer structure"]
147impl crate::Writable for SYS_SYSCFG_9_SPEC {
148    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150}
151#[doc = "`reset()` method sets sys_syscfg_9 to value 0"]
152impl crate::Resettable for SYS_SYSCFG_9_SPEC {
153    const RESET_VALUE: Self::Ux = 0;
154}
jh7110_vf2_12a_pac/sys_syscon/sys_syscfg_9.rs

jh7110_vf2_12a_pac/sys_syscon/
sys_syscfg_9.rs
