rt/portable/cpu.rs
1// Browser CPU contract: SIMD128 is selected by bundle compilation, never by x86 CPUID.
2
3/// Native SSE4.1 capability bit; never advertised by the scalar browser backend.
4pub const CPU_SSE41: u32 = 1;
5/// Native AVX2 capability bit; never advertised by the scalar browser backend.
6pub const CPU_AVX2: u32 = 2;
7/// Native FMA capability bit; never advertised by the scalar browser backend.
8pub const CPU_FMA: u32 = 4;
9/// Native POPCNT capability bit; never advertised by the scalar browser backend.
10pub const CPU_POPCNT: u32 = 8;
11/// Native BMI2 capability bit; never advertised by the scalar browser backend.
12pub const CPU_BMI2: u32 = 16;
13
14/// CPUID-shaped compatibility record for architecture-independent platform callers.
15#[derive(Clone, Copy, Default)]
16pub struct CpuidResult {
17 /// EAX result; zero when the CPUID instruction is unavailable.
18 pub eax: u32,
19 /// EBX result.
20 pub ebx: u32,
21 /// ECX result.
22 pub ecx: u32,
23 /// EDX result.
24 pub edx: u32,
25}
26
27/// No x86 CPU leaves exist in WebAssembly.
28pub fn cpuid(_leaf: u32) -> CpuidResult {
29 CpuidResult::default()
30}
31/// No native x86 capability bits apply to either scalar or SIMD128 WASM.
32pub fn features() -> u32 {
33 0
34}
35/// Browser backend selection happens before loading its scalar/SIMD128 bundle.
36pub fn force_baseline() {}