java_asm/dex/
insn_syntax.rs

1#![allow(non_snake_case)]
2
3use crate::dex::{Opcode, I4, U4};
4use crate::impls::jvms::r::U32BasedSize;
5
6macro_rules! syntax {
7    (
8        $(
9            $name:ident {
10                $($field:ident: $t:ty),*
11            };
12        )*
13    ) => {
14        $(
15            #[derive(Copy, Debug, Clone, PartialEq, Eq)]
16            pub struct $name {
17                $(pub $field: $t),*
18            }
19        )*
20    }
21}
22
23syntax! {
24    F00x {};
25    // XX|op
26    F10x { opcode: Opcode, stub: u8 };
27    // B|A|op
28    F12x { opcode: Opcode, vB: U4, vA: U4 };
29    F11n { opcode: Opcode, literalB: I4, vA: U4 };
30    // AA|op
31    F11x { opcode: Opcode, vA: u8 };
32    F10t { opcode: Opcode, offsetA: i8 };
33}
34
35syntax! {
36    // XX|op
37    // AA AA
38    F20t { stub: u8, opcode: Opcode, offsetA: i16 };
39    // AA|op
40    // BB BB
41    F20bc { opcode: Opcode, vA: u8, constB: u16 };
42    // AA|op
43    // BB BB
44    F22x { opcode: Opcode, vA: u8, vB: u16 };
45    F21t { opcode: Opcode, vA: u8, offsetB: i16 };
46    F21s { opcode: Opcode, vA: u8, literalB: i16 };
47    F21h { opcode: Opcode, vA: u8, literalB: i16 };
48    F21c { opcode: Opcode, vA: u8, constB: u16 };
49    // AA|op
50    // CC|BB
51    F23x { opcode: Opcode, vA: u8, vB: u8, vC: u8 };
52    F22b { opcode: Opcode, vA: u8, vB: u8, literalC: i8 };
53    // B|A|op
54    // C C CC
55    F22t { opcode: Opcode, vA: U4, vB: U4, offsetC: i16 };
56    F22s { opcode: Opcode, vA: U4, vB: U4, literalC: i16 };
57    F22c { opcode: Opcode, vA: U4, vB: U4, constC: u16 };
58    F22cs { opcode: Opcode, vA: U4, vB: U4, constC: u16 };
59}
60
61syntax! {
62    // XX|op
63    // AA AA (lo)
64    // AA AA (hi)
65    F30t { stub: u8, opcode: Opcode, offsetA: i32 };
66    // XX|op
67    // AA AA
68    // BB BB
69    F32x { stub: u8, opcode: Opcode, vA: u16, vB: u16 };
70    // AA|op
71    // BB BB (lo)
72    // BB BB (hi)
73    F31i { opcode: Opcode, vA: u8, literalB: i32 };
74    F31t { opcode: Opcode, vA: u8, offsetB: i32 };
75    F31c { opcode: Opcode, vA: u8, constB: U32BasedSize };
76    // A|G|op
77    // B B B B
78    // F|E|D|C
79    F35c { opcode: Opcode, a: U4, vC: U4, vD: U4, vE: U4, vF: U4, vG: U4, constB: u16 };
80    F35ms { opcode: Opcode, a: U4, vC: U4, vD: U4, vE: U4, vF: U4, vG: U4, constB: u16 };
81    F35mi { opcode: Opcode, a: U4, vC: U4, vD: U4, vE: U4, vF: U4, vG: U4, constB: u16 };
82    // AA|op
83    // BB|BB
84    // CC|CC
85    //      N = CC CC + AA - 1
86    F3rc { opcode: Opcode, a: u8, constB: u16, vC: u16 };
87    F3rms { opcode: Opcode, a: u8, constB: u16, vC: u16 };
88    F3rmi { opcode: Opcode, a: u8, constB: u16, vC: u16 };
89}
90
91syntax! {
92    // A|G|op
93    // B B B B
94    // F|E|D|C
95    // H H H H
96    F45cc {
97        opcode: Opcode, a: U4,
98        vC: U4, vD: U4, vE: U4, vF: U4, vG: U4,
99        constB: u16, constH: u16
100    };
101    // AA|op
102    // BB BB
103    // CC CC
104    // HH HH
105    //      N = CC CC + AA - 1
106    F4rcc {
107        opcode: Opcode, a: u8,
108        constB: u16, constH: u16,
109        vC: u16
110    };
111    // AA|op
112    // BB BB (lo)
113    // BB BB
114    // BB BB
115    // BB BB (hi)
116    F51l { opcode: Opcode, vA: u8, literalB: i64 };
117}
java_asm/dex/insn_syntax.rs

java_asm/dex/
insn_syntax.rs
