Enum intel_spi::HsfStsCtlCycle

#[repr(u32)]pub enum HsfStsCtlCycle {
    Read = 0,
    Rsvd = 131_072,
    Write = 262_144,
    BlockErase = 393_216,
    SectorErase = 524_288,
    ReadSfdp = 655_360,
    ReadJedec = 786_432,
    WriteStatus = 917_504,
    ReadStatus = 1_048_576,
    RpmcOp1 = 1_179_648,
    RpmcOp2 = 1_310_720,
}

Variants§

Read = 0

Read number of bytes in FDBC plus one

Rsvd = 131_072

Reserved - treated as 0x0 read

Write = 262_144

Write number of bytes in FDBC plus one

BlockErase = 393_216

Erase 4096 bytes

SectorErase = 524_288

Erase 65536 bytes

ReadSfdp = 655_360

Read SFDP

ReadJedec = 786_432

Read JEDEC ID

WriteStatus = 917_504

Write status

ReadStatus = 1_048_576

Read status

RpmcOp1 = 1_179_648

RPMC Op1

RpmcOp2 = 1_310_720

Rpmc Op2

Auto Trait Implementations§

impl RefUnwindSafe for HsfStsCtlCycle

impl Send for HsfStsCtlCycle

impl Sync for HsfStsCtlCycle

impl Unpin for HsfStsCtlCycle

impl UnwindSafe for HsfStsCtlCycle

Blanket Implementations§

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