intel_8080_kit/emu/
mod.rs

1const CYCLES: [usize; 256] = [
2    4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5,
3    7, 4, 4, 10, 16, 5, 5, 5, 7, 4, 4, 10, 16, 5, 5, 5, 7, 4, 4, 10, 13, 5, 10, 10, 10, 4, 4, 10,
4    13, 5, 5, 5, 7, 4, 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 5,
5    5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5, 7, 7, 7, 7, 7, 7, 7, 7, 5,
6    5, 5, 5, 5, 5, 7, 5, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 4,
7    4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, 4,
8    4, 4, 4, 4, 4, 7, 4, 5, 10, 10, 10, 11, 11, 7, 11, 5, 10, 10, 10, 11, 17, 7, 11, 5, 10, 10, 10,
9    11, 11, 7, 11, 5, 10, 10, 10, 11, 17, 7, 11, 5, 10, 10, 18, 11, 11, 7, 11, 5, 5, 10, 4, 11, 17,
10    7, 11, 5, 10, 10, 4, 11, 11, 7, 11, 5, 5, 10, 4, 11, 17, 7, 11,
11];
12
13pub trait Memory {
14    fn read_byte(&self, addr: u16) -> u8;
15    fn read_word(&self, addr: u16) -> u16;
16
17    fn write_byte(&mut self, addr: u16, byte: u8);
18    fn write_word(&mut self, addr: u16, word: u16);
19
20    fn in_port(&self, port: u8) -> u8;
21    fn out_port(&self, port: u8, byte: u8);
22}
23
24pub struct Emulator {
25    /// Memory
26    mem: Box<dyn Memory>,
27    /// Halted
28    halt: bool,
29    /// Cycles count
30    cycles: usize,
31    /// Program counter
32    pc: Word,
33    /// Stack pointer
34    sp: Word,
35    /// Sign flag
36    s_flag: Flag,
37    /// Zero flag
38    z_flag: Flag,
39    /// Half-carry flag
40    h_flag: Flag,
41    /// Parity flag
42    p_flag: Flag,
43    /// Carry flag
44    c_flag: Flag,
45    a_reg: Register,
46    b_reg: Register,
47    c_reg: Register,
48    d_reg: Register,
49    e_reg: Register,
50    h_reg: Register,
51    l_reg: Register,
52    /// Interrupts information
53    int: InterruptInfo,
54}
55
56#[derive(Debug, Default)]
57struct Register(pub Byte);
58
59#[derive(Debug, Default)]
60struct Flag(pub bool);
61
62#[derive(Debug, Default)]
63struct InterruptInfo {
64    pub pending: bool,
65    pub filp_flop: bool,
66    pub vector: Byte,
67    pub delay: Byte,
68}
69
70#[derive(Debug, Default, Clone, Copy)]
71struct Word(pub u16);
72
73#[derive(Debug, Default, Clone, Copy)]
74struct Byte(pub u8);
75
76impl Byte {
77    pub fn bit_parity(&self) -> bool {
78        let mut ones = 0;
79
80        for i in 0..8 {
81            ones += (self.0 >> i) & i;
82        }
83
84        (ones & 1) == 0
85    }
86
87    pub fn bit_carry(&self, other: Byte, alredy: bool, bits: i32) -> bool {
88        let res = (self.0 as u16) + (other.0 as u16) + (alredy as u16);
89        let carry = res ^ (self.0 as u16) ^ (other.0 as u16);
90
91        carry & (1 << bits) != 0
92    }
93}
94
95impl Emulator {
96    pub fn new(mem: Box<dyn Memory>) -> Self {
97        Self {
98            mem,
99            halt: false,
100            cycles: 0,
101            pc: Word::default(),
102            sp: Word::default(),
103            s_flag: Flag::default(),
104            z_flag: Flag::default(),
105            h_flag: Flag::default(),
106            p_flag: Flag::default(),
107            c_flag: Flag::default(),
108            a_reg: Register::default(),
109            b_reg: Register::default(),
110            c_reg: Register::default(),
111            d_reg: Register::default(),
112            e_reg: Register::default(),
113            h_reg: Register::default(),
114            l_reg: Register::default(),
115            int: InterruptInfo::default(),
116        }
117    }
118
119    fn set_flags(&mut self, value: Byte) {
120        self.z_flag.0 = value.0 == 0u8;
121        self.s_flag.0 = (value.0 >> 7) == 1;
122        self.p_flag.0 = value.bit_parity();
123    }
124
125    fn fetch_next_byte(&mut self) -> u8 {
126        let byte = self.mem.read_byte(self.pc.0);
127        self.pc.0 += 1;
128        byte
129    }
130
131    fn fetch_next_word(&mut self) -> u16 {
132        let word = self.mem.read_word(self.pc.0);
133        self.pc.0 += 2;
134        word
135    }
136
137    fn set_bc_pair(&mut self, value: u16) {
138        self.b_reg.0 = Byte((value >> 8) as u8);
139        self.c_reg.0 = Byte((value & 0xff) as u8);
140    }
141
142    fn get_bc_pair(&self) -> u16 {
143        (self.b_reg.0 .0 as u16) << 8 | self.c_reg.0 .0 as u16
144    }
145
146    fn set_de_pair(&mut self, value: u16) {
147        self.d_reg.0 = Byte((value >> 8) as u8);
148        self.e_reg.0 = Byte((value & 0xff) as u8);
149    }
150
151    fn get_de_pair(&self) -> u16 {
152        (self.d_reg.0 .0 as u16) << 8 | self.e_reg.0 .0 as u16
153    }
154
155    fn set_hl_pair(&mut self, value: u16) {
156        self.l_reg.0 = Byte((value >> 8) as u8);
157        self.h_reg.0 = Byte((value & 0xff) as u8);
158    }
159
160    fn get_hl_pair(&self) -> u16 {
161        (self.h_reg.0 .0 as u16) << 8 | self.l_reg.0 .0 as u16
162    }
163
164    fn push_stack(&mut self, value: u16) {
165        self.sp.0 -= 2;
166        self.mem.write_word(self.sp.0, value);
167    }
168
169    fn pop_stack(&mut self) -> u16 {
170        let value = self.mem.read_word(self.sp.0);
171        self.sp.0 += 2;
172        value
173    }
174
175    fn op_inr(&mut self, value: Byte) -> Byte {
176        let res = Byte(value.0 + 1);
177        self.h_flag.0 = (res.0 & 0x0f) == 0;
178        self.set_flags(res);
179        res
180    }
181
182    fn op_dcr(&mut self, value: Byte) -> Byte {
183        let res = Byte(value.0 - 1);
184        self.h_flag.0 = (res.0 & 0x0f) != 0x0f;
185        self.set_flags(res);
186        res
187    }
188
189    fn op_dad(&mut self, value: u16) {
190        self.c_flag.0 = ((((self.get_hl_pair() + value) as u32) >> 16) & 1) != 0;
191        self.set_hl_pair(self.get_hl_pair() + value);
192    }
193
194    fn op_add(&mut self, reg: Byte, value: Byte, alredy: bool) -> Byte {
195        let res = Byte(reg.0 + value.0 + (alredy as u8));
196        let byte = Byte(reg.0);
197        self.c_flag.0 = byte.bit_carry(value, alredy, 8);
198        self.h_flag.0 = byte.bit_carry(value, alredy, 4);
199
200        self.set_flags(res);
201        res
202    }
203
204    fn op_sub(&mut self, reg: Byte, value: Byte, alredy: bool) -> Byte {
205        let res = self.op_add(reg, Byte(!value.0), !alredy);
206        self.c_flag.0 = !self.c_flag.0;
207        res
208    }
209
210    fn op_daa(&mut self) {
211        let mut alredy = self.c_flag.0;
212        let mut adj = 0;
213        let lsb = self.a_reg.0 .0 & 0x0f;
214        let msb = self.a_reg.0 .0 >> 4;
215
216        if self.h_flag.0 || lsb > 9 {
217            adj += 0x06;
218        }
219
220        if self.c_flag.0 || msb > 9 || (msb >= 9 && lsb > 9) {
221            adj += 0x60;
222            alredy = true;
223        }
224
225        self.a_reg.0 = self.op_add(self.a_reg.0, Byte(adj), alredy);
226        self.c_flag.0 = alredy;
227    }
228
229    fn op_ana(&mut self, value: u8) {
230        let res = Byte(self.a_reg.0 .0 & value);
231        self.c_flag.0 = false;
232        self.h_flag.0 = ((self.a_reg.0 .0 | value) & 0x08) != 0;
233
234        self.set_flags(res);
235        self.a_reg.0 = res;
236    }
237
238    fn op_xra(&mut self, value: u8) {
239        self.a_reg.0 .0 ^= value;
240        self.c_flag.0 = false;
241        self.h_flag.0 = false;
242        self.set_flags(self.a_reg.0);
243    }
244
245    fn op_ora(&mut self, value: u8) {
246        self.a_reg.0 .0 |= value;
247        self.c_flag.0 = false;
248        self.h_flag.0 = false;
249        self.set_flags(self.a_reg.0);
250    }
251
252    fn op_cmp(&mut self, value: u8) {
253        let res = self.a_reg.0 .0 - value;
254        self.c_flag.0 = ((res as u16) >> 8) != 0;
255        self.h_flag.0 = (!(self.a_reg.0 .0 ^ res ^ value) & 0x10) != 0;
256        self.set_flags(Byte(res & 0xff));
257    }
258
259    fn op_jmp(&mut self, addr: u16) {
260        self.pc.0 = addr;
261    }
262
263    fn op_cond_jmp(&mut self, cond: bool) {
264        let addr = self.fetch_next_word();
265
266        if cond {
267            self.op_jmp(addr);
268        }
269    }
270
271    fn op_call(&mut self, addr: u16) {
272        self.push_stack(self.pc.0);
273        self.op_jmp(addr);
274    }
275
276    fn op_cond_call(&mut self, cond: bool) {
277        let addr = self.fetch_next_word();
278
279        if cond {
280            self.op_call(addr);
281            self.cycles += 6;
282        }
283    }
284
285    fn op_ret(&mut self) {
286        self.pc.0 = self.pop_stack();
287    }
288
289    fn op_cond_ret(&mut self, cond: bool) {
290        if cond {
291            self.op_ret();
292            self.cycles += 6;
293        }
294    }
295
296    pub fn exec(&mut self, op: u8) {
297        self.cycles += CYCLES[op as usize];
298
299        if self.int.delay.0 > 0 {
300            self.int.delay.0 -= 1;
301        }
302
303        match op {
304            0x00 => {}
305            0x01 => {
306                let word = self.fetch_next_word();
307                self.set_bc_pair(word);
308            }
309            0x02 => {
310                let value = self.get_bc_pair();
311                self.mem.write_byte(value, self.a_reg.0 .0);
312            }
313            0x03 => {
314                let value = self.get_bc_pair();
315                self.set_bc_pair(value + 1);
316            }
317            0x04 => {
318                self.b_reg.0 = self.op_inr(self.b_reg.0);
319            }
320            0x05 => {
321                self.b_reg.0 = self.op_dcr(self.b_reg.0);
322            }
323            0x06 => {
324                self.b_reg.0 = Byte(self.fetch_next_byte());
325            }
326            0x07 => {
327                self.c_flag.0 = (self.a_reg.0 .0 >> 7) != 0;
328                self.a_reg.0 .0 = (self.a_reg.0 .0 << 1) | self.c_flag.0 as u8;
329            }
330            0x09 => {
331                self.op_dad(self.get_bc_pair());
332            }
333            0x0a => {
334                self.a_reg.0 .0 = self.mem.read_byte(self.get_bc_pair());
335            }
336            0x0b => {
337                let value = self.get_bc_pair();
338                self.set_bc_pair(value - 1);
339            }
340            0x0c => {
341                self.c_reg.0 = self.op_inr(self.c_reg.0);
342            }
343            0x0d => {
344                self.c_reg.0 = self.op_dcr(self.c_reg.0);
345            }
346            0x0e => {
347                self.c_reg.0 = Byte(self.fetch_next_byte());
348            }
349            0x0f => {
350                self.c_flag.0 = (self.a_reg.0 .0 & 1) != 0;
351                self.a_reg.0 .0 = (self.a_reg.0 .0 >> 1) | ((self.c_flag.0 as u8) << 7)
352            }
353            0x11 => {
354                let word = self.fetch_next_word();
355                self.set_de_pair(word);
356            }
357            0x12 => {
358                let addr = self.get_de_pair();
359                self.mem.write_byte(addr, self.a_reg.0 .0);
360            }
361            0x13 => {
362                let value = self.get_de_pair();
363                self.set_de_pair(value + 1);
364            }
365            0x14 => {
366                self.d_reg.0 = self.op_inr(self.d_reg.0);
367            }
368            0x15 => {
369                self.d_reg.0 = self.op_dcr(self.d_reg.0);
370            }
371            0x16 => {
372                self.d_reg.0 = Byte(self.fetch_next_byte());
373            }
374            0x17 => {
375                let alredy = self.c_flag.0;
376                self.c_flag.0 = (self.a_reg.0 .0 >> 7) != 0;
377                self.a_reg.0 .0 = (self.a_reg.0 .0 << 1) | (alredy as u8);
378            }
379            0x19 => {
380                self.op_dad(self.get_de_pair());
381            }
382            0x1a => {
383                self.a_reg.0 .0 = self.mem.read_byte(self.get_de_pair());
384            }
385            0x1b => {
386                let value = self.get_de_pair();
387                self.set_de_pair(value - 1);
388            }
389            0x1c => {
390                self.e_reg.0 = self.op_inr(self.e_reg.0);
391            }
392            0x1d => {
393                self.e_reg.0 = self.op_dcr(self.e_reg.0);
394            }
395            0x1e => {
396                self.e_reg.0 = Byte(self.fetch_next_byte());
397            }
398            0x1f => {
399                let alredy = self.c_flag.0;
400                self.c_flag.0 = (self.a_reg.0 .0 & 1) != 0;
401                self.a_reg.0 .0 = (self.a_reg.0 .0 >> 1) | ((alredy as u8) << 7);
402            }
403            0x21 => {
404                let word = self.fetch_next_word();
405                self.set_hl_pair(word);
406            }
407            0x22 => {
408                let addr = self.fetch_next_word();
409                self.mem.write_word(addr, self.get_hl_pair());
410            }
411            0x23 => {
412                let value = self.get_hl_pair();
413                self.set_hl_pair(value + 1);
414            }
415            0x24 => {
416                self.h_reg.0 = self.op_inr(self.h_reg.0);
417            }
418            0x25 => {
419                self.h_reg.0 = self.op_dcr(self.h_reg.0);
420            }
421            0x26 => {
422                self.h_reg.0 = Byte(self.fetch_next_byte());
423            }
424            0x27 => {
425                self.op_daa();
426            }
427            0x29 => {
428                self.op_dad(self.get_hl_pair());
429            }
430            0x2a => {
431                let addr = self.fetch_next_word();
432                self.set_hl_pair(self.mem.read_word(addr))
433            }
434            0x2b => {
435                let value = self.get_hl_pair();
436                self.set_hl_pair(value - 1);
437            }
438            0x2c => {
439                self.l_reg.0 = self.op_inr(self.l_reg.0);
440            }
441            0x2d => {
442                self.l_reg.0 = self.op_dcr(self.l_reg.0);
443            }
444            0x2e => {
445                self.l_reg.0 = Byte(self.fetch_next_byte());
446            }
447            0x2f => {
448                self.a_reg.0 .0 = !self.a_reg.0 .0;
449            }
450            0x31 => {
451                let word = self.fetch_next_word();
452                self.sp = Word(word);
453            }
454            0x32 => {
455                let addr = self.fetch_next_word();
456                self.mem.write_byte(addr, self.a_reg.0 .0);
457            }
458            0x33 => {
459                self.sp.0 += 1;
460            }
461            0x34 => {
462                let byte = self.mem.read_byte(self.get_hl_pair());
463                let value = self.op_inr(Byte(byte));
464                self.mem.write_byte(self.get_hl_pair(), value.0);
465            }
466            0x35 => {
467                let byte = self.mem.read_byte(self.get_hl_pair());
468                let value = self.op_dcr(Byte(byte));
469                self.mem.write_byte(self.get_hl_pair(), value.0);
470            }
471            0x36 => {
472                let value = self.fetch_next_byte();
473                self.mem.write_byte(self.get_hl_pair(), value);
474            }
475            0x37 => {
476                self.c_flag.0 = true;
477            }
478            0x39 => {
479                self.op_dad(self.sp.0);
480            }
481            0x3a => {
482                let addr = self.fetch_next_word();
483                self.a_reg.0 .0 = self.mem.read_byte(addr);
484            }
485            0x3b => {
486                self.sp.0 -= 1;
487            }
488            0x3c => {
489                self.a_reg.0 = self.op_inr(self.a_reg.0);
490            }
491            0x3d => {
492                self.a_reg.0 = self.op_dcr(self.a_reg.0);
493            }
494            0x3e => {
495                self.a_reg.0 = Byte(self.fetch_next_byte());
496            }
497            0x3f => {
498                self.c_flag.0 = !self.c_flag.0;
499            }
500            0x40 => {
501                self.b_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
502            }
503            0x41 => {
504                self.b_reg.0 = self.c_reg.0;
505            }
506            0x42 => {
507                self.b_reg.0 = self.d_reg.0;
508            }
509            0x43 => {
510                self.b_reg.0 = self.e_reg.0;
511            }
512            0x44 => {
513                self.b_reg.0 = self.h_reg.0;
514            }
515            0x45 => {
516                self.b_reg.0 = self.l_reg.0;
517            }
518            0x46 => {
519                self.b_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
520            }
521            0x47 => {
522                self.b_reg.0 = self.a_reg.0;
523            }
524            0x48 => {
525                self.c_reg.0 = self.b_reg.0;
526            }
527            0x49 => {
528                self.c_reg.0 = self.c_reg.0;
529            }
530            0x4a => {
531                self.c_reg.0 = self.d_reg.0;
532            }
533            0x4b => {
534                self.c_reg.0 = self.e_reg.0;
535            }
536            0x4c => {
537                self.c_reg.0 = self.h_reg.0;
538            }
539            0x4d => {
540                self.c_reg.0 = self.l_reg.0;
541            }
542            0x4e => {
543                self.c_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
544            }
545            0x4f => {
546                self.c_reg.0 = self.a_reg.0;
547            }
548            0x50 => {
549                self.d_reg.0 = self.b_reg.0;
550            }
551            0x51 => {
552                self.d_reg.0 = self.c_reg.0;
553            }
554            0x52 => {
555                self.d_reg.0 = self.d_reg.0;
556            }
557            0x53 => {
558                self.d_reg.0 = self.e_reg.0;
559            }
560            0x54 => {
561                self.d_reg.0 = self.h_reg.0;
562            }
563            0x55 => {
564                self.d_reg.0 = self.l_reg.0;
565            }
566            0x56 => {
567                self.d_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
568            }
569            0x57 => {
570                self.d_reg.0 = self.a_reg.0;
571            }
572            0x58 => {
573                self.e_reg.0 = self.b_reg.0;
574            }
575            0x59 => {
576                self.e_reg.0 = self.c_reg.0;
577            }
578            0x5a => {
579                self.e_reg.0 = self.d_reg.0;
580            }
581            0x5b => {
582                self.e_reg.0 = self.e_reg.0;
583            }
584            0x5c => {
585                self.e_reg.0 = self.h_reg.0;
586            }
587            0x5d => {
588                self.e_reg.0 = self.l_reg.0;
589            }
590            0x5e => {
591                self.e_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
592            }
593            0x5f => {
594                self.e_reg.0 = self.a_reg.0;
595            }
596            0x60 => {
597                self.h_reg.0 = self.b_reg.0;
598            }
599            0x61 => {
600                self.h_reg.0 = self.c_reg.0;
601            }
602            0x62 => {
603                self.h_reg.0 = self.d_reg.0;
604            }
605            0x63 => {
606                self.h_reg.0 = self.e_reg.0;
607            }
608            0x64 => {
609                self.h_reg.0 = self.h_reg.0;
610            }
611            0x65 => {
612                self.h_reg.0 = self.l_reg.0;
613            }
614            0x66 => {
615                self.h_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
616            }
617            0x67 => {
618                self.h_reg.0 = self.a_reg.0;
619            }
620            0x68 => {
621                self.l_reg.0 = self.b_reg.0;
622            }
623            0x69 => {
624                self.l_reg.0 = self.c_reg.0;
625            }
626            0x6a => {
627                self.l_reg.0 = self.d_reg.0;
628            }
629            0x6b => {
630                self.l_reg.0 = self.e_reg.0;
631            }
632            0x6c => {
633                self.l_reg.0 = self.h_reg.0;
634            }
635            0x6d => {
636                self.l_reg.0 = self.l_reg.0;
637            }
638            0x6e => {
639                self.l_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
640            }
641            0x6f => {
642                self.l_reg.0 = self.a_reg.0;
643            }
644            0x70 => {
645                self.mem.write_byte(self.get_hl_pair(), self.b_reg.0 .0);
646            }
647            0x71 => {
648                self.mem.write_byte(self.get_hl_pair(), self.c_reg.0 .0);
649            }
650            0x72 => {
651                self.mem.write_byte(self.get_hl_pair(), self.d_reg.0 .0);
652            }
653            0x73 => {
654                self.mem.write_byte(self.get_hl_pair(), self.e_reg.0 .0);
655            }
656            0x74 => {
657                self.mem.write_byte(self.get_hl_pair(), self.h_reg.0 .0);
658            }
659            0x75 => {
660                self.mem.write_byte(self.get_hl_pair(), self.l_reg.0 .0);
661            }
662            0x76 => {
663                self.halt = true;
664            }
665            0x77 => {
666                self.mem.write_byte(self.get_hl_pair(), self.a_reg.0 .0);
667            }
668            0x78 => {
669                self.a_reg.0 = self.b_reg.0;
670            }
671            0x79 => {
672                self.a_reg.0 = self.c_reg.0;
673            }
674            0x7a => {
675                self.a_reg.0 = self.d_reg.0;
676            }
677            0x7b => {
678                self.a_reg.0 = self.e_reg.0;
679            }
680            0x7c => {
681                self.a_reg.0 = self.h_reg.0;
682            }
683            0x7d => {
684                self.a_reg.0 = self.l_reg.0;
685            }
686            0x7e => {
687                self.a_reg.0 .0 = self.mem.read_byte(self.get_hl_pair());
688            }
689            0x7f => {
690                self.a_reg.0 = self.a_reg.0;
691            }
692            0x80 => {
693                self.a_reg.0 = self.op_add(self.a_reg.0, self.b_reg.0, false);
694            }
695            0x81 => {
696                self.a_reg.0 = self.op_add(self.a_reg.0, self.c_reg.0, false);
697            }
698            0x82 => {
699                self.a_reg.0 = self.op_add(self.a_reg.0, self.d_reg.0, false);
700            }
701            0x83 => {
702                self.a_reg.0 = self.op_add(self.a_reg.0, self.e_reg.0, false);
703            }
704            0x84 => {
705                self.a_reg.0 = self.op_add(self.a_reg.0, self.h_reg.0, false);
706            }
707            0x85 => {
708                self.a_reg.0 = self.op_add(self.a_reg.0, self.l_reg.0, false);
709            }
710            0x86 => {
711                let value = self.mem.read_byte(self.get_hl_pair());
712                self.a_reg.0 = self.op_add(self.a_reg.0, Byte(value), false);
713            }
714            0x87 => {
715                self.a_reg.0 = self.op_add(self.a_reg.0, self.a_reg.0, false);
716            }
717            0x88 => {
718                self.a_reg.0 = self.op_add(self.a_reg.0, self.b_reg.0, self.c_flag.0);
719            }
720            0x89 => {
721                self.a_reg.0 = self.op_add(self.a_reg.0, self.c_reg.0, self.c_flag.0);
722            }
723            0x8a => {
724                self.a_reg.0 = self.op_add(self.a_reg.0, self.d_reg.0, self.c_flag.0);
725            }
726            0x8b => {
727                self.a_reg.0 = self.op_add(self.a_reg.0, self.e_reg.0, self.c_flag.0);
728            }
729            0x8c => {
730                self.a_reg.0 = self.op_add(self.a_reg.0, self.h_reg.0, self.c_flag.0);
731            }
732            0x8d => {
733                self.a_reg.0 = self.op_add(self.a_reg.0, self.l_reg.0, self.c_flag.0);
734            }
735            0x8e => {
736                let value = self.mem.read_byte(self.get_hl_pair());
737                self.a_reg.0 = self.op_add(self.a_reg.0, Byte(value), self.c_flag.0);
738            }
739            0x8f => {
740                self.a_reg.0 = self.op_add(self.a_reg.0, self.a_reg.0, self.c_flag.0);
741            }
742            0x90 => {
743                self.a_reg.0 = self.op_sub(self.a_reg.0, self.b_reg.0, false);
744            }
745            0x91 => {
746                self.a_reg.0 = self.op_sub(self.a_reg.0, self.c_reg.0, false);
747            }
748            0x92 => {
749                self.a_reg.0 = self.op_sub(self.a_reg.0, self.d_reg.0, false);
750            }
751            0x93 => {
752                self.a_reg.0 = self.op_sub(self.a_reg.0, self.e_reg.0, false);
753            }
754            0x94 => {
755                self.a_reg.0 = self.op_sub(self.a_reg.0, self.h_reg.0, false);
756            }
757            0x95 => {
758                self.a_reg.0 = self.op_sub(self.a_reg.0, self.l_reg.0, false);
759            }
760            0x96 => {
761                let value = self.mem.read_byte(self.get_hl_pair());
762                self.a_reg.0 = self.op_sub(self.a_reg.0, Byte(value), false);
763            }
764            0x97 => {
765                self.a_reg.0 = self.op_sub(self.a_reg.0, self.a_reg.0, false);
766            }
767            0x98 => {
768                self.a_reg.0 = self.op_sub(self.a_reg.0, self.b_reg.0, self.c_flag.0);
769            }
770            0x99 => {
771                self.a_reg.0 = self.op_sub(self.a_reg.0, self.c_reg.0, self.c_flag.0);
772            }
773            0x9a => {
774                self.a_reg.0 = self.op_sub(self.a_reg.0, self.d_reg.0, self.c_flag.0);
775            }
776            0x9b => {
777                self.a_reg.0 = self.op_sub(self.a_reg.0, self.e_reg.0, self.c_flag.0);
778            }
779            0x9c => {
780                self.a_reg.0 = self.op_sub(self.a_reg.0, self.h_reg.0, self.c_flag.0);
781            }
782            0x9d => {
783                self.a_reg.0 = self.op_sub(self.a_reg.0, self.l_reg.0, self.c_flag.0);
784            }
785            0x9e => {
786                let value = self.mem.read_byte(self.get_hl_pair());
787                self.a_reg.0 = self.op_sub(self.a_reg.0, Byte(value), self.c_flag.0);
788            }
789            0x9f => {
790                self.a_reg.0 = self.op_sub(self.a_reg.0, self.a_reg.0, self.c_flag.0);
791            }
792            0xa0 => {
793                self.op_ana(self.b_reg.0 .0);
794            }
795            0xa1 => {
796                self.op_ana(self.c_reg.0 .0);
797            }
798            0xa2 => {
799                self.op_ana(self.d_reg.0 .0);
800            }
801            0xa3 => {
802                self.op_ana(self.e_reg.0 .0);
803            }
804            0xa4 => {
805                self.op_ana(self.h_reg.0 .0);
806            }
807            0xa5 => {
808                self.op_ana(self.l_reg.0 .0);
809            }
810            0xa6 => {
811                let value = self.mem.read_byte(self.get_hl_pair());
812                self.op_ana(value);
813            }
814            0xa7 => {
815                self.op_ana(self.a_reg.0 .0);
816            }
817            0xa8 => {
818                self.op_xra(self.b_reg.0 .0);
819            }
820            0xa9 => {
821                self.op_xra(self.c_reg.0 .0);
822            }
823            0xaa => {
824                self.op_xra(self.d_reg.0 .0);
825            }
826            0xab => {
827                self.op_xra(self.e_reg.0 .0);
828            }
829            0xac => {
830                self.op_xra(self.h_reg.0 .0);
831            }
832            0xad => {
833                self.op_xra(self.l_reg.0 .0);
834            }
835            0xae => {
836                let value = self.mem.read_byte(self.get_hl_pair());
837                self.op_xra(value);
838            }
839            0xaf => {
840                self.op_xra(self.a_reg.0 .0);
841            }
842            0xb0 => {
843                self.op_ora(self.b_reg.0 .0);
844            }
845            0xb1 => {
846                self.op_ora(self.c_reg.0 .0);
847            }
848            0xb2 => {
849                self.op_ora(self.d_reg.0 .0);
850            }
851            0xb3 => {
852                self.op_ora(self.e_reg.0 .0);
853            }
854            0xb4 => {
855                self.op_ora(self.h_reg.0 .0);
856            }
857            0xb5 => {
858                self.op_ora(self.l_reg.0 .0);
859            }
860            0xb6 => {
861                let value = self.mem.read_byte(self.get_hl_pair());
862                self.op_ora(value);
863            }
864            0xb7 => {
865                self.op_ora(self.a_reg.0 .0);
866            }
867            0xb8 => {
868                self.op_cmp(self.b_reg.0 .0);
869            }
870            0xb9 => {
871                self.op_cmp(self.c_reg.0 .0);
872            }
873            0xba => {
874                self.op_cmp(self.d_reg.0 .0);
875            }
876            0xbb => {
877                self.op_cmp(self.e_reg.0 .0);
878            }
879            0xbc => {
880                self.op_cmp(self.h_reg.0 .0);
881            }
882            0xbd => {
883                self.op_cmp(self.l_reg.0 .0);
884            }
885            0xbe => {
886                let value = self.mem.read_byte(self.get_hl_pair());
887                self.op_cmp(value);
888            }
889            0xbf => {
890                self.op_cmp(self.a_reg.0 .0);
891            }
892            0xc0 => {
893                self.op_cond_ret(!self.z_flag.0);
894            }
895            0xc1 => {
896                let value = self.pop_stack();
897                self.set_bc_pair(value)
898            }
899            0xc2 => {
900                self.op_cond_jmp(!self.z_flag.0);
901            }
902            0xc3 => {
903                let addr = self.fetch_next_word();
904                self.op_jmp(addr);
905            }
906            0xc4 => {
907                self.op_cond_call(!self.z_flag.0);
908            }
909            0xc5 => {
910                self.push_stack(self.get_bc_pair());
911            }
912            0xc6 => {
913                let value = self.fetch_next_byte();
914                self.a_reg.0 = self.op_add(self.a_reg.0, Byte(value), false);
915            }
916            0xc7 => {
917                self.op_call(0x00);
918            }
919            0xc8 => {
920                self.op_cond_ret(self.z_flag.0);
921            }
922            0xc9 => {
923                self.op_ret();
924            }
925            0xca => {
926                self.op_cond_jmp(self.z_flag.0);
927            }
928            0xcc => {
929                self.op_cond_call(self.z_flag.0);
930            }
931            0xcd => {
932                let addr = self.fetch_next_word();
933                self.op_call(addr);
934            }
935            0xce => {
936                let value = self.fetch_next_byte();
937                self.a_reg.0 = self.op_add(self.a_reg.0, Byte(value), self.c_flag.0);
938            }
939            0xcf => {
940                self.op_call(0x08);
941            }
942            0xd0 => {
943                self.op_cond_ret(!self.c_flag.0);
944            }
945            0xd1 => {
946                let value = self.pop_stack();
947                self.set_de_pair(value)
948            }
949            0xd2 => {
950                self.op_cond_jmp(!self.c_flag.0);
951            }
952            0xd3 => {
953                let port = self.fetch_next_byte();
954                self.mem.out_port(port, self.a_reg.0 .0);
955            }
956            0xd4 => {
957                self.op_cond_call(!self.c_flag.0);
958            }
959            0xd5 => {
960                self.push_stack(self.get_de_pair());
961            }
962            0xd6 => {
963                let value = self.fetch_next_byte();
964                self.a_reg.0 = self.op_sub(self.a_reg.0, Byte(value), false);
965            }
966            0xd7 => {
967                self.op_call(0x10);
968            }
969            0xd8 => {
970                self.op_cond_ret(self.c_flag.0);
971            }
972            0xda => {
973                self.op_cond_jmp(self.c_flag.0);
974            }
975            0xdb => {
976                let port = self.fetch_next_byte();
977                self.a_reg.0 .0 = self.mem.in_port(port);
978            }
979            0xdc => {
980                self.op_cond_call(self.c_flag.0);
981            }
982            0xde => {
983                let value = self.fetch_next_byte();
984                self.a_reg.0 = self.op_sub(self.a_reg.0, Byte(value), self.c_flag.0);
985            }
986            0xdf => {
987                self.op_call(0x18);
988            }
989            0xe0 => {
990                self.op_cond_ret(!self.p_flag.0);
991            }
992            0xe1 => {
993                let value = self.pop_stack();
994                self.set_hl_pair(value)
995            }
996            0xe2 => {
997                self.op_cond_jmp(!self.p_flag.0);
998            }
999            0xe3 => {
1000                let value = self.mem.read_word(self.sp.0);
1001                self.mem.write_word(self.sp.0, self.get_hl_pair());
1002                self.set_hl_pair(value);
1003            }
1004            0xe4 => {
1005                self.op_cond_call(!self.p_flag.0);
1006            }
1007            0xe5 => {
1008                self.push_stack(self.get_hl_pair());
1009            }
1010            0xe6 => {
1011                let value = self.fetch_next_byte();
1012                self.op_ana(value);
1013            }
1014            0xe7 => {
1015                self.op_call(0x20);
1016            }
1017            0xe8 => {
1018                self.op_cond_ret(self.p_flag.0);
1019            }
1020            0xe9 => {
1021                self.pc.0 = self.get_hl_pair();
1022            }
1023            0xea => {
1024                self.op_cond_jmp(self.p_flag.0);
1025            }
1026            0xeb => {
1027                let value = self.get_de_pair();
1028                self.set_de_pair(self.get_hl_pair());
1029                self.set_hl_pair(value);
1030            }
1031            0xec => {
1032                self.op_cond_call(self.p_flag.0);
1033            }
1034            0xee => {
1035                let value = self.fetch_next_byte();
1036                self.op_xra(value);
1037            }
1038            0xef => {
1039                self.op_call(0x28);
1040            }
1041            0xf0 => {
1042                self.op_cond_ret(!self.s_flag.0);
1043            }
1044            0xf1 => {
1045                let value = self.pop_stack();
1046                self.a_reg.0 .0 = (value >> 8) as u8;
1047
1048                let psw = (value & 0xff) as u8;
1049                self.s_flag.0 = ((psw >> 7) & 1) != 0;
1050                self.z_flag.0 = ((psw >> 6) & 1) != 0;
1051                self.h_flag.0 = ((psw >> 4) & 1) != 0;
1052                self.p_flag.0 = ((psw >> 2) & 1) != 0;
1053                self.c_flag.0 = ((psw >> 0) & 1) != 0;
1054            }
1055            0xf2 => {
1056                self.op_cond_jmp(!self.s_flag.0);
1057            }
1058            0xf3 => {
1059                self.int.filp_flop = true;
1060            }
1061            0xf4 => {
1062                self.op_cond_call(!self.s_flag.0);
1063            }
1064            0xf5 => {
1065                let mut psw: u8 = 0;
1066                psw |= (self.s_flag.0 as u8) << 7;
1067                psw |= (self.z_flag.0 as u8) << 6;
1068                psw |= (self.h_flag.0 as u8) << 4;
1069                psw |= (self.p_flag.0 as u8) << 2;
1070                psw |= 1 << 1;
1071                psw |= (self.c_flag.0 as u8) << 0;
1072
1073                self.push_stack((self.a_reg.0 .0 as u16) << 8 | (psw as u16));
1074            }
1075            0xf6 => {
1076                let value = self.fetch_next_byte();
1077                self.op_ora(value);
1078            }
1079            0xf7 => {
1080                self.op_call(0x30);
1081            }
1082            0xf8 => {
1083                self.op_cond_ret(self.s_flag.0);
1084            }
1085            0xf9 => {
1086                self.sp.0 = self.get_hl_pair();
1087            }
1088            0xfa => {
1089                self.op_cond_jmp(self.s_flag.0);
1090            }
1091            0xfb => {
1092                self.int.filp_flop = false;
1093                self.int.delay.0 = 1;
1094            }
1095            0xfc => {
1096                self.op_cond_call(self.s_flag.0);
1097            }
1098            0xfe => {
1099                let value = self.fetch_next_byte();
1100                self.op_cmp(value);
1101            }
1102            0xff => {
1103                self.op_call(0x38);
1104            }
1105
1106            // Undocumented ops
1107            0x08 | 0x10 | 0x18 | 0x20 | 0x28 | 0x30 | 0x38 => {}
1108            0xd9 => {
1109                self.op_ret();
1110            }
1111            0xdd | 0xed | 0xfd => {
1112                let addr = self.fetch_next_word();
1113                self.op_call(addr);
1114            }
1115            0xcb => {
1116                let addr = self.fetch_next_word();
1117                self.op_jmp(addr);
1118            }
1119        }
1120    }
1121
1122    pub fn run(&mut self) {
1123        while !self.halt {
1124            let op = self.fetch_next_byte();
1125            self.exec(op);
1126        }
1127    }
1128}
intel_8080_kit/emu/mod.rs

intel_8080_kit/emu/
mod.rs
