Struct imxrt1062_usbphy1::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u32, Reg<u32, _PWD>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:9 - Reserved.

pub fn txpwdfs(&self) -> TXPWDFS_R

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&self) -> TXPWDIBIAS_R

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&self) -> TXPWDV2I_R

Bit 12 - 0 = Normal operation

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:16 - Reserved.

pub fn rxpwdenv(&self) -> RXPWDENV_R

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&self) -> RXPWD1PT1_R

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&self) -> RXPWDDIFF_R

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&self) -> RXPWDRX_R

Bit 20 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:31 - Reserved.

impl R<u32, Reg<u32, _PWD_SET>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:9 - Reserved.

pub fn txpwdfs(&self) -> TXPWDFS_R

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&self) -> TXPWDIBIAS_R

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&self) -> TXPWDV2I_R

Bit 12 - 0 = Normal operation

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:16 - Reserved.

pub fn rxpwdenv(&self) -> RXPWDENV_R

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&self) -> RXPWD1PT1_R

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&self) -> RXPWDDIFF_R

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&self) -> RXPWDRX_R

Bit 20 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:31 - Reserved.

impl R<u32, Reg<u32, _PWD_CLR>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:9 - Reserved.

pub fn txpwdfs(&self) -> TXPWDFS_R

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&self) -> TXPWDIBIAS_R

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&self) -> TXPWDV2I_R

Bit 12 - 0 = Normal operation

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:16 - Reserved.

pub fn rxpwdenv(&self) -> RXPWDENV_R

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&self) -> RXPWD1PT1_R

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&self) -> RXPWDDIFF_R

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&self) -> RXPWDRX_R

Bit 20 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:31 - Reserved.

impl R<u32, Reg<u32, _PWD_TOG>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:9 - Reserved.

pub fn txpwdfs(&self) -> TXPWDFS_R

Bit 10 - 0 = Normal operation

pub fn txpwdibias(&self) -> TXPWDIBIAS_R

Bit 11 - 0 = Normal operation

pub fn txpwdv2i(&self) -> TXPWDV2I_R

Bit 12 - 0 = Normal operation

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:16 - Reserved.

pub fn rxpwdenv(&self) -> RXPWDENV_R

Bit 17 - 0 = Normal operation

pub fn rxpwd1pt1(&self) -> RXPWD1PT1_R

Bit 18 - 0 = Normal operation

pub fn rxpwddiff(&self) -> RXPWDDIFF_R

Bit 19 - 0 = Normal operation

pub fn rxpwdrx(&self) -> RXPWDRX_R

Bit 20 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:31 - Reserved.

impl R<u32, Reg<u32, _TX>>

pub fn d_cal(&self) -> D_CAL_R

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&self) -> RSVD0_R

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&self) -> TXCAL45DN_R

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&self) -> RSVD1_R

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&self) -> TXCAL45DP_R

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn rsvd2(&self) -> RSVD2_R

Bits 20:25 - Reserved.

pub fn usbphy_tx_edgectrl(&self) -> USBPHY_TX_EDGECTRL_R

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

pub fn rsvd5(&self) -> RSVD5_R

Bits 29:31 - Reserved.

impl R<u32, Reg<u32, _TX_SET>>

pub fn d_cal(&self) -> D_CAL_R

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&self) -> RSVD0_R

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&self) -> TXCAL45DN_R

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&self) -> RSVD1_R

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&self) -> TXCAL45DP_R

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn rsvd2(&self) -> RSVD2_R

Bits 20:25 - Reserved.

pub fn usbphy_tx_edgectrl(&self) -> USBPHY_TX_EDGECTRL_R

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

pub fn rsvd5(&self) -> RSVD5_R

Bits 29:31 - Reserved.

impl R<u32, Reg<u32, _TX_CLR>>

pub fn d_cal(&self) -> D_CAL_R

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&self) -> RSVD0_R

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&self) -> TXCAL45DN_R

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&self) -> RSVD1_R

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&self) -> TXCAL45DP_R

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn rsvd2(&self) -> RSVD2_R

Bits 20:25 - Reserved.

pub fn usbphy_tx_edgectrl(&self) -> USBPHY_TX_EDGECTRL_R

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

pub fn rsvd5(&self) -> RSVD5_R

Bits 29:31 - Reserved.

impl R<u32, Reg<u32, _TX_TOG>>

pub fn d_cal(&self) -> D_CAL_R

Bits 0:3 - Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%

pub fn rsvd0(&self) -> RSVD0_R

Bits 4:7 - Reserved. Note: This bit should remain clear.

pub fn txcal45dn(&self) -> TXCAL45DN_R

Bits 8:11 - Decode to select a 45-Ohm resistance to the USB_DN output pin

pub fn rsvd1(&self) -> RSVD1_R

Bits 12:15 - Reserved. Note: This bit should remain clear.

pub fn txcal45dp(&self) -> TXCAL45DP_R

Bits 16:19 - Decode to select a 45-Ohm resistance to the USB_DP output pin

pub fn rsvd2(&self) -> RSVD2_R

Bits 20:25 - Reserved.

pub fn usbphy_tx_edgectrl(&self) -> USBPHY_TX_EDGECTRL_R

Bits 26:28 - Controls the edge-rate of the current sensing transistors used in HS transmit

pub fn rsvd5(&self) -> RSVD5_R

Bits 29:31 - Reserved.

impl R<u32, Reg<u32, _RX>>

pub fn envadj(&self) -> ENVADJ_R

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn rsvd0(&self) -> RSVD0_R

Bit 3 - Reserved.

pub fn disconadj(&self) -> DISCONADJ_R

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rsvd1(&self) -> RSVD1_R

Bits 7:21 - Reserved.

pub fn rxdbypass(&self) -> RXDBYPASS_R

Bit 22 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 23:31 - Reserved.

impl R<u32, Reg<u32, _RX_SET>>

pub fn envadj(&self) -> ENVADJ_R

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn rsvd0(&self) -> RSVD0_R

Bit 3 - Reserved.

pub fn disconadj(&self) -> DISCONADJ_R

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rsvd1(&self) -> RSVD1_R

Bits 7:21 - Reserved.

pub fn rxdbypass(&self) -> RXDBYPASS_R

Bit 22 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 23:31 - Reserved.

impl R<u32, Reg<u32, _RX_CLR>>

pub fn envadj(&self) -> ENVADJ_R

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn rsvd0(&self) -> RSVD0_R

Bit 3 - Reserved.

pub fn disconadj(&self) -> DISCONADJ_R

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rsvd1(&self) -> RSVD1_R

Bits 7:21 - Reserved.

pub fn rxdbypass(&self) -> RXDBYPASS_R

Bit 22 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 23:31 - Reserved.

impl R<u32, Reg<u32, _RX_TOG>>

pub fn envadj(&self) -> ENVADJ_R

Bits 0:2 - The ENVADJ field adjusts the trip point for the envelope detector

pub fn rsvd0(&self) -> RSVD0_R

Bit 3 - Reserved.

pub fn disconadj(&self) -> DISCONADJ_R

Bits 4:6 - The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0

pub fn rsvd1(&self) -> RSVD1_R

Bits 7:21 - Reserved.

pub fn rxdbypass(&self) -> RXDBYPASS_R

Bit 22 - 0 = Normal operation

pub fn rsvd2(&self) -> RSVD2_R

Bits 23:31 - Reserved.

impl R<u32, Reg<u32, _CTRL>>

pub fn enotg_id_chg_irq(&self) -> ENOTG_ID_CHG_IRQ_R

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&self) -> ENIRQHOSTDISCON_R

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&self) -> ENDEVPLUGINDETECT_R

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&self) -> DEVPLUGIN_POLARITY_R

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&self) -> OTG_ID_CHG_IRQ_R

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&self) -> ENOTGIDDETECT_R

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&self) -> RESUMEIRQSTICKY_R

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&self) -> ENIRQRESUMEDETECT_R

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&self) -> RESUME_IRQ_R

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&self) -> ENIRQDEVPLUGIN_R

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&self) -> DATA_ON_LRADC_R

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&self) -> ENIRQWAKEUP_R

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&self) -> WAKEUP_IRQ_R

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&self) -> ENAUTO_PWRON_PLL_R

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&self) -> ENDPDMCHG_WKUP_R

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&self) -> ENIDCHG_WKUP_R

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&self) -> ENVBUSCHG_WKUP_R

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&self) -> FSDLL_RST_EN_R

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn rsvd1(&self) -> RSVD1_R

Bits 25:26 - Reserved.

pub fn otg_id_value(&self) -> OTG_ID_VALUE_R

Bit 27 - Almost same as OTGID_STATUS in USBPHYx_STATUS Register

pub fn host_force_ls_se0(&self) -> HOST_FORCE_LS_SE0_R

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R

Bit 29 - Used by the PHY to indicate a powered-down state

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl R<u32, Reg<u32, _CTRL_SET>>

pub fn enotg_id_chg_irq(&self) -> ENOTG_ID_CHG_IRQ_R

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&self) -> ENIRQHOSTDISCON_R

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&self) -> ENDEVPLUGINDETECT_R

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&self) -> DEVPLUGIN_POLARITY_R

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&self) -> OTG_ID_CHG_IRQ_R

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&self) -> ENOTGIDDETECT_R

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&self) -> RESUMEIRQSTICKY_R

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&self) -> ENIRQRESUMEDETECT_R

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&self) -> RESUME_IRQ_R

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&self) -> ENIRQDEVPLUGIN_R

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&self) -> DATA_ON_LRADC_R

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&self) -> ENIRQWAKEUP_R

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&self) -> WAKEUP_IRQ_R

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&self) -> ENAUTO_PWRON_PLL_R

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&self) -> ENDPDMCHG_WKUP_R

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&self) -> ENIDCHG_WKUP_R

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&self) -> ENVBUSCHG_WKUP_R

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&self) -> FSDLL_RST_EN_R

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn rsvd1(&self) -> RSVD1_R

Bits 25:26 - Reserved.

pub fn otg_id_value(&self) -> OTG_ID_VALUE_R

Bit 27 - Almost same as OTGID_STATUS in USBPHYx_STATUS Register

pub fn host_force_ls_se0(&self) -> HOST_FORCE_LS_SE0_R

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R

Bit 29 - Used by the PHY to indicate a powered-down state

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl R<u32, Reg<u32, _CTRL_CLR>>

pub fn enotg_id_chg_irq(&self) -> ENOTG_ID_CHG_IRQ_R

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&self) -> ENIRQHOSTDISCON_R

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&self) -> ENDEVPLUGINDETECT_R

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&self) -> DEVPLUGIN_POLARITY_R

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&self) -> OTG_ID_CHG_IRQ_R

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&self) -> ENOTGIDDETECT_R

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&self) -> RESUMEIRQSTICKY_R

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&self) -> ENIRQRESUMEDETECT_R

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&self) -> RESUME_IRQ_R

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&self) -> ENIRQDEVPLUGIN_R

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&self) -> DATA_ON_LRADC_R

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&self) -> ENIRQWAKEUP_R

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&self) -> WAKEUP_IRQ_R

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&self) -> ENAUTO_PWRON_PLL_R

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&self) -> ENDPDMCHG_WKUP_R

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&self) -> ENIDCHG_WKUP_R

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&self) -> ENVBUSCHG_WKUP_R

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&self) -> FSDLL_RST_EN_R

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn rsvd1(&self) -> RSVD1_R

Bits 25:26 - Reserved.

pub fn otg_id_value(&self) -> OTG_ID_VALUE_R

Bit 27 - Almost same as OTGID_STATUS in USBPHYx_STATUS Register

pub fn host_force_ls_se0(&self) -> HOST_FORCE_LS_SE0_R

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R

Bit 29 - Used by the PHY to indicate a powered-down state

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl R<u32, Reg<u32, _CTRL_TOG>>

pub fn enotg_id_chg_irq(&self) -> ENOTG_ID_CHG_IRQ_R

Bit 0 - Enable OTG_ID_CHG_IRQ.

pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R

Bit 1 - For host mode, enables high-speed disconnect detector

pub fn enirqhostdiscon(&self) -> ENIRQHOSTDISCON_R

Bit 2 - Enables interrupt for detection of disconnection to Device when in high-speed host mode

pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R

Bit 3 - Indicates that the device has disconnected in high-speed mode

pub fn endevplugindetect(&self) -> ENDEVPLUGINDETECT_R

Bit 4 - For device mode, enables 200-KOhm pullups for detecting connectivity to the host.

pub fn devplugin_polarity(&self) -> DEVPLUGIN_POLARITY_R

Bit 5 - For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in

pub fn otg_id_chg_irq(&self) -> OTG_ID_CHG_IRQ_R

Bit 6 - OTG ID change interrupt. Indicates the value of ID pin changed.

pub fn enotgiddetect(&self) -> ENOTGIDDETECT_R

Bit 7 - Enables circuit to detect resistance of MiniAB ID pin.

pub fn resumeirqsticky(&self) -> RESUMEIRQSTICKY_R

Bit 8 - Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it

pub fn enirqresumedetect(&self) -> ENIRQRESUMEDETECT_R

Bit 9 - Enables interrupt for detection of a non-J state on the USB line

pub fn resume_irq(&self) -> RESUME_IRQ_R

Bit 10 - Indicates that the host is sending a wake-up after suspend

pub fn enirqdevplugin(&self) -> ENIRQDEVPLUGIN_R

Bit 11 - Enables interrupt for the detection of connectivity to the USB line.

pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R

Bit 12 - Indicates that the device is connected

pub fn data_on_lradc(&self) -> DATA_ON_LRADC_R

Bit 13 - Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only.

pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R

Bit 14 - Enables UTMI+ Level2. This should be enabled if needs to support LS device

pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R

Bit 15 - Enables UTMI+ Level3

pub fn enirqwakeup(&self) -> ENIRQWAKEUP_R

Bit 16 - Enables interrupt for the wakeup events.

pub fn wakeup_irq(&self) -> WAKEUP_IRQ_R

Bit 17 - Indicates that there is a wakeup event

pub fn enauto_pwron_pll(&self) -> ENAUTO_PWRON_PLL_R

Bit 18 - Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended

pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R

Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended

pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R

Bit 20 - Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended

pub fn endpdmchg_wkup(&self) -> ENDPDMCHG_WKUP_R

Bit 21 - Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended

pub fn enidchg_wkup(&self) -> ENIDCHG_WKUP_R

Bit 22 - Enables the feature to wakeup USB if ID is toggled when USB is suspended.

pub fn envbuschg_wkup(&self) -> ENVBUSCHG_WKUP_R

Bit 23 - Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.

pub fn fsdll_rst_en(&self) -> FSDLL_RST_EN_R

Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.

pub fn rsvd1(&self) -> RSVD1_R

Bits 25:26 - Reserved.

pub fn otg_id_value(&self) -> OTG_ID_VALUE_R

Bit 27 - Almost same as OTGID_STATUS in USBPHYx_STATUS Register

pub fn host_force_ls_se0(&self) -> HOST_FORCE_LS_SE0_R

Bit 28 - Forces the next FS packet that is transmitted to have a EOP with LS timing

pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R

Bit 29 - Used by the PHY to indicate a powered-down state

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate UTMI Clocks

pub fn sftrst(&self) -> SFTRST_R

Bit 31 - Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers

impl R<u32, Reg<u32, _STATUS>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:2 - Reserved.

pub fn hostdiscondetect_status(&self) -> HOSTDISCONDETECT_STATUS_R

Bit 3 - Indicates that the device has disconnected while in high-speed host mode.

pub fn rsvd1(&self) -> RSVD1_R

Bits 4:5 - Reserved.

pub fn devplugin_status(&self) -> DEVPLUGIN_STATUS_R

Bit 6 - Indicates that the device has been connected on the USB_DP and USB_DM lines.

pub fn rsvd2(&self) -> RSVD2_R

Bit 7 - Reserved.

pub fn otgid_status(&self) -> OTGID_STATUS_R

Bit 8 - Indicates the results of ID pin on MiniAB plug

pub fn rsvd3(&self) -> RSVD3_R

Bit 9 - Reserved.

pub fn resume_status(&self) -> RESUME_STATUS_R

Bit 10 - Indicates that the host is sending a wake-up after suspend and has triggered an interrupt.

pub fn rsvd4(&self) -> RSVD4_R

Bits 11:31 - Reserved.

impl R<u32, Reg<u32, _DEBUG>>

pub fn otgidpiolock(&self) -> OTGIDPIOLOCK_R

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&self) -> DEBUG_INTERFACE_HOLD_R

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&self) -> HSTPULLDOWN_R

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&self) -> ENHSTPULLDOWN_R

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn rsvd0(&self) -> RSVD0_R

Bits 6:7 - Reserved.

pub fn tx2rxcount(&self) -> TX2RXCOUNT_R

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&self) -> ENTX2RXCOUNT_R

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:15 - Reserved.

pub fn squelchresetcount(&self) -> SQUELCHRESETCOUNT_R

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:23 - Reserved.

pub fn ensquelchreset(&self) -> ENSQUELCHRESET_R

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&self) -> SQUELCHRESETLENGTH_R

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&self) -> HOST_RESUME_DEBUG_R

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate Test Clocks

pub fn rsvd3(&self) -> RSVD3_R

Bit 31 - Reserved.

impl R<u32, Reg<u32, _DEBUG_SET>>

pub fn otgidpiolock(&self) -> OTGIDPIOLOCK_R

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&self) -> DEBUG_INTERFACE_HOLD_R

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&self) -> HSTPULLDOWN_R

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&self) -> ENHSTPULLDOWN_R

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn rsvd0(&self) -> RSVD0_R

Bits 6:7 - Reserved.

pub fn tx2rxcount(&self) -> TX2RXCOUNT_R

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&self) -> ENTX2RXCOUNT_R

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:15 - Reserved.

pub fn squelchresetcount(&self) -> SQUELCHRESETCOUNT_R

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:23 - Reserved.

pub fn ensquelchreset(&self) -> ENSQUELCHRESET_R

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&self) -> SQUELCHRESETLENGTH_R

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&self) -> HOST_RESUME_DEBUG_R

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate Test Clocks

pub fn rsvd3(&self) -> RSVD3_R

Bit 31 - Reserved.

impl R<u32, Reg<u32, _DEBUG_CLR>>

pub fn otgidpiolock(&self) -> OTGIDPIOLOCK_R

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&self) -> DEBUG_INTERFACE_HOLD_R

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&self) -> HSTPULLDOWN_R

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&self) -> ENHSTPULLDOWN_R

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn rsvd0(&self) -> RSVD0_R

Bits 6:7 - Reserved.

pub fn tx2rxcount(&self) -> TX2RXCOUNT_R

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&self) -> ENTX2RXCOUNT_R

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:15 - Reserved.

pub fn squelchresetcount(&self) -> SQUELCHRESETCOUNT_R

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:23 - Reserved.

pub fn ensquelchreset(&self) -> ENSQUELCHRESET_R

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&self) -> SQUELCHRESETLENGTH_R

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&self) -> HOST_RESUME_DEBUG_R

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate Test Clocks

pub fn rsvd3(&self) -> RSVD3_R

Bit 31 - Reserved.

impl R<u32, Reg<u32, _DEBUG_TOG>>

pub fn otgidpiolock(&self) -> OTGIDPIOLOCK_R

Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value

pub fn debug_interface_hold(&self) -> DEBUG_INTERFACE_HOLD_R

Bit 1 - Use holding registers to assist in timing for external UTMI interface.

pub fn hstpulldown(&self) -> HSTPULLDOWN_R

Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line

pub fn enhstpulldown(&self) -> ENHSTPULLDOWN_R

Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown

pub fn rsvd0(&self) -> RSVD0_R

Bits 6:7 - Reserved.

pub fn tx2rxcount(&self) -> TX2RXCOUNT_R

Bits 8:11 - Delay in between the end of transmit to the beginning of receive

pub fn entx2rxcount(&self) -> ENTX2RXCOUNT_R

Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.

pub fn rsvd1(&self) -> RSVD1_R

Bits 13:15 - Reserved.

pub fn squelchresetcount(&self) -> SQUELCHRESETCOUNT_R

Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.

pub fn rsvd2(&self) -> RSVD2_R

Bits 21:23 - Reserved.

pub fn ensquelchreset(&self) -> ENSQUELCHRESET_R

Bit 24 - Set bit to allow squelch to reset high-speed receive.

pub fn squelchresetlength(&self) -> SQUELCHRESETLENGTH_R

Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.

pub fn host_resume_debug(&self) -> HOST_RESUME_DEBUG_R

Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.

pub fn clkgate(&self) -> CLKGATE_R

Bit 30 - Gate Test Clocks

pub fn rsvd3(&self) -> RSVD3_R

Bit 31 - Reserved.

impl R<u32, Reg<u32, _DEBUG0_STATUS>>

pub fn loop_back_fail_count(&self) -> LOOP_BACK_FAIL_COUNT_R

Bits 0:15 - Running count of the failed pseudo-random generator loopback

pub fn utmi_rxerror_fail_count(&self) -> UTMI_RXERROR_FAIL_COUNT_R

Bits 16:25 - Running count of the UTMI_RXERROR.

pub fn squelch_count(&self) -> SQUELCH_COUNT_R

Bits 26:31 - Running count of the squelch reset instead of normal end for HS RX.

impl R<u32, Reg<u32, _DEBUG1>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&self) -> ENTAILADJVD_R

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

pub fn rsvd1(&self) -> RSVD1_R

Bits 15:31 - Reserved.

impl R<u32, Reg<u32, _DEBUG1_SET>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&self) -> ENTAILADJVD_R

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

pub fn rsvd1(&self) -> RSVD1_R

Bits 15:31 - Reserved.

impl R<u32, Reg<u32, _DEBUG1_CLR>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&self) -> ENTAILADJVD_R

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

pub fn rsvd1(&self) -> RSVD1_R

Bits 15:31 - Reserved.

impl R<u32, Reg<u32, _DEBUG1_TOG>>

pub fn rsvd0(&self) -> RSVD0_R

Bits 0:12 - Reserved. Note: This bit should remain clear.

pub fn entailadjvd(&self) -> ENTAILADJVD_R

Bits 13:14 - Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%

pub fn rsvd1(&self) -> RSVD1_R

Bits 15:31 - Reserved.

impl R<u32, Reg<u32, _VERSION>>

pub fn step(&self) -> STEP_R

Bits 0:15 - Fixed read-only value reflecting the stepping of the RTL version.

pub fn minor(&self) -> MINOR_R

Bits 16:23 - Fixed read-only value reflecting the MINOR field of the RTL version.

pub fn major(&self) -> MAJOR_R

Bits 24:31 - Fixed read-only value reflecting the MAJOR field of the RTL version.

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.