Type Definition imxrt1062_usb1::endptctrl3::W

type W = W<u32, ENDPTCTRL3>;

Writer for register ENDPTCTRL3

Methods

impl W

pub fn rxs(&mut self) -> RXS_W

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&mut self) -> RXD_W

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&mut self) -> RXT_W

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&mut self) -> RXI_W

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&mut self) -> RXR_W

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&mut self) -> RXE_W

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&mut self) -> TXS_W

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&mut self) -> TXD_W

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&mut self) -> TXT_W

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&mut self) -> TXI_W

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&mut self) -> TXR_W

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&mut self) -> TXE_W

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured