Struct imxrt1062_usb1::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u32, Reg<u32, _ID>>

pub fn id(&self) -> ID_R

Bits 0:5 - Configuration number

pub fn nid(&self) -> NID_R

Bits 8:13 - Complement version of ID

pub fn revision(&self) -> REVISION_R

Bits 16:23 - Revision number of the controller core.

impl R<u8, PHYW_A>

pub fn variant(&self) -> PHYW_A

Get enumerated values variant

pub fn is_phyw_0(&self) -> bool

Checks if the value of the field is PHYW_0

pub fn is_phyw_1(&self) -> bool

Checks if the value of the field is PHYW_1

pub fn is_phyw_2(&self) -> bool

Checks if the value of the field is PHYW_2

pub fn is_phyw_3(&self) -> bool

Checks if the value of the field is PHYW_3

impl R<u8, PHYM_A>

pub fn variant(&self) -> PHYM_A

Get enumerated values variant

pub fn is_phym_0(&self) -> bool

Checks if the value of the field is PHYM_0

pub fn is_phym_1(&self) -> bool

Checks if the value of the field is PHYM_1

pub fn is_phym_2(&self) -> bool

Checks if the value of the field is PHYM_2

pub fn is_phym_3(&self) -> bool

Checks if the value of the field is PHYM_3

pub fn is_phym_4(&self) -> bool

Checks if the value of the field is PHYM_4

pub fn is_phym_5(&self) -> bool

Checks if the value of the field is PHYM_5

pub fn is_phym_6(&self) -> bool

Checks if the value of the field is PHYM_6

pub fn is_phym_7(&self) -> bool

Checks if the value of the field is PHYM_7

impl R<u8, SM_A>

pub fn variant(&self) -> SM_A

Get enumerated values variant

pub fn is_sm_0(&self) -> bool

Checks if the value of the field is SM_0

pub fn is_sm_1(&self) -> bool

Checks if the value of the field is SM_1

pub fn is_sm_2(&self) -> bool

Checks if the value of the field is SM_2

pub fn is_sm_3(&self) -> bool

Checks if the value of the field is SM_3

impl R<u32, Reg<u32, _HWGENERAL>>

pub fn phyw(&self) -> PHYW_R

Bits 4:5 - Data width of the transciever connected to the controller core. PHYW bit reset value is

pub fn phym(&self) -> PHYM_R

Bits 6:8 - Transciever type

pub fn sm(&self) -> SM_R

Bits 9:10 - Serial interface mode capability

impl R<bool, HC_A>

pub fn variant(&self) -> HC_A

Get enumerated values variant

pub fn is_hc_0(&self) -> bool

Checks if the value of the field is HC_0

pub fn is_hc_1(&self) -> bool

Checks if the value of the field is HC_1

impl R<u32, Reg<u32, _HWHOST>>

pub fn hc(&self) -> HC_R

Bit 0 - Host Capable. Indicating whether host operation mode is supported or not.

pub fn nport(&self) -> NPORT_R

Bits 1:3 - The Nmber of downstream ports supported by the host controller is (NPORT+1)

impl R<bool, DC_A>

pub fn variant(&self) -> DC_A

Get enumerated values variant

pub fn is_dc_0(&self) -> bool

Checks if the value of the field is DC_0

pub fn is_dc_1(&self) -> bool

Checks if the value of the field is DC_1

impl R<u32, Reg<u32, _HWDEVICE>>

pub fn dc(&self) -> DC_R

Bit 0 - Device Capable. Indicating whether device operation mode is supported or not.

pub fn devep(&self) -> DEVEP_R

Bits 1:5 - Device Endpoint Number

impl R<u32, Reg<u32, _HWTXBUF>>

pub fn txburst(&self) -> TXBURST_R

Bits 0:7 - Default burst size for memory to TX buffer transfer

pub fn txchanadd(&self) -> TXCHANADD_R

Bits 16:23 - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes

impl R<u32, Reg<u32, _HWRXBUF>>

pub fn rxburst(&self) -> RXBURST_R

Bits 0:7 - Default burst size for memory to RX buffer transfer

pub fn rxadd(&self) -> RXADD_R

Bits 8:15 - Buffer total size for all receive endpoints is (2^RXADD)

impl R<u32, Reg<u32, _GPTIMER0LD>>

pub fn gptld(&self) -> GPTLD_R

Bits 0:23 - General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'

impl R<bool, GPTMODE_A>

pub fn variant(&self) -> GPTMODE_A

Get enumerated values variant

pub fn is_gptmode_0(&self) -> bool

Checks if the value of the field is GPTMODE_0

pub fn is_gptmode_1(&self) -> bool

Checks if the value of the field is GPTMODE_1

impl R<bool, GPTRST_A>

pub fn variant(&self) -> GPTRST_A

Get enumerated values variant

pub fn is_gptrst_0(&self) -> bool

Checks if the value of the field is GPTRST_0

pub fn is_gptrst_1(&self) -> bool

Checks if the value of the field is GPTRST_1

impl R<bool, GPTRUN_A>

pub fn variant(&self) -> GPTRUN_A

Get enumerated values variant

pub fn is_gptrun_0(&self) -> bool

Checks if the value of the field is GPTRUN_0

pub fn is_gptrun_1(&self) -> bool

Checks if the value of the field is GPTRUN_1

impl R<u32, Reg<u32, _GPTIMER0CTRL>>

pub fn gptcnt(&self) -> GPTCNT_R

Bits 0:23 - General Purpose Timer Counter. This field is the count value of the countdown timer.

pub fn gptmode(&self) -> GPTMODE_R

Bit 24 - General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again

pub fn gptrst(&self) -> GPTRST_R

Bit 30 - General Purpose Timer Reset

pub fn gptrun(&self) -> GPTRUN_R

Bit 31 - General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.

impl R<u32, Reg<u32, _GPTIMER1LD>>

pub fn gptld(&self) -> GPTLD_R

Bits 0:23 - General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'

impl R<bool, GPTMODE_A>

pub fn variant(&self) -> GPTMODE_A

Get enumerated values variant

pub fn is_gptmode_0(&self) -> bool

Checks if the value of the field is GPTMODE_0

pub fn is_gptmode_1(&self) -> bool

Checks if the value of the field is GPTMODE_1

impl R<bool, GPTRST_A>

pub fn variant(&self) -> GPTRST_A

Get enumerated values variant

pub fn is_gptrst_0(&self) -> bool

Checks if the value of the field is GPTRST_0

pub fn is_gptrst_1(&self) -> bool

Checks if the value of the field is GPTRST_1

impl R<bool, GPTRUN_A>

pub fn variant(&self) -> GPTRUN_A

Get enumerated values variant

pub fn is_gptrun_0(&self) -> bool

Checks if the value of the field is GPTRUN_0

pub fn is_gptrun_1(&self) -> bool

Checks if the value of the field is GPTRUN_1

impl R<u32, Reg<u32, _GPTIMER1CTRL>>

pub fn gptcnt(&self) -> GPTCNT_R

Bits 0:23 - General Purpose Timer Counter. This field is the count value of the countdown timer.

pub fn gptmode(&self) -> GPTMODE_R

Bit 24 - General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software

pub fn gptrst(&self) -> GPTRST_R

Bit 30 - General Purpose Timer Reset

pub fn gptrun(&self) -> GPTRUN_R

Bit 31 - General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit.

impl R<u8, AHBBRST_A>

pub fn variant(&self) -> Variant<u8, AHBBRST_A>

Get enumerated values variant

pub fn is_ahbbrst_0(&self) -> bool

Checks if the value of the field is AHBBRST_0

pub fn is_ahbbrst_1(&self) -> bool

Checks if the value of the field is AHBBRST_1

pub fn is_ahbbrst_2(&self) -> bool

Checks if the value of the field is AHBBRST_2

pub fn is_ahbbrst_3(&self) -> bool

Checks if the value of the field is AHBBRST_3

pub fn is_ahbbrst_5(&self) -> bool

Checks if the value of the field is AHBBRST_5

pub fn is_ahbbrst_6(&self) -> bool

Checks if the value of the field is AHBBRST_6

pub fn is_ahbbrst_7(&self) -> bool

Checks if the value of the field is AHBBRST_7

impl R<u32, Reg<u32, _SBUSCFG>>

pub fn ahbbrst(&self) -> AHBBRST_R

Bits 0:2 - AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority)

impl R<u8, Reg<u8, _CAPLENGTH>>

pub fn caplength(&self) -> CAPLENGTH_R

Bits 0:7 - These bits are used as an offset to add to register base to find the beginning of the Operational Register

impl R<u16, Reg<u16, _HCIVERSION>>

pub fn hciversion(&self) -> HCIVERSION_R

Bits 0:15 - Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0.

impl R<u8, N_CC_A>

pub fn variant(&self) -> Variant<u8, N_CC_A>

Get enumerated values variant

pub fn is_n_cc_0(&self) -> bool

Checks if the value of the field is N_CC_0

pub fn is_n_cc_1(&self) -> bool

Checks if the value of the field is N_CC_1

impl R<u32, Reg<u32, _HCSPARAMS>>

pub fn n_ports(&self) -> N_PORTS_R

Bits 0:3 - Number of downstream ports

pub fn ppc(&self) -> PPC_R

Bit 4 - Port Power Control This field indicates whether the host controller implementation includes port power control

pub fn n_pcc(&self) -> N_PCC_R

Bits 8:11 - Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller

pub fn n_cc(&self) -> N_CC_R

Bits 12:15 - Number of Companion Controller (N_CC)

pub fn pi(&self) -> PI_R

Bit 16 - Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control

pub fn n_ptt(&self) -> N_PTT_R

Bits 20:23 - Number of Ports per Transaction Translator (N_PTT)

pub fn n_tt(&self) -> N_TT_R

Bits 24:27 - Number of Transaction Translators (N_TT)

impl R<u32, Reg<u32, _HCCPARAMS>>

pub fn adc(&self) -> ADC_R

Bit 0 - 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported

pub fn pfl(&self) -> PFL_R

Bit 1 - Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller

pub fn asp(&self) -> ASP_R

Bit 2 - Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule

pub fn ist(&self) -> IST_R

Bits 4:7 - Isochronous Scheduling Threshold

pub fn eecp(&self) -> EECP_R

Bits 8:15 - EHCI Extended Capabilities Pointer

impl R<u16, Reg<u16, _DCIVERSION>>

pub fn dciversion(&self) -> DCIVERSION_R

Bits 0:15 - Device Controller Interface Version Number Default value is '01h', which means rev0.1.

impl R<u32, Reg<u32, _DCCPARAMS>>

pub fn den(&self) -> DEN_R

Bits 0:4 - Device Endpoint Number This field indicates the number of endpoints built into the device controller

pub fn dc(&self) -> DC_R

Bit 7 - Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device.

pub fn hc(&self) -> HC_R

Bit 8 - Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2

impl R<bool, PSE_A>

pub fn variant(&self) -> PSE_A

Get enumerated values variant

pub fn is_pse_0(&self) -> bool

Checks if the value of the field is PSE_0

pub fn is_pse_1(&self) -> bool

Checks if the value of the field is PSE_1

impl R<bool, ASE_A>

pub fn variant(&self) -> ASE_A

Get enumerated values variant

pub fn is_ase_0(&self) -> bool

Checks if the value of the field is ASE_0

pub fn is_ase_1(&self) -> bool

Checks if the value of the field is ASE_1

impl R<bool, FS_2_A>

pub fn variant(&self) -> FS_2_A

Get enumerated values variant

pub fn is_fs_2_0(&self) -> bool

Checks if the value of the field is FS_2_0

pub fn is_fs_2_1(&self) -> bool

Checks if the value of the field is FS_2_1

impl R<u8, ITC_A>

pub fn variant(&self) -> Variant<u8, ITC_A>

Get enumerated values variant

pub fn is_itc_0(&self) -> bool

Checks if the value of the field is ITC_0

pub fn is_itc_1(&self) -> bool

Checks if the value of the field is ITC_1

pub fn is_itc_2(&self) -> bool

Checks if the value of the field is ITC_2

pub fn is_itc_4(&self) -> bool

Checks if the value of the field is ITC_4

pub fn is_itc_8(&self) -> bool

Checks if the value of the field is ITC_8

pub fn is_itc_16(&self) -> bool

Checks if the value of the field is ITC_16

pub fn is_itc_32(&self) -> bool

Checks if the value of the field is ITC_32

pub fn is_itc_64(&self) -> bool

Checks if the value of the field is ITC_64

impl R<u32, Reg<u32, _USBCMD>>

pub fn rs(&self) -> RS_R

Bit 0 - Run/Stop (RS) - Read/Write

pub fn rst(&self) -> RST_R

Bit 1 - Controller Reset (RESET) - Read/Write

pub fn fs_1(&self) -> FS_1_R

Bits 2:3 - See description at bit 15

pub fn pse(&self) -> PSE_R

Bit 4 - Periodic Schedule Enable- Read/Write

pub fn ase(&self) -> ASE_R

Bit 5 - Asynchronous Schedule Enable - Read/Write

pub fn iaa(&self) -> IAA_R

Bit 6 - Interrupt on Async Advance Doorbell - Read/Write

pub fn asp(&self) -> ASP_R

Bits 8:9 - Asynchronous Schedule Park Mode Count - Read/Write

pub fn aspe(&self) -> ASPE_R

Bit 11 - Asynchronous Schedule Park Mode Enable - Read/Write

pub fn atdtw(&self) -> ATDTW_R

Bit 12 - Add dTD TripWire - Read/Write

pub fn sutw(&self) -> SUTW_R

Bit 13 - Setup TripWire - Read/Write

pub fn fs_2(&self) -> FS_2_R

Bit 15 - See also bits 3-2 Frame List Size - (Read/Write or Read Only)

pub fn itc(&self) -> ITC_R

Bits 16:23 - Interrupt Threshold Control -Read/Write

impl R<u32, Reg<u32, _USBSTS>>

pub fn ui(&self) -> UI_R

Bit 0 - USB Interrupt (USBINT) - R/WC

pub fn uei(&self) -> UEI_R

Bit 1 - USB Error Interrupt (USBERRINT) - R/WC

pub fn pci(&self) -> PCI_R

Bit 2 - Port Change Detect - R/WC

pub fn fri(&self) -> FRI_R

Bit 3 - Frame List Rollover - R/WC

pub fn sei(&self) -> SEI_R

Bit 4 - System Error- R/WC

pub fn aai(&self) -> AAI_R

Bit 5 - Interrupt on Async Advance - R/WC

pub fn uri(&self) -> URI_R

Bit 6 - USB Reset Received - R/WC

pub fn sri(&self) -> SRI_R

Bit 7 - SOF Received - R/WC

pub fn sli(&self) -> SLI_R

Bit 8 - DCSuspend - R/WC

pub fn ulpii(&self) -> ULPII_R

Bit 10 - ULPI Interrupt - R/WC

pub fn hch(&self) -> HCH_R

Bit 12 - HCHaIted - Read Only

pub fn rcl(&self) -> RCL_R

Bit 13 - Reclamation - Read Only

pub fn ps(&self) -> PS_R

Bit 14 - Periodic Schedule Status - Read Only

pub fn as_(&self) -> AS_R

Bit 15 - Asynchronous Schedule Status - Read Only

pub fn naki(&self) -> NAKI_R

Bit 16 - NAK Interrupt Bit--RO

pub fn ti0(&self) -> TI0_R

Bit 24 - General Purpose Timer Interrupt 0(GPTINT0)--R/WC

pub fn ti1(&self) -> TI1_R

Bit 25 - General Purpose Timer Interrupt 1(GPTINT1)--R/WC

impl R<u32, Reg<u32, _USBINTR>>

pub fn ue(&self) -> UE_R

Bit 0 - USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn uee(&self) -> UEE_R

Bit 1 - USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn pce(&self) -> PCE_R

Bit 2 - Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn fre(&self) -> FRE_R

Bit 3 - Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn see(&self) -> SEE_R

Bit 4 - System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn aae(&self) -> AAE_R

Bit 5 - Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn ure(&self) -> URE_R

Bit 6 - USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn sre(&self) -> SRE_R

Bit 7 - SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn sle(&self) -> SLE_R

Bit 8 - Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt

pub fn ulpie(&self) -> ULPIE_R

Bit 10 - ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn nake(&self) -> NAKE_R

Bit 16 - NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn uaie(&self) -> UAIE_R

Bit 18 - USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold

pub fn upie(&self) -> UPIE_R

Bit 19 - USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold

pub fn tie0(&self) -> TIE0_R

Bit 24 - General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt

pub fn tie1(&self) -> TIE1_R

Bit 25 - General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt

impl R<u16, FRINDEX_A>

pub fn variant(&self) -> Variant<u16, FRINDEX_A>

Get enumerated values variant

pub fn is_frindex_0(&self) -> bool

Checks if the value of the field is FRINDEX_0

pub fn is_frindex_1(&self) -> bool

Checks if the value of the field is FRINDEX_1

pub fn is_frindex_2(&self) -> bool

Checks if the value of the field is FRINDEX_2

pub fn is_frindex_3(&self) -> bool

Checks if the value of the field is FRINDEX_3

pub fn is_frindex_4(&self) -> bool

Checks if the value of the field is FRINDEX_4

pub fn is_frindex_5(&self) -> bool

Checks if the value of the field is FRINDEX_5

pub fn is_frindex_6(&self) -> bool

Checks if the value of the field is FRINDEX_6

pub fn is_frindex_7(&self) -> bool

Checks if the value of the field is FRINDEX_7

impl R<u32, Reg<u32, _FRINDEX>>

pub fn frindex(&self) -> FRINDEX_R

Bits 0:13 - Frame Index

impl R<u32, Reg<u32, _DEVICEADDR>>

pub fn usbadra(&self) -> USBADRA_R

Bit 24 - Device Address Advance

pub fn usbadr(&self) -> USBADR_R

Bits 25:31 - Device Address. These bits correspond to the USB device address

impl R<u32, Reg<u32, _PERIODICLISTBASE>>

pub fn baseadr(&self) -> BASEADR_R

Bits 12:31 - Base Address (Low)

impl R<u32, Reg<u32, _ASYNCLISTADDR>>

pub fn asybase(&self) -> ASYBASE_R

Bits 5:31 - Link Pointer Low (LPL)

impl R<u32, Reg<u32, _ENDPTLISTADDR>>

pub fn epbase(&self) -> EPBASE_R

Bits 11:31 - Endpoint List Pointer(Low)

impl R<u32, Reg<u32, _BURSTSIZE>>

pub fn rxpburst(&self) -> RXPBURST_R

Bits 0:7 - Programmable RX Burst Size

pub fn txpburst(&self) -> TXPBURST_R

Bits 8:16 - Programmable TX Burst Size

impl R<u32, Reg<u32, _TXFILLTUNING>>

pub fn txschoh(&self) -> TXSCHOH_R

Bits 0:7 - Scheduler Overhead

pub fn txschhealth(&self) -> TXSCHHEALTH_R

Bits 8:12 - Scheduler Health Counter

pub fn txfifothres(&self) -> TXFIFOTHRES_R

Bits 16:21 - FIFO Burst Threshold

impl R<u32, Reg<u32, _ENDPTNAK>>

pub fn eprn(&self) -> EPRN_R

Bits 0:7 - RX Endpoint NAK - R/WC

pub fn eptn(&self) -> EPTN_R

Bits 16:23 - TX Endpoint NAK - R/WC

impl R<u32, Reg<u32, _ENDPTNAKEN>>

pub fn eprne(&self) -> EPRNE_R

Bits 0:7 - RX Endpoint NAK Enable - R/W

pub fn eptne(&self) -> EPTNE_R

Bits 16:23 - TX Endpoint NAK Enable - R/W

impl R<bool, CF_A>

pub fn variant(&self) -> CF_A

Get enumerated values variant

pub fn is_cf_0(&self) -> bool

Checks if the value of the field is CF_0

pub fn is_cf_1(&self) -> bool

Checks if the value of the field is CF_1

impl R<u32, Reg<u32, _CONFIGFLAG>>

pub fn cf(&self) -> CF_R

Bit 0 - Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller

impl R<bool, OCA_A>

pub fn variant(&self) -> OCA_A

Get enumerated values variant

pub fn is_oca_0(&self) -> bool

Checks if the value of the field is OCA_0

pub fn is_oca_1(&self) -> bool

Checks if the value of the field is OCA_1

impl R<u8, LS_A>

pub fn variant(&self) -> LS_A

Get enumerated values variant

pub fn is_ls_0(&self) -> bool

Checks if the value of the field is LS_0

pub fn is_ls_1(&self) -> bool

Checks if the value of the field is LS_1

pub fn is_ls_2(&self) -> bool

Checks if the value of the field is LS_2

pub fn is_ls_3(&self) -> bool

Checks if the value of the field is LS_3

impl R<u8, PIC_A>

pub fn variant(&self) -> PIC_A

Get enumerated values variant

pub fn is_pic_0(&self) -> bool

Checks if the value of the field is PIC_0

pub fn is_pic_1(&self) -> bool

Checks if the value of the field is PIC_1

pub fn is_pic_2(&self) -> bool

Checks if the value of the field is PIC_2

pub fn is_pic_3(&self) -> bool

Checks if the value of the field is PIC_3

impl R<u8, PTC_A>

pub fn variant(&self) -> Variant<u8, PTC_A>

Get enumerated values variant

pub fn is_ptc_0(&self) -> bool

Checks if the value of the field is PTC_0

pub fn is_ptc_1(&self) -> bool

Checks if the value of the field is PTC_1

pub fn is_ptc_2(&self) -> bool

Checks if the value of the field is PTC_2

pub fn is_ptc_3(&self) -> bool

Checks if the value of the field is PTC_3

pub fn is_ptc_4(&self) -> bool

Checks if the value of the field is PTC_4

pub fn is_ptc_5(&self) -> bool

Checks if the value of the field is PTC_5

pub fn is_ptc_6(&self) -> bool

Checks if the value of the field is PTC_6

pub fn is_ptc_7(&self) -> bool

Checks if the value of the field is PTC_7

impl R<bool, PHCD_A>

pub fn variant(&self) -> PHCD_A

Get enumerated values variant

pub fn is_phcd_0(&self) -> bool

Checks if the value of the field is PHCD_0

pub fn is_phcd_1(&self) -> bool

Checks if the value of the field is PHCD_1

impl R<bool, PFSC_A>

pub fn variant(&self) -> PFSC_A

Get enumerated values variant

pub fn is_pfsc_0(&self) -> bool

Checks if the value of the field is PFSC_0

pub fn is_pfsc_1(&self) -> bool

Checks if the value of the field is PFSC_1

impl R<u8, PSPD_A>

pub fn variant(&self) -> PSPD_A

Get enumerated values variant

pub fn is_pspd_0(&self) -> bool

Checks if the value of the field is PSPD_0

pub fn is_pspd_1(&self) -> bool

Checks if the value of the field is PSPD_1

pub fn is_pspd_2(&self) -> bool

Checks if the value of the field is PSPD_2

pub fn is_pspd_3(&self) -> bool

Checks if the value of the field is PSPD_3

impl R<bool, PTW_A>

pub fn variant(&self) -> PTW_A

Get enumerated values variant

pub fn is_ptw_0(&self) -> bool

Checks if the value of the field is PTW_0

pub fn is_ptw_1(&self) -> bool

Checks if the value of the field is PTW_1

impl R<u32, Reg<u32, _PORTSC1>>

pub fn ccs(&self) -> CCS_R

Bit 0 - Current Connect Status-Read Only

pub fn csc(&self) -> CSC_R

Bit 1 - Connect Status Change-R/WC

pub fn pe(&self) -> PE_R

Bit 2 - Port Enabled/Disabled-Read/Write

pub fn pec(&self) -> PEC_R

Bit 3 - Port Enable/Disable Change-R/WC

pub fn oca(&self) -> OCA_R

Bit 4 - Over-current Active-Read Only

pub fn occ(&self) -> OCC_R

Bit 5 - Over-current Change-R/WC

pub fn fpr(&self) -> FPR_R

Bit 6 - Force Port Resume -Read/Write

pub fn susp(&self) -> SUSP_R

Bit 7 - Suspend - Read/Write or Read Only

pub fn pr(&self) -> PR_R

Bit 8 - Port Reset - Read/Write or Read Only

pub fn hsp(&self) -> HSP_R

Bit 9 - High-Speed Port - Read Only

pub fn ls(&self) -> LS_R

Bits 10:11 - Line Status-Read Only

pub fn pp(&self) -> PP_R

Bit 12 - Port Power (PP)-Read/Write or Read Only

pub fn po(&self) -> PO_R

Bit 13 - Port Owner-Read/Write

pub fn pic(&self) -> PIC_R

Bits 14:15 - Port Indicator Control - Read/Write

pub fn ptc(&self) -> PTC_R

Bits 16:19 - Port Test Control - Read/Write

pub fn wkcn(&self) -> WKCN_R

Bit 20 - Wake on Connect Enable (WKCNNT_E) - Read/Write

pub fn wkdc(&self) -> WKDC_R

Bit 21 - Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write

pub fn wkoc(&self) -> WKOC_R

Bit 22 - Wake on Over-current Enable (WKOC_E) - Read/Write

pub fn phcd(&self) -> PHCD_R

Bit 23 - PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write

pub fn pfsc(&self) -> PFSC_R

Bit 24 - Port Force Full Speed Connect - Read/Write

pub fn pts_2(&self) -> PTS_2_R

Bit 25 - See description at bits 31-30

pub fn pspd(&self) -> PSPD_R

Bits 26:27 - Port Speed - Read Only. This register field indicates the speed at which the port is operating.

pub fn ptw(&self) -> PTW_R

Bit 28 - Parallel Transceiver Width This bit has no effect if serial interface engine is used

pub fn sts(&self) -> STS_R

Bit 29 - Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals

pub fn pts_1(&self) -> PTS_1_R

Bits 30:31 - All USB port interface modes are listed in this field description, but not all are supported

impl R<u32, Reg<u32, _OTGSC>>

pub fn vd(&self) -> VD_R

Bit 0 - VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor.

pub fn vc(&self) -> VC_R

Bit 1 - VBUS Charge - Read/Write

pub fn ot(&self) -> OT_R

Bit 3 - OTG Termination - Read/Write

pub fn dp(&self) -> DP_R

Bit 4 - Data Pulsing - Read/Write

pub fn idpu(&self) -> IDPU_R

Bit 5 - ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]

pub fn id(&self) -> ID_R

Bit 8 - USB ID - Read Only. 0 = A device, 1 = B device

pub fn avv(&self) -> AVV_R

Bit 9 - A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold.

pub fn asv(&self) -> ASV_R

Bit 10 - A Session Valid - Read Only. Indicates VBus is above the A session valid threshold.

pub fn bsv(&self) -> BSV_R

Bit 11 - B Session Valid - Read Only. Indicates VBus is above the B session valid threshold.

pub fn bse(&self) -> BSE_R

Bit 12 - B Session End - Read Only. Indicates VBus is below the B session end threshold.

pub fn tog_1ms(&self) -> TOG_1MS_R

Bit 13 - 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond.

pub fn dps(&self) -> DPS_R

Bit 14 - Data Bus Pulsing Status - Read Only

pub fn idis(&self) -> IDIS_R

Bit 16 - USB ID Interrupt Status - Read/Write

pub fn avvis(&self) -> AVVIS_R

Bit 17 - A VBus Valid Interrupt Status - Read/Write to Clear

pub fn asvis(&self) -> ASVIS_R

Bit 18 - A Session Valid Interrupt Status - Read/Write to Clear

pub fn bsvis(&self) -> BSVIS_R

Bit 19 - B Session Valid Interrupt Status - Read/Write to Clear

pub fn bseis(&self) -> BSEIS_R

Bit 20 - B Session End Interrupt Status - Read/Write to Clear

pub fn status_1ms(&self) -> STATUS_1MS_R

Bit 21 - 1 millisecond timer Interrupt Status - Read/Write to Clear

pub fn dpis(&self) -> DPIS_R

Bit 22 - Data Pulse Interrupt Status - Read/Write to Clear

pub fn idie(&self) -> IDIE_R

Bit 24 - USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt.

pub fn avvie(&self) -> AVVIE_R

Bit 25 - A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt.

pub fn asvie(&self) -> ASVIE_R

Bit 26 - A Session Valid Interrupt Enable - Read/Write

pub fn bsvie(&self) -> BSVIE_R

Bit 27 - B Session Valid Interrupt Enable - Read/Write

pub fn bseie(&self) -> BSEIE_R

Bit 28 - B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt.

pub fn en_1ms(&self) -> EN_1MS_R

Bit 29 - 1 millisecond timer Interrupt Enable - Read/Write

pub fn dpie(&self) -> DPIE_R

Bit 30 - Data Pulse Interrupt Enable

impl R<u8, CM_A>

pub fn variant(&self) -> Variant<u8, CM_A>

Get enumerated values variant

pub fn is_cm_0(&self) -> bool

Checks if the value of the field is CM_0

pub fn is_cm_2(&self) -> bool

Checks if the value of the field is CM_2

pub fn is_cm_3(&self) -> bool

Checks if the value of the field is CM_3

impl R<bool, ES_A>

pub fn variant(&self) -> ES_A

Get enumerated values variant

pub fn is_es_0(&self) -> bool

Checks if the value of the field is ES_0

pub fn is_es_1(&self) -> bool

Checks if the value of the field is ES_1

impl R<bool, SLOM_A>

pub fn variant(&self) -> SLOM_A

Get enumerated values variant

pub fn is_slom_0(&self) -> bool

Checks if the value of the field is SLOM_0

pub fn is_slom_1(&self) -> bool

Checks if the value of the field is SLOM_1

impl R<u32, Reg<u32, _USBMODE>>

pub fn cm(&self) -> CM_R

Bits 0:1 - Controller Mode - R/WO

pub fn es(&self) -> ES_R

Bit 2 - Endian Select - Read/Write

pub fn slom(&self) -> SLOM_R

Bit 3 - Setup Lockout Mode

pub fn sdis(&self) -> SDIS_R

Bit 4 - Stream Disable Mode

impl R<u32, Reg<u32, _ENDPTSETUPSTAT>>

pub fn endptsetupstat(&self) -> ENDPTSETUPSTAT_R

Bits 0:15 - Setup Endpoint Status

impl R<u32, Reg<u32, _ENDPTPRIME>>

pub fn perb(&self) -> PERB_R

Bits 0:7 - Prime Endpoint Receive Buffer - R/WS

pub fn petb(&self) -> PETB_R

Bits 16:23 - Prime Endpoint Transmit Buffer - R/WS

impl R<u32, Reg<u32, _ENDPTFLUSH>>

pub fn ferb(&self) -> FERB_R

Bits 0:7 - Flush Endpoint Receive Buffer - R/WS

pub fn fetb(&self) -> FETB_R

Bits 16:23 - Flush Endpoint Transmit Buffer - R/WS

impl R<u32, Reg<u32, _ENDPTSTAT>>

pub fn erbr(&self) -> ERBR_R

Bits 0:7 - Endpoint Receive Buffer Ready -- Read Only

pub fn etbr(&self) -> ETBR_R

Bits 16:23 - Endpoint Transmit Buffer Ready -- Read Only

impl R<u32, Reg<u32, _ENDPTCOMPLETE>>

pub fn erce(&self) -> ERCE_R

Bits 0:7 - Endpoint Receive Complete Event - RW/C

pub fn etce(&self) -> ETCE_R

Bits 16:23 - Endpoint Transmit Complete Event - R/WC

impl R<u32, Reg<u32, _ENDPTCTRL0>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point.

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 1 Enabled Endpoint0 is always enabled.

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point.

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 1 Enabled Endpoint0 is always enabled.

impl R<u32, Reg<u32, _ENDPTCTRL1>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl R<u32, Reg<u32, _ENDPTCTRL2>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl R<u32, Reg<u32, _ENDPTCTRL3>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl R<u32, Reg<u32, _ENDPTCTRL4>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl R<u32, Reg<u32, _ENDPTCTRL5>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl R<u32, Reg<u32, _ENDPTCTRL6>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

impl R<u32, Reg<u32, _ENDPTCTRL7>>

pub fn rxs(&self) -> RXS_R

Bit 0 - RX Endpoint Stall - Read/Write 0 End Point OK

pub fn rxd(&self) -> RXD_R

Bit 1 - RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero

pub fn rxt(&self) -> RXT_R

Bits 2:3 - RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn rxi(&self) -> RXI_R

Bit 5 - RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero

pub fn rxr(&self) -> RXR_R

Bit 6 - RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device

pub fn rxe(&self) -> RXE_R

Bit 7 - RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

pub fn txs(&self) -> TXS_R

Bit 16 - TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared

pub fn txd(&self) -> TXD_R

Bit 17 - TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0

pub fn txt(&self) -> TXT_R

Bits 18:19 - TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt

pub fn txi(&self) -> TXI_R

Bit 21 - TX Data Toggle Inhibit 0 PID Sequencing Enabled

pub fn txr(&self) -> TXR_R

Bit 22 - TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device

pub fn txe(&self) -> TXE_R

Bit 23 - TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.