Struct imxrt1062_tmr1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u16, Reg<u16, _COMP1>>

pub fn comparison_1(&mut self) -> COMPARISON_1_W

Bits 0:15 - Comparison Value 1

impl W<u16, Reg<u16, _COMP2>>

pub fn comparison_2(&mut self) -> COMPARISON_2_W

Bits 0:15 - Comparison Value 2

impl W<u16, Reg<u16, _CAPT>>

pub fn capture(&mut self) -> CAPTURE_W

Bits 0:15 - Capture Value

impl W<u16, Reg<u16, _LOAD>>

pub fn load(&mut self) -> LOAD_W

Bits 0:15 - Timer Load Register

impl W<u16, Reg<u16, _HOLD>>

pub fn hold(&mut self) -> HOLD_W

Bits 0:15 - This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read

impl W<u16, Reg<u16, _CNTR>>

pub fn counter(&mut self) -> COUNTER_W

Bits 0:15 - This read/write register is the counter for the corresponding channel in a timer module.

impl W<u16, Reg<u16, _CTRL>>

pub fn outmode(&mut self) -> OUTMODE_W

Bits 0:2 - Output Mode

pub fn coinit(&mut self) -> COINIT_W

Bit 3 - Co-Channel Initialization

pub fn dir(&mut self) -> DIR_W

Bit 4 - Count Direction

pub fn length(&mut self) -> LENGTH_W

Bit 5 - Count Length

pub fn once(&mut self) -> ONCE_W

Bit 6 - Count Once

pub fn scs(&mut self) -> SCS_W

Bits 7:8 - Secondary Count Source

pub fn pcs(&mut self) -> PCS_W

Bits 9:12 - Primary Count Source

pub fn cm(&mut self) -> CM_W

Bits 13:15 - Count Mode

impl W<u16, Reg<u16, _SCTRL>>

pub fn oen(&mut self) -> OEN_W

Bit 0 - Output Enable

pub fn ops(&mut self) -> OPS_W

Bit 1 - Output Polarity Select

pub fn force(&mut self) -> FORCE_W

Bit 2 - Force OFLAG Output

pub fn val(&mut self) -> VAL_W

Bit 3 - Forced OFLAG Value

pub fn eeof(&mut self) -> EEOF_W

Bit 4 - Enable External OFLAG Force

pub fn mstr(&mut self) -> MSTR_W

Bit 5 - Master Mode

pub fn capture_mode(&mut self) -> CAPTURE_MODE_W

Bits 6:7 - Input Capture Mode

pub fn ips(&mut self) -> IPS_W

Bit 9 - Input Polarity Select

pub fn iefie(&mut self) -> IEFIE_W

Bit 10 - Input Edge Flag Interrupt Enable

pub fn ief(&mut self) -> IEF_W

Bit 11 - Input Edge Flag

pub fn tofie(&mut self) -> TOFIE_W

Bit 12 - Timer Overflow Flag Interrupt Enable

pub fn tof(&mut self) -> TOF_W

Bit 13 - Timer Overflow Flag

pub fn tcfie(&mut self) -> TCFIE_W

Bit 14 - Timer Compare Flag Interrupt Enable

pub fn tcf(&mut self) -> TCF_W

Bit 15 - Timer Compare Flag

impl W<u16, Reg<u16, _CMPLD1>>

pub fn comparator_load_1(&mut self) -> COMPARATOR_LOAD_1_W

Bits 0:15 - This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module

impl W<u16, Reg<u16, _CMPLD2>>

pub fn comparator_load_2(&mut self) -> COMPARATOR_LOAD_2_W

Bits 0:15 - This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module

impl W<u16, Reg<u16, _CSCTRL>>

pub fn cl1(&mut self) -> CL1_W

Bits 0:1 - Compare Load Control 1

pub fn cl2(&mut self) -> CL2_W

Bits 2:3 - Compare Load Control 2

pub fn tcf1(&mut self) -> TCF1_W

Bit 4 - Timer Compare 1 Interrupt Flag

pub fn tcf2(&mut self) -> TCF2_W

Bit 5 - Timer Compare 2 Interrupt Flag

pub fn tcf1en(&mut self) -> TCF1EN_W

Bit 6 - Timer Compare 1 Interrupt Enable

pub fn tcf2en(&mut self) -> TCF2EN_W

Bit 7 - Timer Compare 2 Interrupt Enable

pub fn tci(&mut self) -> TCI_W

Bit 10 - Triggered Count Initialization Control

pub fn roc(&mut self) -> ROC_W

Bit 11 - Reload on Capture

pub fn alt_load(&mut self) -> ALT_LOAD_W

Bit 12 - Alternative Load Enable

pub fn fault(&mut self) -> FAULT_W

Bit 13 - Fault Enable

pub fn dbg_en(&mut self) -> DBG_EN_W

Bits 14:15 - Debug Actions Enable

impl W<u16, Reg<u16, _FILT>>

pub fn filt_per(&mut self) -> FILT_PER_W

Bits 0:7 - Input Filter Sample Period

pub fn filt_cnt(&mut self) -> FILT_CNT_W

Bits 8:10 - Input Filter Sample Count

impl W<u16, Reg<u16, _DMA>>

pub fn iefde(&mut self) -> IEFDE_W

Bit 0 - Input Edge Flag DMA Enable

pub fn cmpld1de(&mut self) -> CMPLD1DE_W

Bit 1 - Comparator Preload Register 1 DMA Enable

pub fn cmpld2de(&mut self) -> CMPLD2DE_W

Bit 2 - Comparator Preload Register 2 DMA Enable

impl W<u16, Reg<u16, _ENBL>>

pub fn enbl(&mut self) -> ENBL_W

Bits 0:3 - Timer Channel Enable