Struct imxrt1062_system_control::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _ACTLR>>

pub fn disfold(&mut self) -> DISFOLD_W

Bit 2 - Disables folding of IT instructions.

pub fn fpexcodis(&mut self) -> FPEXCODIS_W

Bit 10 - Disables FPU exception outputs.

pub fn disramode(&mut self) -> DISRAMODE_W

Bit 11 - Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions.

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W

Bit 12 - Disables ITM and DWT ATB flush.

pub fn disbtacread(&mut self) -> DISBTACREAD_W

Bit 13 - Disables BTAC read.

pub fn disbtacalloc(&mut self) -> DISBTACALLOC_W

Bit 14 - Disables BTAC allocate.

pub fn discritaxirur(&mut self) -> DISCRITAXIRUR_W

Bit 15 - Disables critical AXI Read-Under-Read.

pub fn disdi(&mut self) -> DISDI_W

Bits 16:20 - Disables dual-issued.

pub fn disissch1(&mut self) -> DISISSCH1_W

Bits 21:25 - Disables dual-issued.

pub fn disdynadd(&mut self) -> DISDYNADD_W

Bit 26 - Disables dynamic allocation of ADD and SUB instructions

pub fn discritaxiruw(&mut self) -> DISCRITAXIRUW_W

Bit 27 - Disables critical AXI read-under-write

pub fn disfpuissopt(&mut self) -> DISFPUISSOPT_W

Bit 28 - Disables critical AXI read-under-write

impl W<u32, Reg<u32, _ICSR>>

pub fn pendstclr(&mut self) -> PENDSTCLR_W

Bit 25 - SysTick exception clear-pending bit

pub fn pendstset(&mut self) -> PENDSTSET_W

Bit 26 - SysTick exception set-pending bit

pub fn pendsvclr(&mut self) -> PENDSVCLR_W

Bit 27 - PendSV clear-pending bit

pub fn pendsvset(&mut self) -> PENDSVSET_W

Bit 28 - PendSV set-pending bit

pub fn nmipendset(&mut self) -> NMIPENDSET_W

Bit 31 - NMI set-pending bit

impl W<u32, Reg<u32, _VTOR>>

pub fn tbloff(&mut self) -> TBLOFF_W

Bits 7:31 - Vector table base offset

impl W<u32, Reg<u32, _AIRCR>>

pub fn vectreset(&mut self) -> VECTRESET_W

Bit 0 - Writing 1 to this bit causes a local system reset

pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W

Bit 1 - Writing 1 to this bit clears all active state information for fixed and configurable exceptions.

pub fn sysresetreq(&mut self) -> SYSRESETREQ_W

Bit 2 - System reset request

pub fn prigroup(&mut self) -> PRIGROUP_W

Bits 8:10 - Interrupt priority grouping field. This field determines the split of group priority from subpriority.

pub fn vectkey(&mut self) -> VECTKEY_W

Bits 16:31 - Register key

impl W<u32, Reg<u32, _SCR>>

pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W

Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode

pub fn sleepdeep(&mut self) -> SLEEPDEEP_W

Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode

pub fn sevonpend(&mut self) -> SEVONPEND_W

Bit 4 - Send Event on Pending bit

impl W<u32, Reg<u32, _CCR>>

pub fn nonbasethrdena(&mut self) -> NONBASETHRDENA_W

Bit 0 - Indicates how the processor enters Thread mode

pub fn usersetmpend(&mut self) -> USERSETMPEND_W

Bit 1 - Enables unprivileged software access to the STIR

pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W

Bit 3 - Enables unaligned access traps

pub fn div_0_trp(&mut self) -> DIV_0_TRP_W

Bit 4 - Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0

pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W

Bit 8 - Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.

pub fn stkalign(&mut self) -> STKALIGN_W

Bit 9 - Indicates stack alignment on exception entry

pub fn dc(&mut self) -> DC_W

Bit 16 - Enables L1 data cache.

pub fn ic(&mut self) -> IC_W

Bit 17 - Enables L1 instruction cache.

impl W<u32, Reg<u32, _SHPR1>>

pub fn pri_4(&mut self) -> PRI_4_W

Bits 0:7 - Priority of system handler 4, MemManage

pub fn pri_5(&mut self) -> PRI_5_W

Bits 8:15 - Priority of system handler 5, BusFault

pub fn pri_6(&mut self) -> PRI_6_W

Bits 16:23 - Priority of system handler 6, UsageFault

impl W<u32, Reg<u32, _SHPR2>>

pub fn pri_11(&mut self) -> PRI_11_W

Bits 24:31 - Priority of system handler 11, SVCall

impl W<u32, Reg<u32, _SHPR3>>

pub fn pri_14(&mut self) -> PRI_14_W

Bits 16:23 - Priority of system handler 14, PendSV

pub fn pri_15(&mut self) -> PRI_15_W

Bits 24:31 - Priority of system handler 15, SysTick exception

impl W<u32, Reg<u32, _SHCSR>>

pub fn memfaultact(&mut self) -> MEMFAULTACT_W

Bit 0 - MemManage exception active bit

pub fn busfaultact(&mut self) -> BUSFAULTACT_W

Bit 1 - BusFault exception active bit

pub fn usgfaultact(&mut self) -> USGFAULTACT_W

Bit 3 - UsageFault exception active bit

pub fn svcallact(&mut self) -> SVCALLACT_W

Bit 7 - SVCall active bit

pub fn monitoract(&mut self) -> MONITORACT_W

Bit 8 - Debug monitor active bit

pub fn pendsvact(&mut self) -> PENDSVACT_W

Bit 10 - PendSV exception active bit

pub fn systickact(&mut self) -> SYSTICKACT_W

Bit 11 - SysTick exception active bit

pub fn usgfaultpended(&mut self) -> USGFAULTPENDED_W

Bit 12 - UsageFault exception pending bit

pub fn memfaultpended(&mut self) -> MEMFAULTPENDED_W

Bit 13 - MemManage exception pending bit

pub fn busfaultpended(&mut self) -> BUSFAULTPENDED_W

Bit 14 - BusFault exception pending bit

pub fn svcallpended(&mut self) -> SVCALLPENDED_W

Bit 15 - SVCall pending bit

pub fn memfaultena(&mut self) -> MEMFAULTENA_W

Bit 16 - MemManage enable bit

pub fn busfaultena(&mut self) -> BUSFAULTENA_W

Bit 17 - BusFault enable bit

pub fn usgfaultena(&mut self) -> USGFAULTENA_W

Bit 18 - UsageFault enable bit

impl W<u32, Reg<u32, _CFSR>>

pub fn iaccviol(&mut self) -> IACCVIOL_W

Bit 0 - Instruction access violation flag

pub fn daccviol(&mut self) -> DACCVIOL_W

Bit 1 - Data access violation flag

pub fn munstkerr(&mut self) -> MUNSTKERR_W

Bit 3 - MemManage fault on unstacking for a return from exception

pub fn mstkerr(&mut self) -> MSTKERR_W

Bit 4 - MemManage fault on stacking for exception entry

pub fn mlsperr(&mut self) -> MLSPERR_W

Bit 5 - MemManage fault occurred during floating-point lazy state preservation

pub fn mmarvalid(&mut self) -> MMARVALID_W

Bit 7 - MemManage Fault Address Register (MMFAR) valid flag

pub fn ibuserr(&mut self) -> IBUSERR_W

Bit 8 - Instruction bus error

pub fn preciserr(&mut self) -> PRECISERR_W

Bit 9 - Precise data bus error

pub fn impreciserr(&mut self) -> IMPRECISERR_W

Bit 10 - Imprecise data bus error

pub fn unstkerr(&mut self) -> UNSTKERR_W

Bit 11 - BusFault on unstacking for a return from exception

pub fn stkerr(&mut self) -> STKERR_W

Bit 12 - BusFault on stacking for exception entry

pub fn lsperr(&mut self) -> LSPERR_W

Bit 13 - Bus fault occurred during floating-point lazy state preservation

pub fn bfarvalid(&mut self) -> BFARVALID_W

Bit 15 - BusFault Address Register (BFAR) valid flag

pub fn undefinstr(&mut self) -> UNDEFINSTR_W

Bit 16 - Undefined instruction UsageFault

pub fn invstate(&mut self) -> INVSTATE_W

Bit 17 - Invalid state UsageFault

pub fn invpc(&mut self) -> INVPC_W

Bit 18 - Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN

pub fn nocp(&mut self) -> NOCP_W

Bit 19 - No coprocessor UsageFault

pub fn unaligned(&mut self) -> UNALIGNED_W

Bit 24 - Unaligned access UsageFault

pub fn divbyzero(&mut self) -> DIVBYZERO_W

Bit 25 - Divide by zero UsageFault

impl W<u32, Reg<u32, _HFSR>>

pub fn vecttbl(&mut self) -> VECTTBL_W

Bit 1 - Indicates a BusFault on a vector table read during exception processing.

pub fn forced(&mut self) -> FORCED_W

Bit 30 - Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled.

pub fn debugevt(&mut self) -> DEBUGEVT_W

Bit 31 - Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.

impl W<u32, Reg<u32, _DFSR>>

pub fn halted(&mut self) -> HALTED_W

Bit 0 - Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1.

pub fn bkpt(&mut self) -> BKPT_W

Bit 1 - Debug event generated by BKPT instruction execution or a breakpoint match in FPB

pub fn dwttrap(&mut self) -> DWTTRAP_W

Bit 2 - Debug event generated by the DWT

pub fn vcatch(&mut self) -> VCATCH_W

Bit 3 - Indicates triggering of a Vector catch

pub fn external(&mut self) -> EXTERNAL_W

Bit 4 - Debug event generated because of the assertion of an external debug request

impl W<u32, Reg<u32, _MMFAR>>

pub fn address(&mut self) -> ADDRESS_W

Bits 0:31 - Address of MemManage fault location

impl W<u32, Reg<u32, _BFAR>>

pub fn address(&mut self) -> ADDRESS_W

Bits 0:31 - Address of the BusFault location

impl W<u32, Reg<u32, _CSSELR>>

pub fn ind(&mut self) -> IND_W

Bit 0 - Instruction not data bit

pub fn level(&mut self) -> LEVEL_W

Bits 1:3 - Cache level of required cache

impl W<u32, Reg<u32, _CPACR>>

pub fn cp0(&mut self) -> CP0_W

Bits 0:1 - Access privileges for coprocessor 0.

pub fn cp1(&mut self) -> CP1_W

Bits 2:3 - Access privileges for coprocessor 1.

pub fn cp2(&mut self) -> CP2_W

Bits 4:5 - Access privileges for coprocessor 2.

pub fn cp3(&mut self) -> CP3_W

Bits 6:7 - Access privileges for coprocessor 3.

pub fn cp4(&mut self) -> CP4_W

Bits 8:9 - Access privileges for coprocessor 4.

pub fn cp5(&mut self) -> CP5_W

Bits 10:11 - Access privileges for coprocessor 5.

pub fn cp6(&mut self) -> CP6_W

Bits 12:13 - Access privileges for coprocessor 6.

pub fn cp7(&mut self) -> CP7_W

Bits 14:15 - Access privileges for coprocessor 7.

pub fn cp10(&mut self) -> CP10_W

Bits 20:21 - Access privileges for coprocessor 10.

pub fn cp11(&mut self) -> CP11_W

Bits 22:23 - Access privileges for coprocessor 11.

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W

Bits 0:8 - Indicates the interrupt to be triggered

impl W<u32, Reg<u32, _ICIALLU>>

pub fn iciallu(&mut self) -> ICIALLU_W

Bits 0:31 - I-cache invalidate all to PoU

impl W<u32, Reg<u32, _ICIMVAU>>

pub fn icimvau(&mut self) -> ICIMVAU_W

Bits 0:31 - I-cache invalidate by MVA to PoU

impl W<u32, Reg<u32, _DCIMVAC>>

pub fn dcimvac(&mut self) -> DCIMVAC_W

Bits 0:31 - D-cache invalidate by MVA to PoC

impl W<u32, Reg<u32, _DCISW>>

pub fn dcisw(&mut self) -> DCISW_W

Bits 0:31 - D-cache invalidate by set-way

impl W<u32, Reg<u32, _DCCMVAU>>

pub fn dccmvau(&mut self) -> DCCMVAU_W

Bits 0:31 - D-cache clean by MVA to PoU

impl W<u32, Reg<u32, _DCCMVAC>>

pub fn dccmvac(&mut self) -> DCCMVAC_W

Bits 0:31 - D-cache clean by MVA to PoC

impl W<u32, Reg<u32, _DCCSW>>

pub fn dccsw(&mut self) -> DCCSW_W

Bits 0:31 - D-cache clean by set-way

impl W<u32, Reg<u32, _DCCIMVAC>>

pub fn dccimvac(&mut self) -> DCCIMVAC_W

Bits 0:31 - D-cache clean and invalidate by MVA to PoC

impl W<u32, Reg<u32, _DCCISW>>

pub fn dccisw(&mut self) -> DCCISW_W

Bits 0:31 - D-cache clean and invalidate by set-way

impl W<u32, Reg<u32, _CM7_ITCMCR>>

pub fn en(&mut self) -> EN_W

Bit 0 - TCM enable. When a TCM is disabled all accesses are made to the AXIM interface.

pub fn rmw(&mut self) -> RMW_W

Bit 1 - Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence.

pub fn reten(&mut self) -> RETEN_W

Bit 2 - Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access.

impl W<u32, Reg<u32, _CM7_DTCMCR>>

pub fn en(&mut self) -> EN_W

Bit 0 - TCM enable. When a TCM is disabled all accesses are made to the AXIM interface.

pub fn rmw(&mut self) -> RMW_W

Bit 1 - Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence.

pub fn reten(&mut self) -> RETEN_W

Bit 2 - Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access.

impl W<u32, Reg<u32, _CM7_AHBPCR>>

pub fn en(&mut self) -> EN_W

Bit 0 - AHBP enable.

impl W<u32, Reg<u32, _CM7_CACR>>

pub fn siwt(&mut self) -> SIWT_W

Bit 0 - Shared cacheable-is-WT for data cache. Enables limited cache coherency usage.

pub fn eccdis(&mut self) -> ECCDIS_W

Bit 1 - Enables ECC in the instruction and data cache.

pub fn forcewt(&mut self) -> FORCEWT_W

Bit 2 - Enables Force Write-Through in the data cache.

impl W<u32, Reg<u32, _CM7_AHBSCR>>

pub fn ctl(&mut self) -> CTL_W

Bits 0:1 - AHBS prioritization control.

pub fn tpri(&mut self) -> TPRI_W

Bits 2:10 - Threshold execution priority for AHBS traffic demotion.

pub fn initcount(&mut self) -> INITCOUNT_W

Bits 11:15 - Fairness counter initialization value.

impl W<u32, Reg<u32, _CM7_ABFSR>>

pub fn itcm(&mut self) -> ITCM_W

Bit 0 - Asynchronous fault on ITCM interface.

pub fn dtcm(&mut self) -> DTCM_W

Bit 1 - Asynchronous fault on DTCM interface.

pub fn ahbp(&mut self) -> AHBP_W

Bit 2 - Asynchronous fault on AHBP interface.

pub fn axim(&mut self) -> AXIM_W

Bit 3 - Asynchronous fault on AXIM interface.

pub fn eppb(&mut self) -> EPPB_W

Bit 4 - Asynchronous fault on EPPB interface.

pub fn aximtype(&mut self) -> AXIMTYPE_W

Bits 8:9 - Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1.