Type Definition imxrt1062_snvs::hpcomr::W

type W = W<u32, HPCOMR>;

Writer for register HPCOMR

Methods

impl W

pub fn ssm_st(&mut self) -> SSM_ST_W

Bit 0 - SSM State Transition Transition state of the system security monitor

pub fn ssm_st_dis(&mut self) -> SSM_ST_DIS_W

Bit 1 - SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state

pub fn ssm_sfns_dis(&mut self) -> SSM_SFNS_DIS_W

Bit 2 - SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state

pub fn lp_swr(&mut self) -> LP_SWR_W

Bit 4 - LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set

pub fn lp_swr_dis(&mut self) -> LP_SWR_DIS_W

Bit 5 - LP Software Reset Disable When set, disables the LP software reset

pub fn sw_sv(&mut self) -> SW_SV_W

Bit 8 - Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation

pub fn sw_fsv(&mut self) -> SW_FSV_W

Bit 9 - Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation

pub fn sw_lpsv(&mut self) -> SW_LPSV_W

Bit 10 - LP Software Security Violation When set, SNVS_LP treats this bit as a security violation

pub fn prog_zmk(&mut self) -> PROG_ZMK_W

Bit 12 - Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism

pub fn mks_en(&mut self) -> MKS_EN_W

Bit 13 - Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default

pub fn hac_en(&mut self) -> HAC_EN_W

Bit 16 - High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state

pub fn hac_load(&mut self) -> HAC_LOAD_W

Bit 17 - High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register

pub fn hac_clear(&mut self) -> HAC_CLEAR_W

Bit 18 - High Assurance Counter Clear When set, it clears the High Assurance Counter Register

pub fn hac_stop(&mut self) -> HAC_STOP_W

Bit 19 - High Assurance Counter Stop This bit can be set only when SSM is in soft fail state

pub fn npswa_en(&mut self) -> NPSWA_EN_W

Bit 31 - Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only