Struct imxrt1062_semc::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _MCR>>

pub fn swrst(&mut self) -> SWRST_W

Bit 0 - Software Reset

pub fn mdis(&mut self) -> MDIS_W

Bit 1 - Module Disable

pub fn dqsmd(&mut self) -> DQSMD_W

Bit 2 - DQS (read strobe) mode

pub fn wpol0(&mut self) -> WPOL0_W

Bit 6 - WAIT/RDY# polarity for NOR/PSRAM

pub fn wpol1(&mut self) -> WPOL1_W

Bit 7 - WAIT/RDY# polarity for NAND

pub fn dqssel(&mut self) -> DQSSEL_W

Bit 10 - Select DQS source when DQSMD and DLLSEL both set.

pub fn dllsel(&mut self) -> DLLSEL_W

Bit 11 - Select DLL delay chain clock input.

pub fn cto(&mut self) -> CTO_W

Bits 16:23 - Command Execution timeout cycles

pub fn bto(&mut self) -> BTO_W

Bits 24:28 - Bus timeout cycles

impl W<u32, Reg<u32, _IOCR>>

pub fn mux_a8(&mut self) -> MUX_A8_W

Bits 0:2 - SEMC_A8 output selection

pub fn mux_csx0(&mut self) -> MUX_CSX0_W

Bits 3:5 - SEMC_CSX0 output selection

pub fn mux_csx1(&mut self) -> MUX_CSX1_W

Bits 6:8 - SEMC_CSX1 output selection

pub fn mux_csx2(&mut self) -> MUX_CSX2_W

Bits 9:11 - SEMC_CSX2 output selection

pub fn mux_csx3(&mut self) -> MUX_CSX3_W

Bits 12:14 - SEMC_CSX3 output selection

pub fn mux_rdy(&mut self) -> MUX_RDY_W

Bits 15:17 - SEMC_RDY function selection

pub fn mux_clkx0(&mut self) -> MUX_CLKX0_W

Bit 24 - SEMC_CLKX0 function selection

pub fn mux_clkx1(&mut self) -> MUX_CLKX1_W

Bit 25 - SEMC_CLKX1 function selection

impl W<u32, Reg<u32, _BMCR0>>

pub fn wqos(&mut self) -> WQOS_W

Bits 0:3 - Weight of QoS

pub fn wage(&mut self) -> WAGE_W

Bits 4:7 - Weight of Aging

pub fn wsh(&mut self) -> WSH_W

Bits 8:15 - Weight of Slave Hit (no read/write switch)

pub fn wrws(&mut self) -> WRWS_W

Bits 16:23 - Weight of Slave Hit (Read/Write switch)

impl W<u32, Reg<u32, _BMCR1>>

pub fn wqos(&mut self) -> WQOS_W

Bits 0:3 - Weight of QoS

pub fn wage(&mut self) -> WAGE_W

Bits 4:7 - Weight of Aging

pub fn wph(&mut self) -> WPH_W

Bits 8:15 - Weight of Page Hit

pub fn wrws(&mut self) -> WRWS_W

Bits 16:23 - Weight of Read/Write switch

pub fn wbr(&mut self) -> WBR_W

Bits 24:31 - Weight of Bank Rotation

impl W<u32, Reg<u32, _BR0>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR1>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR2>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR3>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR4>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR5>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR6>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR7>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _BR8>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn ms(&mut self) -> MS_W

Bits 1:5 - Memory size

pub fn ba(&mut self) -> BA_W

Bits 12:31 - Base Address

impl W<u32, Reg<u32, _DLLCR>>

pub fn dllen(&mut self) -> DLLEN_W

Bit 0 - DLL calibration enable.

pub fn dllreset(&mut self) -> DLLRESET_W

Bit 1 - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).

pub fn slvdlytarget(&mut self) -> SLVDLYTARGET_W

Bits 3:6 - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (ipgclock).

pub fn ovrden(&mut self) -> OVRDEN_W

Bit 8 - Slave clock delay line delay cell number selection override enable.

pub fn ovrdval(&mut self) -> OVRDVAL_W

Bits 9:14 - Slave clock delay line delay cell number selection override value.

impl W<u32, Reg<u32, _INTEN>>

pub fn ipcmddoneen(&mut self) -> IPCMDDONEEN_W

Bit 0 - IP command done interrupt enable

pub fn ipcmderren(&mut self) -> IPCMDERREN_W

Bit 1 - IP command error interrupt enable

pub fn axicmderren(&mut self) -> AXICMDERREN_W

Bit 2 - AXI command error interrupt enable

pub fn axibuserren(&mut self) -> AXIBUSERREN_W

Bit 3 - AXI bus error interrupt enable

pub fn ndpageenden(&mut self) -> NDPAGEENDEN_W

Bit 4 - This bit enable/disable the NDPAGEEND interrupt generation.

pub fn ndnopenden(&mut self) -> NDNOPENDEN_W

Bit 5 - This bit enable/disable the NDNOPEND interrupt generation.

impl W<u32, Reg<u32, _INTR>>

pub fn ipcmddone(&mut self) -> IPCMDDONE_W

Bit 0 - IP command normal done interrupt

pub fn ipcmderr(&mut self) -> IPCMDERR_W

Bit 1 - IP command error done interrupt

pub fn axicmderr(&mut self) -> AXICMDERR_W

Bit 2 - AXI command error interrupt

pub fn axibuserr(&mut self) -> AXIBUSERR_W

Bit 3 - AXI bus error interrupt

pub fn ndpageend(&mut self) -> NDPAGEEND_W

Bit 4 - This interrupt is generated when the last address of one page in NAND device is written by AXI command

pub fn ndnopend(&mut self) -> NDNOPEND_W

Bit 5 - This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface.

impl W<u32, Reg<u32, _SDRAMCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Port Size

pub fn bl(&mut self) -> BL_W

Bits 4:6 - Burst Length

pub fn col8(&mut self) -> COL8_W

Bit 7 - Column 8 selection bit

pub fn col(&mut self) -> COL_W

Bits 8:9 - Column address bit number

pub fn cl(&mut self) -> CL_W

Bits 10:11 - CAS Latency

pub fn bank2(&mut self) -> BANK2_W

Bit 14 - 2 Bank selection bit

impl W<u32, Reg<u32, _SDRAMCR1>>

pub fn pre2act(&mut self) -> PRE2ACT_W

Bits 0:3 - PRECHARGE to ACT/Refresh wait time

pub fn act2rw(&mut self) -> ACT2RW_W

Bits 4:7 - ACT to Read/Write wait time

pub fn rfrc(&mut self) -> RFRC_W

Bits 8:12 - Refresh recovery time

pub fn wrc(&mut self) -> WRC_W

Bits 13:15 - Write recovery time

pub fn ckeoff(&mut self) -> CKEOFF_W

Bits 16:19 - CKE OFF minimum time

pub fn act2pre(&mut self) -> ACT2PRE_W

Bits 20:23 - ACT to Precharge minimum time

impl W<u32, Reg<u32, _SDRAMCR2>>

pub fn srrc(&mut self) -> SRRC_W

Bits 0:7 - Self Refresh Recovery time

pub fn ref2ref(&mut self) -> REF2REF_W

Bits 8:15 - Refresh to Refresh wait time

pub fn act2act(&mut self) -> ACT2ACT_W

Bits 16:23 - ACT to ACT wait time

pub fn ito(&mut self) -> ITO_W

Bits 24:31 - SDRAM Idle timeout

impl W<u32, Reg<u32, _SDRAMCR3>>

pub fn ren(&mut self) -> REN_W

Bit 0 - Refresh enable

pub fn rebl(&mut self) -> REBL_W

Bits 1:3 - Refresh burst length

pub fn prescale(&mut self) -> PRESCALE_W

Bits 8:15 - Prescaler timer period

pub fn rt(&mut self) -> RT_W

Bits 16:23 - Refresh timer period

pub fn ut(&mut self) -> UT_W

Bits 24:31 - Refresh urgent threshold

impl W<u32, Reg<u32, _NANDCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Port Size

pub fn syncen(&mut self) -> SYNCEN_W

Bit 1 - Select NAND controller mode.

pub fn bl(&mut self) -> BL_W

Bits 4:6 - Burst Length

pub fn edo(&mut self) -> EDO_W

Bit 7 - EDO mode enabled

pub fn col(&mut self) -> COL_W

Bits 8:10 - Column address bit number

impl W<u32, Reg<u32, _NANDCR1>>

pub fn ces(&mut self) -> CES_W

Bits 0:3 - CE setup time

pub fn ceh(&mut self) -> CEH_W

Bits 4:7 - CE hold time

pub fn wel(&mut self) -> WEL_W

Bits 8:11 - WE# LOW time

pub fn weh(&mut self) -> WEH_W

Bits 12:15 - WE# HIGH time

pub fn rel(&mut self) -> REL_W

Bits 16:19 - RE# LOW time

pub fn reh(&mut self) -> REH_W

Bits 20:23 - RE# HIGH time

pub fn ta(&mut self) -> TA_W

Bits 24:27 - Turnaround time

pub fn ceitv(&mut self) -> CEITV_W

Bits 28:31 - CE# interval time

impl W<u32, Reg<u32, _NANDCR2>>

pub fn twhr(&mut self) -> TWHR_W

Bits 0:5 - WE# HIGH to RE# LOW wait time

pub fn trhw(&mut self) -> TRHW_W

Bits 6:11 - RE# HIGH to WE# LOW wait time

pub fn tadl(&mut self) -> TADL_W

Bits 12:17 - ALE to WRITE Data start wait time

pub fn trr(&mut self) -> TRR_W

Bits 18:23 - Ready to RE# LOW min wait time

pub fn twb(&mut self) -> TWB_W

Bits 24:29 - WE# HIGH to busy wait time

impl W<u32, Reg<u32, _NANDCR3>>

pub fn ndopt1(&mut self) -> NDOPT1_W

Bit 0 - NAND option bit 1

pub fn ndopt2(&mut self) -> NDOPT2_W

Bit 1 - NAND option bit 2

pub fn ndopt3(&mut self) -> NDOPT3_W

Bit 2 - NAND option bit 3

pub fn cle(&mut self) -> CLE_W

Bit 3 - NAND CLE Option

pub fn rds(&mut self) -> RDS_W

Bits 16:19 - Read Data Setup cycle time.

pub fn rdh(&mut self) -> RDH_W

Bits 20:23 - Read Data Hold cycle time.

pub fn wds(&mut self) -> WDS_W

Bits 24:27 - Write Data Setup cycle time.

pub fn wdh(&mut self) -> WDH_W

Bits 28:31 - Write Data Hold cycle time.

impl W<u32, Reg<u32, _NORCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Port Size

pub fn syncen(&mut self) -> SYNCEN_W

Bit 1 - Select NOR controller mode.

pub fn bl(&mut self) -> BL_W

Bits 4:6 - Burst Length

pub fn am(&mut self) -> AM_W

Bits 8:9 - Address Mode

pub fn advp(&mut self) -> ADVP_W

Bit 10 - ADV# polarity

pub fn advh(&mut self) -> ADVH_W

Bit 11 - ADV# level control during address hold state

pub fn col(&mut self) -> COL_W

Bits 12:15 - Column Address bit width

impl W<u32, Reg<u32, _NORCR1>>

pub fn ces(&mut self) -> CES_W

Bits 0:3 - CE setup time cycle

pub fn ceh(&mut self) -> CEH_W

Bits 4:7 - CE hold min time (CEH+1) cycle

pub fn as_(&mut self) -> AS_W

Bits 8:11 - Address setup time

pub fn ah(&mut self) -> AH_W

Bits 12:15 - Address hold time

pub fn wel(&mut self) -> WEL_W

Bits 16:19 - WE LOW time (WEL+1) cycle

pub fn weh(&mut self) -> WEH_W

Bits 20:23 - WE HIGH time (WEH+1) cycle

pub fn rel(&mut self) -> REL_W

Bits 24:27 - RE LOW time (REL+1) cycle

pub fn reh(&mut self) -> REH_W

Bits 28:31 - RE HIGH time (REH+1) cycle

impl W<u32, Reg<u32, _NORCR2>>

pub fn ta(&mut self) -> TA_W

Bits 8:11 - Turnaround time cycle

pub fn awdh(&mut self) -> AWDH_W

Bits 12:15 - Address to write data hold time cycle

pub fn lc(&mut self) -> LC_W

Bits 16:19 - Latency count

pub fn rd(&mut self) -> RD_W

Bits 20:23 - Read cycle time

pub fn ceitv(&mut self) -> CEITV_W

Bits 24:27 - CE# interval min time

pub fn rdh(&mut self) -> RDH_W

Bits 28:31 - Read cycle hold time

impl W<u32, Reg<u32, _NORCR3>>

pub fn assr(&mut self) -> ASSR_W

Bits 0:3 - Address setup time for synchronous read

pub fn ahsr(&mut self) -> AHSR_W

Bits 4:7 - Address hold time for synchronous read

impl W<u32, Reg<u32, _SRAMCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Port Size

pub fn syncen(&mut self) -> SYNCEN_W

Bit 1 - Select SRAM controller mode.

pub fn bl(&mut self) -> BL_W

Bits 4:6 - Burst Length

pub fn am(&mut self) -> AM_W

Bits 8:9 - Address Mode

pub fn advp(&mut self) -> ADVP_W

Bit 10 - ADV# polarity

pub fn advh(&mut self) -> ADVH_W

Bit 11 - ADV# level control during address hold state

pub fn col(&mut self) -> COL_W

Bits 12:15 - Column Address bit width

impl W<u32, Reg<u32, _SRAMCR1>>

pub fn ces(&mut self) -> CES_W

Bits 0:3 - CE setup time cycle

pub fn ceh(&mut self) -> CEH_W

Bits 4:7 - CE hold min time

pub fn as_(&mut self) -> AS_W

Bits 8:11 - Address setup time

pub fn ah(&mut self) -> AH_W

Bits 12:15 - Address hold time

pub fn wel(&mut self) -> WEL_W

Bits 16:19 - WE LOW time (WEL+1) cycle

pub fn weh(&mut self) -> WEH_W

Bits 20:23 - WE HIGH time (WEH+1) cycle

pub fn rel(&mut self) -> REL_W

Bits 24:27 - RE LOW time (REL+1) cycle

pub fn reh(&mut self) -> REH_W

Bits 28:31 - RE HIGH time (REH+1) cycle

impl W<u32, Reg<u32, _SRAMCR2>>

pub fn wds(&mut self) -> WDS_W

Bits 0:3 - Write Data setup time (WDS+1) cycle

pub fn wdh(&mut self) -> WDH_W

Bits 4:7 - Write Data hold time WDH cycle

pub fn ta(&mut self) -> TA_W

Bits 8:11 - Turnaround time cycle

pub fn awdh(&mut self) -> AWDH_W

Bits 12:15 - Address to write data hold time cycle

pub fn lc(&mut self) -> LC_W

Bits 16:19 - Latency count

pub fn rd(&mut self) -> RD_W

Bits 20:23 - Read cycle time

pub fn ceitv(&mut self) -> CEITV_W

Bits 24:27 - CE# interval min time

pub fn rdh(&mut self) -> RDH_W

Bits 28:31 - Read cycle hold time

impl W<u32, Reg<u32, _DBICR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Port Size

pub fn bl(&mut self) -> BL_W

Bits 4:6 - Burst Length

pub fn col(&mut self) -> COL_W

Bits 12:15 - Column Address bit width

impl W<u32, Reg<u32, _DBICR1>>

pub fn ces(&mut self) -> CES_W

Bits 0:3 - CSX Setup Time

pub fn ceh(&mut self) -> CEH_W

Bits 4:7 - CSX Hold Time

pub fn wel(&mut self) -> WEL_W

Bits 8:11 - WRX Low Time

pub fn weh(&mut self) -> WEH_W

Bits 12:15 - WRX High Time

pub fn rel(&mut self) -> REL_W

Bits 16:21 - RDX Low Time

pub fn reh(&mut self) -> REH_W

Bits 22:27 - RDX High Time

pub fn ceitv(&mut self) -> CEITV_W

Bits 28:31 - CSX interval min time

impl W<u32, Reg<u32, _IPCR0>>

pub fn sa(&mut self) -> SA_W

Bits 0:31 - Slave address

impl W<u32, Reg<u32, _IPCR1>>

pub fn datsz(&mut self) -> DATSZ_W

Bits 0:2 - Data Size in Byte

pub fn nand_ext_addr(&mut self) -> NAND_EXT_ADDR_W

Bits 8:15 - NAND Extended Address

impl W<u32, Reg<u32, _IPCR2>>

pub fn bm0(&mut self) -> BM0_W

Bit 0 - Byte Mask for Byte 0 (IPTXD bit 7:0)

pub fn bm1(&mut self) -> BM1_W

Bit 1 - Byte Mask for Byte 1 (IPTXD bit 15:8)

pub fn bm2(&mut self) -> BM2_W

Bit 2 - Byte Mask for Byte 2 (IPTXD bit 23:16)

pub fn bm3(&mut self) -> BM3_W

Bit 3 - Byte Mask for Byte 3 (IPTXD bit 31:24)

impl W<u32, Reg<u32, _IPCMD>>

pub fn cmd(&mut self) -> CMD_W

Bits 0:15 - SDRAM Commands: 0x8: READ 0x9: WRITE 0xA: MODESET 0xB: ACTIVE 0xC: AUTO REFRESH 0xD: SELF REFRESH 0xE: PRECHARGE 0xF: PRECHARGE ALL Others: RSVD SELF REFRESH will be sent to all SDRAM devices because they shared same SEMC_CLK pin

pub fn key(&mut self) -> KEY_W

Bits 16:31 - This field should be written with 0xA55A when trigging an IP command for all device types

impl W<u32, Reg<u32, _IPTXDAT>>

pub fn dat(&mut self) -> DAT_W

Bits 0:31 - no description available