Struct imxrt1062_sai1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _TCSR>>

pub fn frde(&mut self) -> FRDE_W

Bit 0 - FIFO Request DMA Enable

pub fn fwde(&mut self) -> FWDE_W

Bit 1 - FIFO Warning DMA Enable

pub fn frie(&mut self) -> FRIE_W

Bit 8 - FIFO Request Interrupt Enable

pub fn fwie(&mut self) -> FWIE_W

Bit 9 - FIFO Warning Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 10 - FIFO Error Interrupt Enable

pub fn seie(&mut self) -> SEIE_W

Bit 11 - Sync Error Interrupt Enable

pub fn wsie(&mut self) -> WSIE_W

Bit 12 - Word Start Interrupt Enable

pub fn fef(&mut self) -> FEF_W

Bit 18 - FIFO Error Flag

pub fn sef(&mut self) -> SEF_W

Bit 19 - Sync Error Flag

pub fn wsf(&mut self) -> WSF_W

Bit 20 - Word Start Flag

pub fn sr(&mut self) -> SR_W

Bit 24 - Software Reset

pub fn fr(&mut self) -> FR_W

Bit 25 - FIFO Reset

pub fn bce(&mut self) -> BCE_W

Bit 28 - Bit Clock Enable

pub fn dbge(&mut self) -> DBGE_W

Bit 29 - Debug Enable

pub fn stope(&mut self) -> STOPE_W

Bit 30 - Stop Enable

pub fn te(&mut self) -> TE_W

Bit 31 - Transmitter Enable

impl W<u32, Reg<u32, _TCR1>>

pub fn tfw(&mut self) -> TFW_W

Bits 0:4 - Transmit FIFO Watermark

impl W<u32, Reg<u32, _TCR2>>

pub fn div(&mut self) -> DIV_W

Bits 0:7 - Bit Clock Divide

pub fn bcd(&mut self) -> BCD_W

Bit 24 - Bit Clock Direction

pub fn bcp(&mut self) -> BCP_W

Bit 25 - Bit Clock Polarity

pub fn msel(&mut self) -> MSEL_W

Bits 26:27 - MCLK Select

pub fn bci(&mut self) -> BCI_W

Bit 28 - Bit Clock Input

pub fn bcs(&mut self) -> BCS_W

Bit 29 - Bit Clock Swap

pub fn sync(&mut self) -> SYNC_W

Bits 30:31 - Synchronous Mode

impl W<u32, Reg<u32, _TCR3>>

pub fn wdfl(&mut self) -> WDFL_W

Bits 0:4 - Word Flag Configuration

pub fn tce(&mut self) -> TCE_W

Bits 16:19 - Transmit Channel Enable

pub fn cfr(&mut self) -> CFR_W

Bits 24:27 - Channel FIFO Reset

impl W<u32, Reg<u32, _TCR4>>

pub fn fsd(&mut self) -> FSD_W

Bit 0 - Frame Sync Direction

pub fn fsp(&mut self) -> FSP_W

Bit 1 - Frame Sync Polarity

pub fn ondem(&mut self) -> ONDEM_W

Bit 2 - On Demand Mode

pub fn fse(&mut self) -> FSE_W

Bit 3 - Frame Sync Early

pub fn mf(&mut self) -> MF_W

Bit 4 - MSB First

pub fn chmod(&mut self) -> CHMOD_W

Bit 5 - Channel Mode

pub fn sywd(&mut self) -> SYWD_W

Bits 8:12 - Sync Width

pub fn frsz(&mut self) -> FRSZ_W

Bits 16:20 - Frame size

pub fn fpack(&mut self) -> FPACK_W

Bits 24:25 - FIFO Packing Mode

pub fn fcomb(&mut self) -> FCOMB_W

Bits 26:27 - FIFO Combine Mode

pub fn fcont(&mut self) -> FCONT_W

Bit 28 - FIFO Continue on Error

impl W<u32, Reg<u32, _TCR5>>

pub fn fbt(&mut self) -> FBT_W

Bits 8:12 - First Bit Shifted

pub fn w0w(&mut self) -> W0W_W

Bits 16:20 - Word 0 Width

pub fn wnw(&mut self) -> WNW_W

Bits 24:28 - Word N Width

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W

Bits 0:31 - Transmit Data Register

impl W<u32, Reg<u32, _TMR>>

pub fn twm(&mut self) -> TWM_W

Bits 0:31 - Transmit Word Mask

impl W<u32, Reg<u32, _RCSR>>

pub fn frde(&mut self) -> FRDE_W

Bit 0 - FIFO Request DMA Enable

pub fn fwde(&mut self) -> FWDE_W

Bit 1 - FIFO Warning DMA Enable

pub fn frie(&mut self) -> FRIE_W

Bit 8 - FIFO Request Interrupt Enable

pub fn fwie(&mut self) -> FWIE_W

Bit 9 - FIFO Warning Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 10 - FIFO Error Interrupt Enable

pub fn seie(&mut self) -> SEIE_W

Bit 11 - Sync Error Interrupt Enable

pub fn wsie(&mut self) -> WSIE_W

Bit 12 - Word Start Interrupt Enable

pub fn fef(&mut self) -> FEF_W

Bit 18 - FIFO Error Flag

pub fn sef(&mut self) -> SEF_W

Bit 19 - Sync Error Flag

pub fn wsf(&mut self) -> WSF_W

Bit 20 - Word Start Flag

pub fn sr(&mut self) -> SR_W

Bit 24 - Software Reset

pub fn fr(&mut self) -> FR_W

Bit 25 - FIFO Reset

pub fn bce(&mut self) -> BCE_W

Bit 28 - Bit Clock Enable

pub fn dbge(&mut self) -> DBGE_W

Bit 29 - Debug Enable

pub fn stope(&mut self) -> STOPE_W

Bit 30 - Stop Enable

pub fn re(&mut self) -> RE_W

Bit 31 - Receiver Enable

impl W<u32, Reg<u32, _RCR1>>

pub fn rfw(&mut self) -> RFW_W

Bits 0:4 - Receive FIFO Watermark

impl W<u32, Reg<u32, _RCR2>>

pub fn div(&mut self) -> DIV_W

Bits 0:7 - Bit Clock Divide

pub fn bcd(&mut self) -> BCD_W

Bit 24 - Bit Clock Direction

pub fn bcp(&mut self) -> BCP_W

Bit 25 - Bit Clock Polarity

pub fn msel(&mut self) -> MSEL_W

Bits 26:27 - MCLK Select

pub fn bci(&mut self) -> BCI_W

Bit 28 - Bit Clock Input

pub fn bcs(&mut self) -> BCS_W

Bit 29 - Bit Clock Swap

pub fn sync(&mut self) -> SYNC_W

Bits 30:31 - Synchronous Mode

impl W<u32, Reg<u32, _RCR3>>

pub fn wdfl(&mut self) -> WDFL_W

Bits 0:4 - Word Flag Configuration

pub fn rce(&mut self) -> RCE_W

Bits 16:19 - Receive Channel Enable

pub fn cfr(&mut self) -> CFR_W

Bits 24:27 - Channel FIFO Reset

impl W<u32, Reg<u32, _RCR4>>

pub fn fsd(&mut self) -> FSD_W

Bit 0 - Frame Sync Direction

pub fn fsp(&mut self) -> FSP_W

Bit 1 - Frame Sync Polarity

pub fn ondem(&mut self) -> ONDEM_W

Bit 2 - On Demand Mode

pub fn fse(&mut self) -> FSE_W

Bit 3 - Frame Sync Early

pub fn mf(&mut self) -> MF_W

Bit 4 - MSB First

pub fn sywd(&mut self) -> SYWD_W

Bits 8:12 - Sync Width

pub fn frsz(&mut self) -> FRSZ_W

Bits 16:20 - Frame Size

pub fn fpack(&mut self) -> FPACK_W

Bits 24:25 - FIFO Packing Mode

pub fn fcomb(&mut self) -> FCOMB_W

Bits 26:27 - FIFO Combine Mode

pub fn fcont(&mut self) -> FCONT_W

Bit 28 - FIFO Continue on Error

impl W<u32, Reg<u32, _RCR5>>

pub fn fbt(&mut self) -> FBT_W

Bits 8:12 - First Bit Shifted

pub fn w0w(&mut self) -> W0W_W

Bits 16:20 - Word 0 Width

pub fn wnw(&mut self) -> WNW_W

Bits 24:28 - Word N Width

impl W<u32, Reg<u32, _RMR>>

pub fn rwm(&mut self) -> RWM_W

Bits 0:31 - Receive Word Mask