Struct imxrt1062_pmu::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _REG_1P1>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 1p1 regulator

pub fn selref_weak_linreg(&mut self) -> SELREF_WEAK_LINREG_W

Bit 19 - Selects the source for the reference voltage of the weak 1p1 regulator.

impl W<u32, Reg<u32, _REG_1P1_SET>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 1p1 regulator

pub fn selref_weak_linreg(&mut self) -> SELREF_WEAK_LINREG_W

Bit 19 - Selects the source for the reference voltage of the weak 1p1 regulator.

impl W<u32, Reg<u32, _REG_1P1_CLR>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 1p1 regulator

pub fn selref_weak_linreg(&mut self) -> SELREF_WEAK_LINREG_W

Bit 19 - Selects the source for the reference voltage of the weak 1p1 regulator.

impl W<u32, Reg<u32, _REG_1P1_TOG>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 1p1 regulator

pub fn selref_weak_linreg(&mut self) -> SELREF_WEAK_LINREG_W

Bit 19 - Selects the source for the reference voltage of the weak 1p1 regulator.

impl W<u32, Reg<u32, _REG_3P0>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn vbus_sel(&mut self) -> VBUS_SEL_W

Bit 7 - Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

impl W<u32, Reg<u32, _REG_3P0_SET>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn vbus_sel(&mut self) -> VBUS_SEL_W

Bit 7 - Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

impl W<u32, Reg<u32, _REG_3P0_CLR>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn vbus_sel(&mut self) -> VBUS_SEL_W

Bit 7 - Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

impl W<u32, Reg<u32, _REG_3P0_TOG>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn vbus_sel(&mut self) -> VBUS_SEL_W

Bit 7 - Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

impl W<u32, Reg<u32, _REG_2P5>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 2p5 regulator

impl W<u32, Reg<u32, _REG_2P5_SET>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 2p5 regulator

impl W<u32, Reg<u32, _REG_2P5_CLR>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 2p5 regulator

impl W<u32, Reg<u32, _REG_2P5_TOG>>

pub fn enable_linreg(&mut self) -> ENABLE_LINREG_W

Bit 0 - Control bit to enable the regulator output.

pub fn enable_bo(&mut self) -> ENABLE_BO_W

Bit 1 - Control bit to enable the brownout circuitry in the regulator.

pub fn enable_ilimit(&mut self) -> ENABLE_ILIMIT_W

Bit 2 - Control bit to enable the current-limit circuitry in the regulator.

pub fn enable_pulldown(&mut self) -> ENABLE_PULLDOWN_W

Bit 3 - Control bit to enable the pull-down circuitry in the regulator

pub fn bo_offset(&mut self) -> BO_OFFSET_W

Bits 4:6 - Control bits to adjust the regulator brownout offset voltage in 25mV steps

pub fn output_trg(&mut self) -> OUTPUT_TRG_W

Bits 8:12 - Control bits to adjust the regulator output voltage

pub fn enable_weak_linreg(&mut self) -> ENABLE_WEAK_LINREG_W

Bit 18 - Enables the weak 2p5 regulator

impl W<u32, Reg<u32, _REG_CORE>>

pub fn reg0_targ(&mut self) -> REG0_TARG_W

Bits 0:4 - This field defines the target voltage for the ARM core power domain

pub fn reg0_adj(&mut self) -> REG0_ADJ_W

Bits 5:8 - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg1_targ(&mut self) -> REG1_TARG_W

Bits 9:13 - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub fn reg1_adj(&mut self) -> REG1_ADJ_W

Bits 14:17 - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg2_targ(&mut self) -> REG2_TARG_W

Bits 18:22 - This field defines the target voltage for the SOC power domain

pub fn reg2_adj(&mut self) -> REG2_ADJ_W

Bits 23:26 - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn ramp_rate(&mut self) -> RAMP_RATE_W

Bits 27:28 - Regulator voltage ramp rate.

pub fn fet_odrive(&mut self) -> FET_ODRIVE_W

Bit 29 - If set, increases the gate drive on power gating FETs to reduce leakage in the off state

impl W<u32, Reg<u32, _REG_CORE_SET>>

pub fn reg0_targ(&mut self) -> REG0_TARG_W

Bits 0:4 - This field defines the target voltage for the ARM core power domain

pub fn reg0_adj(&mut self) -> REG0_ADJ_W

Bits 5:8 - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg1_targ(&mut self) -> REG1_TARG_W

Bits 9:13 - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub fn reg1_adj(&mut self) -> REG1_ADJ_W

Bits 14:17 - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg2_targ(&mut self) -> REG2_TARG_W

Bits 18:22 - This field defines the target voltage for the SOC power domain

pub fn reg2_adj(&mut self) -> REG2_ADJ_W

Bits 23:26 - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn ramp_rate(&mut self) -> RAMP_RATE_W

Bits 27:28 - Regulator voltage ramp rate.

pub fn fet_odrive(&mut self) -> FET_ODRIVE_W

Bit 29 - If set, increases the gate drive on power gating FETs to reduce leakage in the off state

impl W<u32, Reg<u32, _REG_CORE_CLR>>

pub fn reg0_targ(&mut self) -> REG0_TARG_W

Bits 0:4 - This field defines the target voltage for the ARM core power domain

pub fn reg0_adj(&mut self) -> REG0_ADJ_W

Bits 5:8 - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg1_targ(&mut self) -> REG1_TARG_W

Bits 9:13 - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub fn reg1_adj(&mut self) -> REG1_ADJ_W

Bits 14:17 - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg2_targ(&mut self) -> REG2_TARG_W

Bits 18:22 - This field defines the target voltage for the SOC power domain

pub fn reg2_adj(&mut self) -> REG2_ADJ_W

Bits 23:26 - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn ramp_rate(&mut self) -> RAMP_RATE_W

Bits 27:28 - Regulator voltage ramp rate.

pub fn fet_odrive(&mut self) -> FET_ODRIVE_W

Bit 29 - If set, increases the gate drive on power gating FETs to reduce leakage in the off state

impl W<u32, Reg<u32, _REG_CORE_TOG>>

pub fn reg0_targ(&mut self) -> REG0_TARG_W

Bits 0:4 - This field defines the target voltage for the ARM core power domain

pub fn reg0_adj(&mut self) -> REG0_ADJ_W

Bits 5:8 - This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg1_targ(&mut self) -> REG1_TARG_W

Bits 9:13 - This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub fn reg1_adj(&mut self) -> REG1_ADJ_W

Bits 14:17 - This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn reg2_targ(&mut self) -> REG2_TARG_W

Bits 18:22 - This field defines the target voltage for the SOC power domain

pub fn reg2_adj(&mut self) -> REG2_ADJ_W

Bits 23:26 - This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub fn ramp_rate(&mut self) -> RAMP_RATE_W

Bits 27:28 - Regulator voltage ramp rate.

pub fn fet_odrive(&mut self) -> FET_ODRIVE_W

Bit 29 - If set, increases the gate drive on power gating FETs to reduce leakage in the off state

impl W<u32, Reg<u32, _MISC0>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - no description available

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's.

impl W<u32, Reg<u32, _MISC0_SET>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - no description available

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's.

impl W<u32, Reg<u32, _MISC0_CLR>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - no description available

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's.

impl W<u32, Reg<u32, _MISC0_TOG>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - no description available

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable.

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's.

impl W<u32, Reg<u32, _MISC1>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.Not related to PMU.

pub fn lvds2_clk_sel(&mut self) -> LVDS2_CLK_SEL_W

Bits 5:9 - This field selects the clk to be routed to anaclk2/2b.Not related to PMU.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk2_oben(&mut self) -> LVDSCLK2_OBEN_W

Bit 11 - This enables the LVDS output buffer for anaclk2/2b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn lvdsclk2_iben(&mut self) -> LVDSCLK2_IBEN_W

Bit 13 - This enables the LVDS input buffer for anaclk2/2b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC1_SET>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.Not related to PMU.

pub fn lvds2_clk_sel(&mut self) -> LVDS2_CLK_SEL_W

Bits 5:9 - This field selects the clk to be routed to anaclk2/2b.Not related to PMU.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk2_oben(&mut self) -> LVDSCLK2_OBEN_W

Bit 11 - This enables the LVDS output buffer for anaclk2/2b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn lvdsclk2_iben(&mut self) -> LVDSCLK2_IBEN_W

Bit 13 - This enables the LVDS input buffer for anaclk2/2b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC1_CLR>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.Not related to PMU.

pub fn lvds2_clk_sel(&mut self) -> LVDS2_CLK_SEL_W

Bits 5:9 - This field selects the clk to be routed to anaclk2/2b.Not related to PMU.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk2_oben(&mut self) -> LVDSCLK2_OBEN_W

Bit 11 - This enables the LVDS output buffer for anaclk2/2b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn lvdsclk2_iben(&mut self) -> LVDSCLK2_IBEN_W

Bit 13 - This enables the LVDS input buffer for anaclk2/2b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC1_TOG>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.Not related to PMU.

pub fn lvds2_clk_sel(&mut self) -> LVDS2_CLK_SEL_W

Bits 5:9 - This field selects the clk to be routed to anaclk2/2b.Not related to PMU.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk2_oben(&mut self) -> LVDSCLK2_OBEN_W

Bit 11 - This enables the LVDS output buffer for anaclk2/2b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn lvdsclk2_iben(&mut self) -> LVDSCLK2_IBEN_W

Bit 13 - This enables the LVDS input buffer for anaclk2/2b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC2>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - Default value of "0"

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video

impl W<u32, Reg<u32, _MISC2_SET>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - Default value of "0"

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video

impl W<u32, Reg<u32, _MISC2_CLR>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - Default value of "0"

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video

impl W<u32, Reg<u32, _MISC2_TOG>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - Default value of "0"

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video