[−][src]Struct imxrt1062_lpi2c1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

Writes raw bits to the register

impl W<u32, Reg<u32, _MCR>>[src]

pub fn men(&mut self) -> MEN_W[src]

Bit 0 - Master Enable

pub fn rst(&mut self) -> RST_W[src]

Bit 1 - Software Reset

pub fn dozen(&mut self) -> DOZEN_W[src]

Bit 2 - Doze mode enable

pub fn dbgen(&mut self) -> DBGEN_W[src]

Bit 3 - Debug Enable

pub fn rtf(&mut self) -> RTF_W[src]

Bit 8 - Reset Transmit FIFO

pub fn rrf(&mut self) -> RRF_W[src]

Bit 9 - Reset Receive FIFO

impl W<u32, Reg<u32, _MSR>>[src]

pub fn epf(&mut self) -> EPF_W[src]

Bit 8 - End Packet Flag

pub fn sdf(&mut self) -> SDF_W[src]

Bit 9 - STOP Detect Flag

pub fn ndf(&mut self) -> NDF_W[src]

Bit 10 - NACK Detect Flag

pub fn alf(&mut self) -> ALF_W[src]

Bit 11 - Arbitration Lost Flag

pub fn fef(&mut self) -> FEF_W[src]

Bit 12 - FIFO Error Flag

pub fn pltf(&mut self) -> PLTF_W[src]

Bit 13 - Pin Low Timeout Flag

pub fn dmf(&mut self) -> DMF_W[src]

Bit 14 - Data Match Flag

impl W<u32, Reg<u32, _MIER>>[src]

pub fn tdie(&mut self) -> TDIE_W[src]

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W[src]

Bit 1 - Receive Data Interrupt Enable

pub fn epie(&mut self) -> EPIE_W[src]

Bit 8 - End Packet Interrupt Enable

pub fn sdie(&mut self) -> SDIE_W[src]

Bit 9 - STOP Detect Interrupt Enable

pub fn ndie(&mut self) -> NDIE_W[src]

Bit 10 - NACK Detect Interrupt Enable

pub fn alie(&mut self) -> ALIE_W[src]

Bit 11 - Arbitration Lost Interrupt Enable

pub fn feie(&mut self) -> FEIE_W[src]

Bit 12 - FIFO Error Interrupt Enable

pub fn pltie(&mut self) -> PLTIE_W[src]

Bit 13 - Pin Low Timeout Interrupt Enable

pub fn dmie(&mut self) -> DMIE_W[src]

Bit 14 - Data Match Interrupt Enable

impl W<u32, Reg<u32, _MDER>>[src]

pub fn tdde(&mut self) -> TDDE_W[src]

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W[src]

Bit 1 - Receive Data DMA Enable

impl W<u32, Reg<u32, _MCFGR0>>[src]

pub fn hren(&mut self) -> HREN_W[src]

Bit 0 - Host Request Enable

pub fn hrpol(&mut self) -> HRPOL_W[src]

Bit 1 - Host Request Polarity

pub fn hrsel(&mut self) -> HRSEL_W[src]

Bit 2 - Host Request Select

pub fn cirfifo(&mut self) -> CIRFIFO_W[src]

Bit 8 - Circular FIFO Enable

pub fn rdmo(&mut self) -> RDMO_W[src]

Bit 9 - Receive Data Match Only

impl W<u32, Reg<u32, _MCFGR1>>[src]

pub fn prescale(&mut self) -> PRESCALE_W[src]

Bits 0:2 - Prescaler

pub fn autostop(&mut self) -> AUTOSTOP_W[src]

Bit 8 - Automatic STOP Generation

pub fn ignack(&mut self) -> IGNACK_W[src]

Bit 9 - IGNACK

pub fn timecfg(&mut self) -> TIMECFG_W[src]

Bit 10 - Timeout Configuration

pub fn matcfg(&mut self) -> MATCFG_W[src]

Bits 16:18 - Match Configuration

pub fn pincfg(&mut self) -> PINCFG_W[src]

Bits 24:26 - Pin Configuration

impl W<u32, Reg<u32, _MCFGR2>>[src]

pub fn busidle(&mut self) -> BUSIDLE_W[src]

Bits 0:11 - Bus Idle Timeout

pub fn filtscl(&mut self) -> FILTSCL_W[src]

Bits 16:19 - Glitch Filter SCL

pub fn filtsda(&mut self) -> FILTSDA_W[src]

Bits 24:27 - Glitch Filter SDA

impl W<u32, Reg<u32, _MCFGR3>>[src]

pub fn pinlow(&mut self) -> PINLOW_W[src]

Bits 8:19 - Pin Low Timeout

impl W<u32, Reg<u32, _MDMR>>[src]

pub fn match0(&mut self) -> MATCH0_W[src]

Bits 0:7 - Match 0 Value

pub fn match1(&mut self) -> MATCH1_W[src]

Bits 16:23 - Match 1 Value

impl W<u32, Reg<u32, _MCCR0>>[src]

pub fn clklo(&mut self) -> CLKLO_W[src]

Bits 0:5 - Clock Low Period

pub fn clkhi(&mut self) -> CLKHI_W[src]

Bits 8:13 - Clock High Period

pub fn sethold(&mut self) -> SETHOLD_W[src]

Bits 16:21 - Setup Hold Delay

pub fn datavd(&mut self) -> DATAVD_W[src]

Bits 24:29 - Data Valid Delay

impl W<u32, Reg<u32, _MCCR1>>[src]

pub fn clklo(&mut self) -> CLKLO_W[src]

Bits 0:5 - Clock Low Period

pub fn clkhi(&mut self) -> CLKHI_W[src]

Bits 8:13 - Clock High Period

pub fn sethold(&mut self) -> SETHOLD_W[src]

Bits 16:21 - Setup Hold Delay

pub fn datavd(&mut self) -> DATAVD_W[src]

Bits 24:29 - Data Valid Delay

impl W<u32, Reg<u32, _MFCR>>[src]

pub fn txwater(&mut self) -> TXWATER_W[src]

Bits 0:1 - Transmit FIFO Watermark

pub fn rxwater(&mut self) -> RXWATER_W[src]

Bits 16:17 - Receive FIFO Watermark

impl W<u32, Reg<u32, _MTDR>>[src]

pub fn data(&mut self) -> DATA_W[src]

Bits 0:7 - Transmit Data

pub fn cmd(&mut self) -> CMD_W[src]

Bits 8:10 - Command Data

impl W<u32, Reg<u32, _SCR>>[src]

pub fn sen(&mut self) -> SEN_W[src]

Bit 0 - Slave Enable

pub fn rst(&mut self) -> RST_W[src]

Bit 1 - Software Reset

pub fn filten(&mut self) -> FILTEN_W[src]

Bit 4 - Filter Enable

pub fn filtdz(&mut self) -> FILTDZ_W[src]

Bit 5 - Filter Doze Enable

pub fn rtf(&mut self) -> RTF_W[src]

Bit 8 - Reset Transmit FIFO

pub fn rrf(&mut self) -> RRF_W[src]

Bit 9 - Reset Receive FIFO

impl W<u32, Reg<u32, _SSR>>[src]

pub fn rsf(&mut self) -> RSF_W[src]

Bit 8 - Repeated Start Flag

pub fn sdf(&mut self) -> SDF_W[src]

Bit 9 - STOP Detect Flag

pub fn bef(&mut self) -> BEF_W[src]

Bit 10 - Bit Error Flag

pub fn fef(&mut self) -> FEF_W[src]

Bit 11 - FIFO Error Flag

impl W<u32, Reg<u32, _SIER>>[src]

pub fn tdie(&mut self) -> TDIE_W[src]

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W[src]

Bit 1 - Receive Data Interrupt Enable

pub fn avie(&mut self) -> AVIE_W[src]

Bit 2 - Address Valid Interrupt Enable

pub fn taie(&mut self) -> TAIE_W[src]

Bit 3 - Transmit ACK Interrupt Enable

pub fn rsie(&mut self) -> RSIE_W[src]

Bit 8 - Repeated Start Interrupt Enable

pub fn sdie(&mut self) -> SDIE_W[src]

Bit 9 - STOP Detect Interrupt Enable

pub fn beie(&mut self) -> BEIE_W[src]

Bit 10 - Bit Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W[src]

Bit 11 - FIFO Error Interrupt Enable

pub fn am0ie(&mut self) -> AM0IE_W[src]

Bit 12 - Address Match 0 Interrupt Enable

pub fn am1f(&mut self) -> AM1F_W[src]

Bit 13 - Address Match 1 Interrupt Enable

pub fn gcie(&mut self) -> GCIE_W[src]

Bit 14 - General Call Interrupt Enable

pub fn sarie(&mut self) -> SARIE_W[src]

Bit 15 - SMBus Alert Response Interrupt Enable

impl W<u32, Reg<u32, _SDER>>[src]

pub fn tdde(&mut self) -> TDDE_W[src]

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W[src]

Bit 1 - Receive Data DMA Enable

pub fn avde(&mut self) -> AVDE_W[src]

Bit 2 - Address Valid DMA Enable

impl W<u32, Reg<u32, _SCFGR1>>[src]

pub fn adrstall(&mut self) -> ADRSTALL_W[src]

Bit 0 - Address SCL Stall

pub fn rxstall(&mut self) -> RXSTALL_W[src]

Bit 1 - RX SCL Stall

pub fn txdstall(&mut self) -> TXDSTALL_W[src]

Bit 2 - TX Data SCL Stall

pub fn ackstall(&mut self) -> ACKSTALL_W[src]

Bit 3 - ACK SCL Stall

pub fn gcen(&mut self) -> GCEN_W[src]

Bit 8 - General Call Enable

pub fn saen(&mut self) -> SAEN_W[src]

Bit 9 - SMBus Alert Enable

pub fn txcfg(&mut self) -> TXCFG_W[src]

Bit 10 - Transmit Flag Configuration

pub fn rxcfg(&mut self) -> RXCFG_W[src]

Bit 11 - Receive Data Configuration

pub fn ignack(&mut self) -> IGNACK_W[src]

Bit 12 - Ignore NACK

pub fn hsmen(&mut self) -> HSMEN_W[src]

Bit 13 - High Speed Mode Enable

pub fn addrcfg(&mut self) -> ADDRCFG_W[src]

Bits 16:18 - Address Configuration

impl W<u32, Reg<u32, _SCFGR2>>[src]

pub fn clkhold(&mut self) -> CLKHOLD_W[src]

Bits 0:3 - Clock Hold Time

pub fn datavd(&mut self) -> DATAVD_W[src]

Bits 8:13 - Data Valid Delay

pub fn filtscl(&mut self) -> FILTSCL_W[src]

Bits 16:19 - Glitch Filter SCL

pub fn filtsda(&mut self) -> FILTSDA_W[src]

Bits 24:27 - Glitch Filter SDA

impl W<u32, Reg<u32, _SAMR>>[src]

pub fn addr0(&mut self) -> ADDR0_W[src]

Bits 1:10 - Address 0 Value

pub fn addr1(&mut self) -> ADDR1_W[src]

Bits 17:26 - Address 1 Value

impl W<u32, Reg<u32, _STAR>>[src]

pub fn txnack(&mut self) -> TXNACK_W[src]

Bit 0 - Transmit NACK

impl W<u32, Reg<u32, _STDR>>[src]

pub fn data(&mut self) -> DATA_W[src]

Bits 0:7 - Transmit Data

Auto Trait Implementations

impl<U, REG> Send for W<U, REG> where
    REG: Send,
    U: Send, 

impl<U, REG> Sync for W<U, REG> where
    REG: Sync,
    U: Sync, 

impl<U, REG> Unpin for W<U, REG> where
    REG: Unpin,
    U: Unpin, 

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.