Type Definition imxrt1062_lcdif::vdctrl0_set::W

type W = W<u32, VDCTRL0_SET>;

Writer for register VDCTRL0_SET

Methods

impl W

pub fn vsync_pulse_width(&mut self) -> VSYNC_PULSE_WIDTH_W

Bits 0:17 - Number of units for which VSYNC signal is active

pub fn half_line_mode(&mut self) -> HALF_LINE_MODE_W

Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub fn half_line(&mut self) -> HALF_LINE_W

Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub fn vsync_pulse_width_unit(&mut self) -> VSYNC_PULSE_WIDTH_UNIT_W

Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn vsync_period_unit(&mut self) -> VSYNC_PERIOD_UNIT_W

Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub fn enable_pol(&mut self) -> ENABLE_POL_W

Bit 24 - Default 0 active low during valid data transfer on each horizontal line.

pub fn dotclk_pol(&mut self) -> DOTCLK_POL_W

Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge

pub fn hsync_pol(&mut self) -> HSYNC_POL_W

Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub fn vsync_pol(&mut self) -> VSYNC_POL_W

Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub fn enable_present(&mut self) -> ENABLE_PRESENT_W

Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK