1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346
#[doc = "Reader of register VDCTRL0"] pub type R = crate::R<u32, super::VDCTRL0>; #[doc = "Writer for register VDCTRL0"] pub type W = crate::W<u32, super::VDCTRL0>; #[doc = "Register VDCTRL0 `reset()`'s with value 0"] impl crate::ResetValue for super::VDCTRL0 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `VSYNC_PULSE_WIDTH`"] pub type VSYNC_PULSE_WIDTH_R = crate::R<u32, u32>; #[doc = "Write proxy for field `VSYNC_PULSE_WIDTH`"] pub struct VSYNC_PULSE_WIDTH_W<'a> { w: &'a mut W, } impl<'a> VSYNC_PULSE_WIDTH_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u32) -> &'a mut W { self.w.bits = (self.w.bits & !0x0003_ffff) | ((value as u32) & 0x0003_ffff); self.w } } #[doc = "Reader of field `HALF_LINE_MODE`"] pub type HALF_LINE_MODE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HALF_LINE_MODE`"] pub struct HALF_LINE_MODE_W<'a> { w: &'a mut W, } impl<'a> HALF_LINE_MODE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18); self.w } } #[doc = "Reader of field `HALF_LINE`"] pub type HALF_LINE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HALF_LINE`"] pub struct HALF_LINE_W<'a> { w: &'a mut W, } impl<'a> HALF_LINE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); self.w } } #[doc = "Reader of field `VSYNC_PULSE_WIDTH_UNIT`"] pub type VSYNC_PULSE_WIDTH_UNIT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `VSYNC_PULSE_WIDTH_UNIT`"] pub struct VSYNC_PULSE_WIDTH_UNIT_W<'a> { w: &'a mut W, } impl<'a> VSYNC_PULSE_WIDTH_UNIT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); self.w } } #[doc = "Reader of field `VSYNC_PERIOD_UNIT`"] pub type VSYNC_PERIOD_UNIT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `VSYNC_PERIOD_UNIT`"] pub struct VSYNC_PERIOD_UNIT_W<'a> { w: &'a mut W, } impl<'a> VSYNC_PERIOD_UNIT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); self.w } } #[doc = "Reader of field `ENABLE_POL`"] pub type ENABLE_POL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ENABLE_POL`"] pub struct ENABLE_POL_W<'a> { w: &'a mut W, } impl<'a> ENABLE_POL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } #[doc = "Reader of field `DOTCLK_POL`"] pub type DOTCLK_POL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DOTCLK_POL`"] pub struct DOTCLK_POL_W<'a> { w: &'a mut W, } impl<'a> DOTCLK_POL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); self.w } } #[doc = "Reader of field `HSYNC_POL`"] pub type HSYNC_POL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `HSYNC_POL`"] pub struct HSYNC_POL_W<'a> { w: &'a mut W, } impl<'a> HSYNC_POL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); self.w } } #[doc = "Reader of field `VSYNC_POL`"] pub type VSYNC_POL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `VSYNC_POL`"] pub struct VSYNC_POL_W<'a> { w: &'a mut W, } impl<'a> VSYNC_POL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27); self.w } } #[doc = "Reader of field `ENABLE_PRESENT`"] pub type ENABLE_PRESENT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ENABLE_PRESENT`"] pub struct ENABLE_PRESENT_W<'a> { w: &'a mut W, } impl<'a> ENABLE_PRESENT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } impl R { #[doc = "Bits 0:17 - Number of units for which VSYNC signal is active"] #[inline(always)] pub fn vsync_pulse_width(&self) -> VSYNC_PULSE_WIDTH_R { VSYNC_PULSE_WIDTH_R::new((self.bits & 0x0003_ffff) as u32) } #[doc = "Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line"] #[inline(always)] pub fn half_line_mode(&self) -> HALF_LINE_MODE_R { HALF_LINE_MODE_R::new(((self.bits >> 18) & 0x01) != 0) } #[doc = "Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i"] #[inline(always)] pub fn half_line(&self) -> HALF_LINE_R { HALF_LINE_R::new(((self.bits >> 19) & 0x01) != 0) } #[doc = "Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles"] #[inline(always)] pub fn vsync_pulse_width_unit(&self) -> VSYNC_PULSE_WIDTH_UNIT_R { VSYNC_PULSE_WIDTH_UNIT_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles"] #[inline(always)] pub fn vsync_period_unit(&self) -> VSYNC_PERIOD_UNIT_R { VSYNC_PERIOD_UNIT_R::new(((self.bits >> 21) & 0x01) != 0) } #[doc = "Bit 24 - Default 0 active low during valid data transfer on each horizontal line."] #[inline(always)] pub fn enable_pol(&self) -> ENABLE_POL_R { ENABLE_POL_R::new(((self.bits >> 24) & 0x01) != 0) } #[doc = "Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge"] #[inline(always)] pub fn dotclk_pol(&self) -> DOTCLK_POL_R { DOTCLK_POL_R::new(((self.bits >> 25) & 0x01) != 0) } #[doc = "Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period"] #[inline(always)] pub fn hsync_pol(&self) -> HSYNC_POL_R { HSYNC_POL_R::new(((self.bits >> 26) & 0x01) != 0) } #[doc = "Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period"] #[inline(always)] pub fn vsync_pol(&self) -> VSYNC_POL_R { VSYNC_POL_R::new(((self.bits >> 27) & 0x01) != 0) } #[doc = "Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK"] #[inline(always)] pub fn enable_present(&self) -> ENABLE_PRESENT_R { ENABLE_PRESENT_R::new(((self.bits >> 28) & 0x01) != 0) } } impl W { #[doc = "Bits 0:17 - Number of units for which VSYNC signal is active"] #[inline(always)] pub fn vsync_pulse_width(&mut self) -> VSYNC_PULSE_WIDTH_W { VSYNC_PULSE_WIDTH_W { w: self } } #[doc = "Bit 18 - When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line"] #[inline(always)] pub fn half_line_mode(&mut self) -> HALF_LINE_MODE_W { HALF_LINE_MODE_W { w: self } } #[doc = "Bit 19 - Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i"] #[inline(always)] pub fn half_line(&mut self) -> HALF_LINE_W { HALF_LINE_W { w: self } } #[doc = "Bit 20 - Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles"] #[inline(always)] pub fn vsync_pulse_width_unit(&mut self) -> VSYNC_PULSE_WIDTH_UNIT_W { VSYNC_PULSE_WIDTH_UNIT_W { w: self } } #[doc = "Bit 21 - Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles"] #[inline(always)] pub fn vsync_period_unit(&mut self) -> VSYNC_PERIOD_UNIT_W { VSYNC_PERIOD_UNIT_W { w: self } } #[doc = "Bit 24 - Default 0 active low during valid data transfer on each horizontal line."] #[inline(always)] pub fn enable_pol(&mut self) -> ENABLE_POL_W { ENABLE_POL_W { w: self } } #[doc = "Bit 25 - Default is data launched at negative edge of DOTCLK and captured at positive edge"] #[inline(always)] pub fn dotclk_pol(&mut self) -> DOTCLK_POL_W { DOTCLK_POL_W { w: self } } #[doc = "Bit 26 - Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period"] #[inline(always)] pub fn hsync_pol(&mut self) -> HSYNC_POL_W { HSYNC_POL_W { w: self } } #[doc = "Bit 27 - Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period"] #[inline(always)] pub fn vsync_pol(&mut self) -> VSYNC_POL_W { VSYNC_POL_W { w: self } } #[doc = "Bit 28 - Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK"] #[inline(always)] pub fn enable_present(&mut self) -> ENABLE_PRESENT_W { ENABLE_PRESENT_W { w: self } } }