List of all items

Structs

• R
• Reg
• RegisterBlock
• W
• anatop_usb_otg1_id_select_input::DAISY_W
• anatop_usb_otg2_id_select_input::DAISY_W
• canfd_ipp_ind_canrx_select_input::DAISY_W
• ccm_pmic_ready_select_input::DAISY_W
• csi_data02_select_input::DAISY_W
• csi_data03_select_input::DAISY_W
• csi_data04_select_input::DAISY_W
• csi_data05_select_input::DAISY_W
• csi_data06_select_input::DAISY_W
• csi_data07_select_input::DAISY_W
• csi_data08_select_input::DAISY_W
• csi_data09_select_input::DAISY_W
• csi_hsync_select_input::DAISY_W
• csi_pixclk_select_input::DAISY_W
• csi_vsync_select_input::DAISY_W
• enet0_rxdata_select_input::DAISY_W
• enet0_timer_select_input::DAISY_W
• enet1_rxdata_select_input::DAISY_W
• enet2_ipg_clk_rmii_select_input::DAISY_W
• enet2_ipp_ind_mac0_mdio_select_input::DAISY_W
• enet2_ipp_ind_mac0_rxdata_select_input_0::DAISY_W
• enet2_ipp_ind_mac0_rxdata_select_input_1::DAISY_W
• enet2_ipp_ind_mac0_rxen_select_input::DAISY_W
• enet2_ipp_ind_mac0_rxerr_select_input::DAISY_W
• enet2_ipp_ind_mac0_timer_select_input_0::DAISY_W
• enet2_ipp_ind_mac0_txclk_select_input::DAISY_W
• enet_ipg_clk_rmii_select_input::DAISY_W
• enet_mdio_select_input::DAISY_W
• enet_rxen_select_input::DAISY_W
• enet_rxerr_select_input::DAISY_W
• enet_txclk_select_input::DAISY_W
• flexcan1_rx_select_input::DAISY_W
• flexcan2_rx_select_input::DAISY_W
• flexpwm1_pwma0_select_input::DAISY_W
• flexpwm1_pwma1_select_input::DAISY_W
• flexpwm1_pwma2_select_input::DAISY_W
• flexpwm1_pwma3_select_input::DAISY_W
• flexpwm1_pwmb0_select_input::DAISY_W
• flexpwm1_pwmb1_select_input::DAISY_W
• flexpwm1_pwmb2_select_input::DAISY_W
• flexpwm1_pwmb3_select_input::DAISY_W
• flexpwm2_pwma0_select_input::DAISY_W
• flexpwm2_pwma1_select_input::DAISY_W
• flexpwm2_pwma2_select_input::DAISY_W
• flexpwm2_pwma3_select_input::DAISY_W
• flexpwm2_pwmb0_select_input::DAISY_W
• flexpwm2_pwmb1_select_input::DAISY_W
• flexpwm2_pwmb2_select_input::DAISY_W
• flexpwm2_pwmb3_select_input::DAISY_W
• flexpwm4_pwma0_select_input::DAISY_W
• flexpwm4_pwma1_select_input::DAISY_W
• flexpwm4_pwma2_select_input::DAISY_W
• flexpwm4_pwma3_select_input::DAISY_W
• flexspi2_ipp_ind_dqs_fa_select_input::DAISY_W
• flexspi2_ipp_ind_io_fa_bit0_select_input::DAISY_W
• flexspi2_ipp_ind_io_fa_bit1_select_input::DAISY_W
• flexspi2_ipp_ind_io_fa_bit2_select_input::DAISY_W
• flexspi2_ipp_ind_io_fa_bit3_select_input::DAISY_W
• flexspi2_ipp_ind_io_fb_bit0_select_input::DAISY_W
• flexspi2_ipp_ind_io_fb_bit1_select_input::DAISY_W
• flexspi2_ipp_ind_io_fb_bit2_select_input::DAISY_W
• flexspi2_ipp_ind_io_fb_bit3_select_input::DAISY_W
• flexspi2_ipp_ind_sck_fa_select_input::DAISY_W
• flexspi2_ipp_ind_sck_fb_select_input::DAISY_W
• flexspia_data0_select_input::DAISY_W
• flexspia_data1_select_input::DAISY_W
• flexspia_data2_select_input::DAISY_W
• flexspia_data3_select_input::DAISY_W
• flexspia_dqs_select_input::DAISY_W
• flexspia_sck_select_input::DAISY_W
• flexspib_data0_select_input::DAISY_W
• flexspib_data1_select_input::DAISY_W
• flexspib_data2_select_input::DAISY_W
• flexspib_data3_select_input::DAISY_W
• gpt1_ipp_ind_capin1_select_input::DAISY_W
• gpt1_ipp_ind_capin2_select_input::DAISY_W
• gpt1_ipp_ind_clkin_select_input::DAISY_W
• gpt2_ipp_ind_capin1_select_input::DAISY_W
• gpt2_ipp_ind_capin2_select_input::DAISY_W
• gpt2_ipp_ind_clkin_select_input::DAISY_W
• lpi2c1_scl_select_input::DAISY_W
• lpi2c1_sda_select_input::DAISY_W
• lpi2c2_scl_select_input::DAISY_W
• lpi2c2_sda_select_input::DAISY_W
• lpi2c3_scl_select_input::DAISY_W
• lpi2c3_sda_select_input::DAISY_W
• lpi2c4_scl_select_input::DAISY_W
• lpi2c4_sda_select_input::DAISY_W
• lpspi1_pcs0_select_input::DAISY_W
• lpspi1_sck_select_input::DAISY_W
• lpspi1_sdi_select_input::DAISY_W
• lpspi1_sdo_select_input::DAISY_W
• lpspi2_pcs0_select_input::DAISY_W
• lpspi2_sck_select_input::DAISY_W
• lpspi2_sdi_select_input::DAISY_W
• lpspi2_sdo_select_input::DAISY_W
• lpspi3_pcs0_select_input::DAISY_W
• lpspi3_sck_select_input::DAISY_W
• lpspi3_sdi_select_input::DAISY_W
• lpspi3_sdo_select_input::DAISY_W
• lpspi4_pcs0_select_input::DAISY_W
• lpspi4_sck_select_input::DAISY_W
• lpspi4_sdi_select_input::DAISY_W
• lpspi4_sdo_select_input::DAISY_W
• lpuart2_rx_select_input::DAISY_W
• lpuart2_tx_select_input::DAISY_W
• lpuart3_cts_b_select_input::DAISY_W
• lpuart3_rx_select_input::DAISY_W
• lpuart3_tx_select_input::DAISY_W
• lpuart4_rx_select_input::DAISY_W
• lpuart4_tx_select_input::DAISY_W
• lpuart5_rx_select_input::DAISY_W
• lpuart5_tx_select_input::DAISY_W
• lpuart6_rx_select_input::DAISY_W
• lpuart6_tx_select_input::DAISY_W
• lpuart7_rx_select_input::DAISY_W
• lpuart7_tx_select_input::DAISY_W
• lpuart8_rx_select_input::DAISY_W
• lpuart8_tx_select_input::DAISY_W
• nmi_select_input::DAISY_W
• qtimer2_timer0_select_input::DAISY_W
• qtimer2_timer1_select_input::DAISY_W
• qtimer2_timer2_select_input::DAISY_W
• qtimer2_timer3_select_input::DAISY_W
• qtimer3_timer0_select_input::DAISY_W
• qtimer3_timer1_select_input::DAISY_W
• qtimer3_timer2_select_input::DAISY_W
• qtimer3_timer3_select_input::DAISY_W
• sai1_mclk2_select_input::DAISY_W
• sai1_rx_bclk_select_input::DAISY_W
• sai1_rx_data0_select_input::DAISY_W
• sai1_rx_data1_select_input::DAISY_W
• sai1_rx_data2_select_input::DAISY_W
• sai1_rx_data3_select_input::DAISY_W
• sai1_rx_sync_select_input::DAISY_W
• sai1_tx_bclk_select_input::DAISY_W
• sai1_tx_sync_select_input::DAISY_W
• sai2_mclk2_select_input::DAISY_W
• sai2_rx_bclk_select_input::DAISY_W
• sai2_rx_data0_select_input::DAISY_W
• sai2_rx_sync_select_input::DAISY_W
• sai2_tx_bclk_select_input::DAISY_W
• sai2_tx_sync_select_input::DAISY_W
• sai3_ipg_clk_sai_mclk_select_input_2::DAISY_W
• sai3_ipp_ind_sai_rxbclk_select_input::DAISY_W
• sai3_ipp_ind_sai_rxdata_select_input_0::DAISY_W
• sai3_ipp_ind_sai_rxsync_select_input::DAISY_W
• sai3_ipp_ind_sai_txbclk_select_input::DAISY_W
• sai3_ipp_ind_sai_txsync_select_input::DAISY_W
• semc_i_ipp_ind_dqs4_select_input::DAISY_W
• spdif_in_select_input::DAISY_W
• sw_mux_ctl_pad_gpio_ad_b0_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_00::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_01::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_02::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_03::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_04::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_05::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_06::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_07::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_08::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_09::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_10::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_11::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_12::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_12::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_13::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_13::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_14::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_14::SION_W
• sw_mux_ctl_pad_gpio_ad_b0_15::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b0_15::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_00::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_01::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_02::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_03::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_04::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_05::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_06::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_07::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_08::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_09::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_10::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_11::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_12::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_12::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_13::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_13::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_14::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_14::SION_W
• sw_mux_ctl_pad_gpio_ad_b1_15::MUX_MODE_W
• sw_mux_ctl_pad_gpio_ad_b1_15::SION_W
• sw_mux_ctl_pad_gpio_b0_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_00::SION_W
• sw_mux_ctl_pad_gpio_b0_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_01::SION_W
• sw_mux_ctl_pad_gpio_b0_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_02::SION_W
• sw_mux_ctl_pad_gpio_b0_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_03::SION_W
• sw_mux_ctl_pad_gpio_b0_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_04::SION_W
• sw_mux_ctl_pad_gpio_b0_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_05::SION_W
• sw_mux_ctl_pad_gpio_b0_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_06::SION_W
• sw_mux_ctl_pad_gpio_b0_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_07::SION_W
• sw_mux_ctl_pad_gpio_b0_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_08::SION_W
• sw_mux_ctl_pad_gpio_b0_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_09::SION_W
• sw_mux_ctl_pad_gpio_b0_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_10::SION_W
• sw_mux_ctl_pad_gpio_b0_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_11::SION_W
• sw_mux_ctl_pad_gpio_b0_12::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_12::SION_W
• sw_mux_ctl_pad_gpio_b0_13::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_13::SION_W
• sw_mux_ctl_pad_gpio_b0_14::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_14::SION_W
• sw_mux_ctl_pad_gpio_b0_15::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b0_15::SION_W
• sw_mux_ctl_pad_gpio_b1_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_00::SION_W
• sw_mux_ctl_pad_gpio_b1_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_01::SION_W
• sw_mux_ctl_pad_gpio_b1_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_02::SION_W
• sw_mux_ctl_pad_gpio_b1_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_03::SION_W
• sw_mux_ctl_pad_gpio_b1_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_04::SION_W
• sw_mux_ctl_pad_gpio_b1_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_05::SION_W
• sw_mux_ctl_pad_gpio_b1_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_06::SION_W
• sw_mux_ctl_pad_gpio_b1_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_07::SION_W
• sw_mux_ctl_pad_gpio_b1_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_08::SION_W
• sw_mux_ctl_pad_gpio_b1_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_09::SION_W
• sw_mux_ctl_pad_gpio_b1_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_10::SION_W
• sw_mux_ctl_pad_gpio_b1_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_11::SION_W
• sw_mux_ctl_pad_gpio_b1_12::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_12::SION_W
• sw_mux_ctl_pad_gpio_b1_13::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_13::SION_W
• sw_mux_ctl_pad_gpio_b1_14::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_14::SION_W
• sw_mux_ctl_pad_gpio_b1_15::MUX_MODE_W
• sw_mux_ctl_pad_gpio_b1_15::SION_W
• sw_mux_ctl_pad_gpio_emc_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_00::SION_W
• sw_mux_ctl_pad_gpio_emc_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_01::SION_W
• sw_mux_ctl_pad_gpio_emc_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_02::SION_W
• sw_mux_ctl_pad_gpio_emc_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_03::SION_W
• sw_mux_ctl_pad_gpio_emc_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_04::SION_W
• sw_mux_ctl_pad_gpio_emc_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_05::SION_W
• sw_mux_ctl_pad_gpio_emc_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_06::SION_W
• sw_mux_ctl_pad_gpio_emc_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_07::SION_W
• sw_mux_ctl_pad_gpio_emc_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_08::SION_W
• sw_mux_ctl_pad_gpio_emc_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_09::SION_W
• sw_mux_ctl_pad_gpio_emc_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_10::SION_W
• sw_mux_ctl_pad_gpio_emc_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_11::SION_W
• sw_mux_ctl_pad_gpio_emc_12::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_12::SION_W
• sw_mux_ctl_pad_gpio_emc_13::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_13::SION_W
• sw_mux_ctl_pad_gpio_emc_14::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_14::SION_W
• sw_mux_ctl_pad_gpio_emc_15::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_15::SION_W
• sw_mux_ctl_pad_gpio_emc_16::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_16::SION_W
• sw_mux_ctl_pad_gpio_emc_17::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_17::SION_W
• sw_mux_ctl_pad_gpio_emc_18::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_18::SION_W
• sw_mux_ctl_pad_gpio_emc_19::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_19::SION_W
• sw_mux_ctl_pad_gpio_emc_20::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_20::SION_W
• sw_mux_ctl_pad_gpio_emc_21::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_21::SION_W
• sw_mux_ctl_pad_gpio_emc_22::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_22::SION_W
• sw_mux_ctl_pad_gpio_emc_23::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_23::SION_W
• sw_mux_ctl_pad_gpio_emc_24::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_24::SION_W
• sw_mux_ctl_pad_gpio_emc_25::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_25::SION_W
• sw_mux_ctl_pad_gpio_emc_26::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_26::SION_W
• sw_mux_ctl_pad_gpio_emc_27::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_27::SION_W
• sw_mux_ctl_pad_gpio_emc_28::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_28::SION_W
• sw_mux_ctl_pad_gpio_emc_29::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_29::SION_W
• sw_mux_ctl_pad_gpio_emc_30::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_30::SION_W
• sw_mux_ctl_pad_gpio_emc_31::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_31::SION_W
• sw_mux_ctl_pad_gpio_emc_32::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_32::SION_W
• sw_mux_ctl_pad_gpio_emc_33::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_33::SION_W
• sw_mux_ctl_pad_gpio_emc_34::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_34::SION_W
• sw_mux_ctl_pad_gpio_emc_35::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_35::SION_W
• sw_mux_ctl_pad_gpio_emc_36::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_36::SION_W
• sw_mux_ctl_pad_gpio_emc_37::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_37::SION_W
• sw_mux_ctl_pad_gpio_emc_38::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_38::SION_W
• sw_mux_ctl_pad_gpio_emc_39::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_39::SION_W
• sw_mux_ctl_pad_gpio_emc_40::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_40::SION_W
• sw_mux_ctl_pad_gpio_emc_41::MUX_MODE_W
• sw_mux_ctl_pad_gpio_emc_41::SION_W
• sw_mux_ctl_pad_gpio_sd_b0_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b0_00::SION_W
• sw_mux_ctl_pad_gpio_sd_b0_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b0_01::SION_W
• sw_mux_ctl_pad_gpio_sd_b0_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b0_02::SION_W
• sw_mux_ctl_pad_gpio_sd_b0_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b0_03::SION_W
• sw_mux_ctl_pad_gpio_sd_b0_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b0_04::SION_W
• sw_mux_ctl_pad_gpio_sd_b0_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b0_05::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_00::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_01::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_02::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_03::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_04::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_05::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_06::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_07::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_08::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_09::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_10::SION_W
• sw_mux_ctl_pad_gpio_sd_b1_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_sd_b1_11::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_00::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_01::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_02::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_03::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_04::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_05::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_06::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_07::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_07::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_08::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_08::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_09::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_09::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_10::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_10::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_11::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_11::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_12::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b0_12::SION_W
• sw_mux_ctl_pad_gpio_spi_b0_13::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_00::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_00::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_01::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_01::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_02::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_02::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_03::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_03::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_04::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_04::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_05::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_05::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_06::MUX_MODE_W
• sw_mux_ctl_pad_gpio_spi_b1_06::SION_W
• sw_mux_ctl_pad_gpio_spi_b1_07::SION_W
• sw_pad_ctl_pad_gpio_ad_b0_00::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_00::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_00::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_00::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_00::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_00::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_00::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_00::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_01::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_01::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_01::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_01::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_01::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_01::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_01::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_01::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_02::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_02::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_02::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_02::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_02::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_02::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_02::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_02::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_03::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_03::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_03::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_03::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_03::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_03::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_03::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_03::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_04::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_04::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_04::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_04::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_04::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_04::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_04::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_04::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_05::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_05::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_05::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_05::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_05::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_05::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_05::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_05::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_06::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_06::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_06::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_06::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_06::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_06::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_06::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_06::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_07::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_07::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_07::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_07::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_07::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_07::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_07::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_07::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_08::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_08::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_08::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_08::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_08::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_08::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_08::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_08::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_09::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_09::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_09::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_09::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_09::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_09::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_09::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_09::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_10::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_10::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_10::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_10::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_10::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_10::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_10::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_10::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_11::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_11::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_11::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_11::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_11::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_11::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_11::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_11::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_12::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_12::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_12::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_12::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_12::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_12::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_12::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_12::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_13::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_13::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_13::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_13::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_13::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_13::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_13::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_13::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_14::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_14::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_14::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_14::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_14::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_14::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_14::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_14::SRE_W
• sw_pad_ctl_pad_gpio_ad_b0_15::DSE_W
• sw_pad_ctl_pad_gpio_ad_b0_15::HYS_W
• sw_pad_ctl_pad_gpio_ad_b0_15::ODE_W
• sw_pad_ctl_pad_gpio_ad_b0_15::PKE_W
• sw_pad_ctl_pad_gpio_ad_b0_15::PUE_W
• sw_pad_ctl_pad_gpio_ad_b0_15::PUS_W
• sw_pad_ctl_pad_gpio_ad_b0_15::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b0_15::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_00::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_00::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_00::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_00::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_00::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_00::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_00::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_00::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_01::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_01::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_01::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_01::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_01::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_01::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_01::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_01::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_02::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_02::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_02::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_02::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_02::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_02::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_02::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_02::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_03::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_03::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_03::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_03::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_03::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_03::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_03::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_03::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_04::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_04::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_04::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_04::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_04::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_04::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_04::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_04::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_05::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_05::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_05::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_05::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_05::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_05::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_05::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_05::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_06::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_06::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_06::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_06::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_06::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_06::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_06::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_06::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_07::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_07::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_07::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_07::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_07::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_07::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_07::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_07::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_08::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_08::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_08::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_08::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_08::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_08::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_08::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_08::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_09::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_09::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_09::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_09::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_09::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_09::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_09::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_09::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_10::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_10::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_10::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_10::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_10::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_10::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_10::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_10::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_11::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_11::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_11::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_11::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_11::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_11::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_11::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_11::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_12::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_12::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_12::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_12::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_12::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_12::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_12::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_12::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_13::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_13::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_13::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_13::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_13::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_13::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_13::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_13::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_14::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_14::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_14::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_14::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_14::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_14::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_14::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_14::SRE_W
• sw_pad_ctl_pad_gpio_ad_b1_15::DSE_W
• sw_pad_ctl_pad_gpio_ad_b1_15::HYS_W
• sw_pad_ctl_pad_gpio_ad_b1_15::ODE_W
• sw_pad_ctl_pad_gpio_ad_b1_15::PKE_W
• sw_pad_ctl_pad_gpio_ad_b1_15::PUE_W
• sw_pad_ctl_pad_gpio_ad_b1_15::PUS_W
• sw_pad_ctl_pad_gpio_ad_b1_15::SPEED_W
• sw_pad_ctl_pad_gpio_ad_b1_15::SRE_W
• sw_pad_ctl_pad_gpio_b0_00::DSE_W
• sw_pad_ctl_pad_gpio_b0_00::HYS_W
• sw_pad_ctl_pad_gpio_b0_00::ODE_W
• sw_pad_ctl_pad_gpio_b0_00::PKE_W
• sw_pad_ctl_pad_gpio_b0_00::PUE_W
• sw_pad_ctl_pad_gpio_b0_00::PUS_W
• sw_pad_ctl_pad_gpio_b0_00::SPEED_W
• sw_pad_ctl_pad_gpio_b0_00::SRE_W
• sw_pad_ctl_pad_gpio_b0_01::DSE_W
• sw_pad_ctl_pad_gpio_b0_01::HYS_W
• sw_pad_ctl_pad_gpio_b0_01::ODE_W
• sw_pad_ctl_pad_gpio_b0_01::PKE_W
• sw_pad_ctl_pad_gpio_b0_01::PUE_W
• sw_pad_ctl_pad_gpio_b0_01::PUS_W
• sw_pad_ctl_pad_gpio_b0_01::SPEED_W
• sw_pad_ctl_pad_gpio_b0_01::SRE_W
• sw_pad_ctl_pad_gpio_b0_02::DSE_W
• sw_pad_ctl_pad_gpio_b0_02::HYS_W
• sw_pad_ctl_pad_gpio_b0_02::ODE_W
• sw_pad_ctl_pad_gpio_b0_02::PKE_W
• sw_pad_ctl_pad_gpio_b0_02::PUE_W
• sw_pad_ctl_pad_gpio_b0_02::PUS_W
• sw_pad_ctl_pad_gpio_b0_02::SPEED_W
• sw_pad_ctl_pad_gpio_b0_02::SRE_W
• sw_pad_ctl_pad_gpio_b0_03::DSE_W
• sw_pad_ctl_pad_gpio_b0_03::HYS_W
• sw_pad_ctl_pad_gpio_b0_03::ODE_W
• sw_pad_ctl_pad_gpio_b0_03::PKE_W
• sw_pad_ctl_pad_gpio_b0_03::PUE_W
• sw_pad_ctl_pad_gpio_b0_03::PUS_W
• sw_pad_ctl_pad_gpio_b0_03::SPEED_W
• sw_pad_ctl_pad_gpio_b0_03::SRE_W
• sw_pad_ctl_pad_gpio_b0_04::DSE_W
• sw_pad_ctl_pad_gpio_b0_04::HYS_W
• sw_pad_ctl_pad_gpio_b0_04::ODE_W
• sw_pad_ctl_pad_gpio_b0_04::PKE_W
• sw_pad_ctl_pad_gpio_b0_04::PUE_W
• sw_pad_ctl_pad_gpio_b0_04::PUS_W
• sw_pad_ctl_pad_gpio_b0_04::SPEED_W
• sw_pad_ctl_pad_gpio_b0_04::SRE_W
• sw_pad_ctl_pad_gpio_b0_05::DSE_W
• sw_pad_ctl_pad_gpio_b0_05::HYS_W
• sw_pad_ctl_pad_gpio_b0_05::ODE_W
• sw_pad_ctl_pad_gpio_b0_05::PKE_W
• sw_pad_ctl_pad_gpio_b0_05::PUE_W
• sw_pad_ctl_pad_gpio_b0_05::PUS_W
• sw_pad_ctl_pad_gpio_b0_05::SPEED_W
• sw_pad_ctl_pad_gpio_b0_05::SRE_W
• sw_pad_ctl_pad_gpio_b0_06::DSE_W
• sw_pad_ctl_pad_gpio_b0_06::HYS_W
• sw_pad_ctl_pad_gpio_b0_06::ODE_W
• sw_pad_ctl_pad_gpio_b0_06::PKE_W
• sw_pad_ctl_pad_gpio_b0_06::PUE_W
• sw_pad_ctl_pad_gpio_b0_06::PUS_W
• sw_pad_ctl_pad_gpio_b0_06::SPEED_W
• sw_pad_ctl_pad_gpio_b0_06::SRE_W
• sw_pad_ctl_pad_gpio_b0_07::DSE_W
• sw_pad_ctl_pad_gpio_b0_07::HYS_W
• sw_pad_ctl_pad_gpio_b0_07::ODE_W
• sw_pad_ctl_pad_gpio_b0_07::PKE_W
• sw_pad_ctl_pad_gpio_b0_07::PUE_W
• sw_pad_ctl_pad_gpio_b0_07::PUS_W
• sw_pad_ctl_pad_gpio_b0_07::SPEED_W
• sw_pad_ctl_pad_gpio_b0_07::SRE_W
• sw_pad_ctl_pad_gpio_b0_08::DSE_W
• sw_pad_ctl_pad_gpio_b0_08::HYS_W
• sw_pad_ctl_pad_gpio_b0_08::ODE_W
• sw_pad_ctl_pad_gpio_b0_08::PKE_W
• sw_pad_ctl_pad_gpio_b0_08::PUE_W
• sw_pad_ctl_pad_gpio_b0_08::PUS_W
• sw_pad_ctl_pad_gpio_b0_08::SPEED_W
• sw_pad_ctl_pad_gpio_b0_08::SRE_W
• sw_pad_ctl_pad_gpio_b0_09::DSE_W
• sw_pad_ctl_pad_gpio_b0_09::HYS_W
• sw_pad_ctl_pad_gpio_b0_09::ODE_W
• sw_pad_ctl_pad_gpio_b0_09::PKE_W
• sw_pad_ctl_pad_gpio_b0_09::PUE_W
• sw_pad_ctl_pad_gpio_b0_09::PUS_W
• sw_pad_ctl_pad_gpio_b0_09::SPEED_W
• sw_pad_ctl_pad_gpio_b0_09::SRE_W
• sw_pad_ctl_pad_gpio_b0_10::DSE_W
• sw_pad_ctl_pad_gpio_b0_10::HYS_W
• sw_pad_ctl_pad_gpio_b0_10::ODE_W
• sw_pad_ctl_pad_gpio_b0_10::PKE_W
• sw_pad_ctl_pad_gpio_b0_10::PUE_W
• sw_pad_ctl_pad_gpio_b0_10::PUS_W
• sw_pad_ctl_pad_gpio_b0_10::SPEED_W
• sw_pad_ctl_pad_gpio_b0_10::SRE_W
• sw_pad_ctl_pad_gpio_b0_11::DSE_W
• sw_pad_ctl_pad_gpio_b0_11::HYS_W
• sw_pad_ctl_pad_gpio_b0_11::ODE_W
• sw_pad_ctl_pad_gpio_b0_11::PKE_W
• sw_pad_ctl_pad_gpio_b0_11::PUE_W
• sw_pad_ctl_pad_gpio_b0_11::PUS_W
• sw_pad_ctl_pad_gpio_b0_11::SPEED_W
• sw_pad_ctl_pad_gpio_b0_11::SRE_W
• sw_pad_ctl_pad_gpio_b0_12::DSE_W
• sw_pad_ctl_pad_gpio_b0_12::HYS_W
• sw_pad_ctl_pad_gpio_b0_12::ODE_W
• sw_pad_ctl_pad_gpio_b0_12::PKE_W
• sw_pad_ctl_pad_gpio_b0_12::PUE_W
• sw_pad_ctl_pad_gpio_b0_12::PUS_W
• sw_pad_ctl_pad_gpio_b0_12::SPEED_W
• sw_pad_ctl_pad_gpio_b0_12::SRE_W
• sw_pad_ctl_pad_gpio_b0_13::DSE_W
• sw_pad_ctl_pad_gpio_b0_13::HYS_W
• sw_pad_ctl_pad_gpio_b0_13::ODE_W
• sw_pad_ctl_pad_gpio_b0_13::PKE_W
• sw_pad_ctl_pad_gpio_b0_13::PUE_W
• sw_pad_ctl_pad_gpio_b0_13::PUS_W
• sw_pad_ctl_pad_gpio_b0_13::SPEED_W
• sw_pad_ctl_pad_gpio_b0_13::SRE_W
• sw_pad_ctl_pad_gpio_b0_14::DSE_W
• sw_pad_ctl_pad_gpio_b0_14::HYS_W
• sw_pad_ctl_pad_gpio_b0_14::ODE_W
• sw_pad_ctl_pad_gpio_b0_14::PKE_W
• sw_pad_ctl_pad_gpio_b0_14::PUE_W
• sw_pad_ctl_pad_gpio_b0_14::PUS_W
• sw_pad_ctl_pad_gpio_b0_14::SPEED_W
• sw_pad_ctl_pad_gpio_b0_14::SRE_W
• sw_pad_ctl_pad_gpio_b0_15::DSE_W
• sw_pad_ctl_pad_gpio_b0_15::HYS_W
• sw_pad_ctl_pad_gpio_b0_15::ODE_W
• sw_pad_ctl_pad_gpio_b0_15::PKE_W
• sw_pad_ctl_pad_gpio_b0_15::PUE_W
• sw_pad_ctl_pad_gpio_b0_15::PUS_W
• sw_pad_ctl_pad_gpio_b0_15::SPEED_W
• sw_pad_ctl_pad_gpio_b0_15::SRE_W
• sw_pad_ctl_pad_gpio_b1_00::DSE_W
• sw_pad_ctl_pad_gpio_b1_00::HYS_W
• sw_pad_ctl_pad_gpio_b1_00::ODE_W
• sw_pad_ctl_pad_gpio_b1_00::PKE_W
• sw_pad_ctl_pad_gpio_b1_00::PUE_W
• sw_pad_ctl_pad_gpio_b1_00::PUS_W
• sw_pad_ctl_pad_gpio_b1_00::SPEED_W
• sw_pad_ctl_pad_gpio_b1_00::SRE_W
• sw_pad_ctl_pad_gpio_b1_01::DSE_W
• sw_pad_ctl_pad_gpio_b1_01::HYS_W
• sw_pad_ctl_pad_gpio_b1_01::ODE_W
• sw_pad_ctl_pad_gpio_b1_01::PKE_W
• sw_pad_ctl_pad_gpio_b1_01::PUE_W
• sw_pad_ctl_pad_gpio_b1_01::PUS_W
• sw_pad_ctl_pad_gpio_b1_01::SPEED_W
• sw_pad_ctl_pad_gpio_b1_01::SRE_W
• sw_pad_ctl_pad_gpio_b1_02::DSE_W
• sw_pad_ctl_pad_gpio_b1_02::HYS_W
• sw_pad_ctl_pad_gpio_b1_02::ODE_W
• sw_pad_ctl_pad_gpio_b1_02::PKE_W
• sw_pad_ctl_pad_gpio_b1_02::PUE_W
• sw_pad_ctl_pad_gpio_b1_02::PUS_W
• sw_pad_ctl_pad_gpio_b1_02::SPEED_W
• sw_pad_ctl_pad_gpio_b1_02::SRE_W
• sw_pad_ctl_pad_gpio_b1_03::DSE_W
• sw_pad_ctl_pad_gpio_b1_03::HYS_W
• sw_pad_ctl_pad_gpio_b1_03::ODE_W
• sw_pad_ctl_pad_gpio_b1_03::PKE_W
• sw_pad_ctl_pad_gpio_b1_03::PUE_W
• sw_pad_ctl_pad_gpio_b1_03::PUS_W
• sw_pad_ctl_pad_gpio_b1_03::SPEED_W
• sw_pad_ctl_pad_gpio_b1_03::SRE_W
• sw_pad_ctl_pad_gpio_b1_04::DSE_W
• sw_pad_ctl_pad_gpio_b1_04::HYS_W
• sw_pad_ctl_pad_gpio_b1_04::ODE_W
• sw_pad_ctl_pad_gpio_b1_04::PKE_W
• sw_pad_ctl_pad_gpio_b1_04::PUE_W
• sw_pad_ctl_pad_gpio_b1_04::PUS_W
• sw_pad_ctl_pad_gpio_b1_04::SPEED_W
• sw_pad_ctl_pad_gpio_b1_04::SRE_W
• sw_pad_ctl_pad_gpio_b1_05::DSE_W
• sw_pad_ctl_pad_gpio_b1_05::HYS_W
• sw_pad_ctl_pad_gpio_b1_05::ODE_W
• sw_pad_ctl_pad_gpio_b1_05::PKE_W
• sw_pad_ctl_pad_gpio_b1_05::PUE_W
• sw_pad_ctl_pad_gpio_b1_05::PUS_W
• sw_pad_ctl_pad_gpio_b1_05::SPEED_W
• sw_pad_ctl_pad_gpio_b1_05::SRE_W
• sw_pad_ctl_pad_gpio_b1_06::DSE_W
• sw_pad_ctl_pad_gpio_b1_06::HYS_W
• sw_pad_ctl_pad_gpio_b1_06::ODE_W
• sw_pad_ctl_pad_gpio_b1_06::PKE_W
• sw_pad_ctl_pad_gpio_b1_06::PUE_W
• sw_pad_ctl_pad_gpio_b1_06::PUS_W
• sw_pad_ctl_pad_gpio_b1_06::SPEED_W
• sw_pad_ctl_pad_gpio_b1_06::SRE_W
• sw_pad_ctl_pad_gpio_b1_07::DSE_W
• sw_pad_ctl_pad_gpio_b1_07::HYS_W
• sw_pad_ctl_pad_gpio_b1_07::ODE_W
• sw_pad_ctl_pad_gpio_b1_07::PKE_W
• sw_pad_ctl_pad_gpio_b1_07::PUE_W
• sw_pad_ctl_pad_gpio_b1_07::PUS_W
• sw_pad_ctl_pad_gpio_b1_07::SPEED_W
• sw_pad_ctl_pad_gpio_b1_07::SRE_W
• sw_pad_ctl_pad_gpio_b1_08::DSE_W
• sw_pad_ctl_pad_gpio_b1_08::HYS_W
• sw_pad_ctl_pad_gpio_b1_08::ODE_W
• sw_pad_ctl_pad_gpio_b1_08::PKE_W
• sw_pad_ctl_pad_gpio_b1_08::PUE_W
• sw_pad_ctl_pad_gpio_b1_08::PUS_W
• sw_pad_ctl_pad_gpio_b1_08::SPEED_W
• sw_pad_ctl_pad_gpio_b1_08::SRE_W
• sw_pad_ctl_pad_gpio_b1_09::DSE_W
• sw_pad_ctl_pad_gpio_b1_09::HYS_W
• sw_pad_ctl_pad_gpio_b1_09::ODE_W
• sw_pad_ctl_pad_gpio_b1_09::PKE_W
• sw_pad_ctl_pad_gpio_b1_09::PUE_W
• sw_pad_ctl_pad_gpio_b1_09::PUS_W
• sw_pad_ctl_pad_gpio_b1_09::SPEED_W
• sw_pad_ctl_pad_gpio_b1_09::SRE_W
• sw_pad_ctl_pad_gpio_b1_10::DSE_W
• sw_pad_ctl_pad_gpio_b1_10::HYS_W
• sw_pad_ctl_pad_gpio_b1_10::ODE_W
• sw_pad_ctl_pad_gpio_b1_10::PKE_W
• sw_pad_ctl_pad_gpio_b1_10::PUE_W
• sw_pad_ctl_pad_gpio_b1_10::PUS_W
• sw_pad_ctl_pad_gpio_b1_10::SPEED_W
• sw_pad_ctl_pad_gpio_b1_10::SRE_W
• sw_pad_ctl_pad_gpio_b1_11::DSE_W
• sw_pad_ctl_pad_gpio_b1_11::HYS_W
• sw_pad_ctl_pad_gpio_b1_11::ODE_W
• sw_pad_ctl_pad_gpio_b1_11::PKE_W
• sw_pad_ctl_pad_gpio_b1_11::PUE_W
• sw_pad_ctl_pad_gpio_b1_11::PUS_W
• sw_pad_ctl_pad_gpio_b1_11::SPEED_W
• sw_pad_ctl_pad_gpio_b1_11::SRE_W
• sw_pad_ctl_pad_gpio_b1_12::DSE_W
• sw_pad_ctl_pad_gpio_b1_12::HYS_W
• sw_pad_ctl_pad_gpio_b1_12::ODE_W
• sw_pad_ctl_pad_gpio_b1_12::PKE_W
• sw_pad_ctl_pad_gpio_b1_12::PUE_W
• sw_pad_ctl_pad_gpio_b1_12::PUS_W
• sw_pad_ctl_pad_gpio_b1_12::SPEED_W
• sw_pad_ctl_pad_gpio_b1_12::SRE_W
• sw_pad_ctl_pad_gpio_b1_13::DSE_W
• sw_pad_ctl_pad_gpio_b1_13::HYS_W
• sw_pad_ctl_pad_gpio_b1_13::ODE_W
• sw_pad_ctl_pad_gpio_b1_13::PKE_W
• sw_pad_ctl_pad_gpio_b1_13::PUE_W
• sw_pad_ctl_pad_gpio_b1_13::PUS_W
• sw_pad_ctl_pad_gpio_b1_13::SPEED_W
• sw_pad_ctl_pad_gpio_b1_13::SRE_W
• sw_pad_ctl_pad_gpio_b1_14::DSE_W
• sw_pad_ctl_pad_gpio_b1_14::HYS_W
• sw_pad_ctl_pad_gpio_b1_14::ODE_W
• sw_pad_ctl_pad_gpio_b1_14::PKE_W
• sw_pad_ctl_pad_gpio_b1_14::PUE_W
• sw_pad_ctl_pad_gpio_b1_14::PUS_W
• sw_pad_ctl_pad_gpio_b1_14::SPEED_W
• sw_pad_ctl_pad_gpio_b1_14::SRE_W
• sw_pad_ctl_pad_gpio_b1_15::DSE_W
• sw_pad_ctl_pad_gpio_b1_15::HYS_W
• sw_pad_ctl_pad_gpio_b1_15::ODE_W
• sw_pad_ctl_pad_gpio_b1_15::PKE_W
• sw_pad_ctl_pad_gpio_b1_15::PUE_W
• sw_pad_ctl_pad_gpio_b1_15::PUS_W
• sw_pad_ctl_pad_gpio_b1_15::SPEED_W
• sw_pad_ctl_pad_gpio_b1_15::SRE_W
• sw_pad_ctl_pad_gpio_emc_00::DSE_W
• sw_pad_ctl_pad_gpio_emc_00::HYS_W
• sw_pad_ctl_pad_gpio_emc_00::ODE_W
• sw_pad_ctl_pad_gpio_emc_00::PKE_W
• sw_pad_ctl_pad_gpio_emc_00::PUE_W
• sw_pad_ctl_pad_gpio_emc_00::PUS_W
• sw_pad_ctl_pad_gpio_emc_00::SPEED_W
• sw_pad_ctl_pad_gpio_emc_00::SRE_W
• sw_pad_ctl_pad_gpio_emc_01::DSE_W
• sw_pad_ctl_pad_gpio_emc_01::HYS_W
• sw_pad_ctl_pad_gpio_emc_01::ODE_W
• sw_pad_ctl_pad_gpio_emc_01::PKE_W
• sw_pad_ctl_pad_gpio_emc_01::PUE_W
• sw_pad_ctl_pad_gpio_emc_01::PUS_W
• sw_pad_ctl_pad_gpio_emc_01::SPEED_W
• sw_pad_ctl_pad_gpio_emc_01::SRE_W
• sw_pad_ctl_pad_gpio_emc_02::DSE_W
• sw_pad_ctl_pad_gpio_emc_02::HYS_W
• sw_pad_ctl_pad_gpio_emc_02::ODE_W
• sw_pad_ctl_pad_gpio_emc_02::PKE_W
• sw_pad_ctl_pad_gpio_emc_02::PUE_W
• sw_pad_ctl_pad_gpio_emc_02::PUS_W
• sw_pad_ctl_pad_gpio_emc_02::SPEED_W
• sw_pad_ctl_pad_gpio_emc_02::SRE_W
• sw_pad_ctl_pad_gpio_emc_03::DSE_W
• sw_pad_ctl_pad_gpio_emc_03::HYS_W
• sw_pad_ctl_pad_gpio_emc_03::ODE_W
• sw_pad_ctl_pad_gpio_emc_03::PKE_W
• sw_pad_ctl_pad_gpio_emc_03::PUE_W
• sw_pad_ctl_pad_gpio_emc_03::PUS_W
• sw_pad_ctl_pad_gpio_emc_03::SPEED_W
• sw_pad_ctl_pad_gpio_emc_03::SRE_W
• sw_pad_ctl_pad_gpio_emc_04::DSE_W
• sw_pad_ctl_pad_gpio_emc_04::HYS_W
• sw_pad_ctl_pad_gpio_emc_04::ODE_W
• sw_pad_ctl_pad_gpio_emc_04::PKE_W
• sw_pad_ctl_pad_gpio_emc_04::PUE_W
• sw_pad_ctl_pad_gpio_emc_04::PUS_W
• sw_pad_ctl_pad_gpio_emc_04::SPEED_W
• sw_pad_ctl_pad_gpio_emc_04::SRE_W
• sw_pad_ctl_pad_gpio_emc_05::DSE_W
• sw_pad_ctl_pad_gpio_emc_05::HYS_W
• sw_pad_ctl_pad_gpio_emc_05::ODE_W
• sw_pad_ctl_pad_gpio_emc_05::PKE_W
• sw_pad_ctl_pad_gpio_emc_05::PUE_W
• sw_pad_ctl_pad_gpio_emc_05::PUS_W
• sw_pad_ctl_pad_gpio_emc_05::SPEED_W
• sw_pad_ctl_pad_gpio_emc_05::SRE_W
• sw_pad_ctl_pad_gpio_emc_06::DSE_W
• sw_pad_ctl_pad_gpio_emc_06::HYS_W
• sw_pad_ctl_pad_gpio_emc_06::ODE_W
• sw_pad_ctl_pad_gpio_emc_06::PKE_W
• sw_pad_ctl_pad_gpio_emc_06::PUE_W
• sw_pad_ctl_pad_gpio_emc_06::PUS_W
• sw_pad_ctl_pad_gpio_emc_06::SPEED_W
• sw_pad_ctl_pad_gpio_emc_06::SRE_W
• sw_pad_ctl_pad_gpio_emc_07::DSE_W
• sw_pad_ctl_pad_gpio_emc_07::HYS_W
• sw_pad_ctl_pad_gpio_emc_07::ODE_W
• sw_pad_ctl_pad_gpio_emc_07::PKE_W
• sw_pad_ctl_pad_gpio_emc_07::PUE_W
• sw_pad_ctl_pad_gpio_emc_07::PUS_W
• sw_pad_ctl_pad_gpio_emc_07::SPEED_W
• sw_pad_ctl_pad_gpio_emc_07::SRE_W
• sw_pad_ctl_pad_gpio_emc_08::DSE_W
• sw_pad_ctl_pad_gpio_emc_08::HYS_W
• sw_pad_ctl_pad_gpio_emc_08::ODE_W
• sw_pad_ctl_pad_gpio_emc_08::PKE_W
• sw_pad_ctl_pad_gpio_emc_08::PUE_W
• sw_pad_ctl_pad_gpio_emc_08::PUS_W
• sw_pad_ctl_pad_gpio_emc_08::SPEED_W
• sw_pad_ctl_pad_gpio_emc_08::SRE_W
• sw_pad_ctl_pad_gpio_emc_09::DSE_W
• sw_pad_ctl_pad_gpio_emc_09::HYS_W
• sw_pad_ctl_pad_gpio_emc_09::ODE_W
• sw_pad_ctl_pad_gpio_emc_09::PKE_W
• sw_pad_ctl_pad_gpio_emc_09::PUE_W
• sw_pad_ctl_pad_gpio_emc_09::PUS_W
• sw_pad_ctl_pad_gpio_emc_09::SPEED_W
• sw_pad_ctl_pad_gpio_emc_09::SRE_W
• sw_pad_ctl_pad_gpio_emc_10::DSE_W
• sw_pad_ctl_pad_gpio_emc_10::HYS_W
• sw_pad_ctl_pad_gpio_emc_10::ODE_W
• sw_pad_ctl_pad_gpio_emc_10::PKE_W
• sw_pad_ctl_pad_gpio_emc_10::PUE_W
• sw_pad_ctl_pad_gpio_emc_10::PUS_W
• sw_pad_ctl_pad_gpio_emc_10::SPEED_W
• sw_pad_ctl_pad_gpio_emc_10::SRE_W
• sw_pad_ctl_pad_gpio_emc_11::DSE_W
• sw_pad_ctl_pad_gpio_emc_11::HYS_W
• sw_pad_ctl_pad_gpio_emc_11::ODE_W
• sw_pad_ctl_pad_gpio_emc_11::PKE_W
• sw_pad_ctl_pad_gpio_emc_11::PUE_W
• sw_pad_ctl_pad_gpio_emc_11::PUS_W
• sw_pad_ctl_pad_gpio_emc_11::SPEED_W
• sw_pad_ctl_pad_gpio_emc_11::SRE_W
• sw_pad_ctl_pad_gpio_emc_12::DSE_W
• sw_pad_ctl_pad_gpio_emc_12::HYS_W
• sw_pad_ctl_pad_gpio_emc_12::ODE_W
• sw_pad_ctl_pad_gpio_emc_12::PKE_W
• sw_pad_ctl_pad_gpio_emc_12::PUE_W
• sw_pad_ctl_pad_gpio_emc_12::PUS_W
• sw_pad_ctl_pad_gpio_emc_12::SPEED_W
• sw_pad_ctl_pad_gpio_emc_12::SRE_W
• sw_pad_ctl_pad_gpio_emc_13::DSE_W
• sw_pad_ctl_pad_gpio_emc_13::HYS_W
• sw_pad_ctl_pad_gpio_emc_13::ODE_W
• sw_pad_ctl_pad_gpio_emc_13::PKE_W
• sw_pad_ctl_pad_gpio_emc_13::PUE_W
• sw_pad_ctl_pad_gpio_emc_13::PUS_W
• sw_pad_ctl_pad_gpio_emc_13::SPEED_W
• sw_pad_ctl_pad_gpio_emc_13::SRE_W
• sw_pad_ctl_pad_gpio_emc_14::DSE_W
• sw_pad_ctl_pad_gpio_emc_14::HYS_W
• sw_pad_ctl_pad_gpio_emc_14::ODE_W
• sw_pad_ctl_pad_gpio_emc_14::PKE_W
• sw_pad_ctl_pad_gpio_emc_14::PUE_W
• sw_pad_ctl_pad_gpio_emc_14::PUS_W
• sw_pad_ctl_pad_gpio_emc_14::SPEED_W
• sw_pad_ctl_pad_gpio_emc_14::SRE_W
• sw_pad_ctl_pad_gpio_emc_15::DSE_W
• sw_pad_ctl_pad_gpio_emc_15::HYS_W
• sw_pad_ctl_pad_gpio_emc_15::ODE_W
• sw_pad_ctl_pad_gpio_emc_15::PKE_W
• sw_pad_ctl_pad_gpio_emc_15::PUE_W
• sw_pad_ctl_pad_gpio_emc_15::PUS_W
• sw_pad_ctl_pad_gpio_emc_15::SPEED_W
• sw_pad_ctl_pad_gpio_emc_15::SRE_W
• sw_pad_ctl_pad_gpio_emc_16::DSE_W
• sw_pad_ctl_pad_gpio_emc_16::HYS_W
• sw_pad_ctl_pad_gpio_emc_16::ODE_W
• sw_pad_ctl_pad_gpio_emc_16::PKE_W
• sw_pad_ctl_pad_gpio_emc_16::PUE_W
• sw_pad_ctl_pad_gpio_emc_16::PUS_W
• sw_pad_ctl_pad_gpio_emc_16::SPEED_W
• sw_pad_ctl_pad_gpio_emc_16::SRE_W
• sw_pad_ctl_pad_gpio_emc_17::DSE_W
• sw_pad_ctl_pad_gpio_emc_17::HYS_W
• sw_pad_ctl_pad_gpio_emc_17::ODE_W
• sw_pad_ctl_pad_gpio_emc_17::PKE_W
• sw_pad_ctl_pad_gpio_emc_17::PUE_W
• sw_pad_ctl_pad_gpio_emc_17::PUS_W
• sw_pad_ctl_pad_gpio_emc_17::SPEED_W
• sw_pad_ctl_pad_gpio_emc_17::SRE_W
• sw_pad_ctl_pad_gpio_emc_18::DSE_W
• sw_pad_ctl_pad_gpio_emc_18::HYS_W
• sw_pad_ctl_pad_gpio_emc_18::ODE_W
• sw_pad_ctl_pad_gpio_emc_18::PKE_W
• sw_pad_ctl_pad_gpio_emc_18::PUE_W
• sw_pad_ctl_pad_gpio_emc_18::PUS_W
• sw_pad_ctl_pad_gpio_emc_18::SPEED_W
• sw_pad_ctl_pad_gpio_emc_18::SRE_W
• sw_pad_ctl_pad_gpio_emc_19::DSE_W
• sw_pad_ctl_pad_gpio_emc_19::HYS_W
• sw_pad_ctl_pad_gpio_emc_19::ODE_W
• sw_pad_ctl_pad_gpio_emc_19::PKE_W
• sw_pad_ctl_pad_gpio_emc_19::PUE_W
• sw_pad_ctl_pad_gpio_emc_19::PUS_W
• sw_pad_ctl_pad_gpio_emc_19::SPEED_W
• sw_pad_ctl_pad_gpio_emc_19::SRE_W
• sw_pad_ctl_pad_gpio_emc_20::DSE_W
• sw_pad_ctl_pad_gpio_emc_20::HYS_W
• sw_pad_ctl_pad_gpio_emc_20::ODE_W
• sw_pad_ctl_pad_gpio_emc_20::PKE_W
• sw_pad_ctl_pad_gpio_emc_20::PUE_W
• sw_pad_ctl_pad_gpio_emc_20::PUS_W
• sw_pad_ctl_pad_gpio_emc_20::SPEED_W
• sw_pad_ctl_pad_gpio_emc_20::SRE_W
• sw_pad_ctl_pad_gpio_emc_21::DSE_W
• sw_pad_ctl_pad_gpio_emc_21::HYS_W
• sw_pad_ctl_pad_gpio_emc_21::ODE_W
• sw_pad_ctl_pad_gpio_emc_21::PKE_W
• sw_pad_ctl_pad_gpio_emc_21::PUE_W
• sw_pad_ctl_pad_gpio_emc_21::PUS_W
• sw_pad_ctl_pad_gpio_emc_21::SPEED_W
• sw_pad_ctl_pad_gpio_emc_21::SRE_W
• sw_pad_ctl_pad_gpio_emc_22::DSE_W
• sw_pad_ctl_pad_gpio_emc_22::HYS_W
• sw_pad_ctl_pad_gpio_emc_22::ODE_W
• sw_pad_ctl_pad_gpio_emc_22::PKE_W
• sw_pad_ctl_pad_gpio_emc_22::PUE_W
• sw_pad_ctl_pad_gpio_emc_22::PUS_W
• sw_pad_ctl_pad_gpio_emc_22::SPEED_W
• sw_pad_ctl_pad_gpio_emc_22::SRE_W
• sw_pad_ctl_pad_gpio_emc_23::DSE_W
• sw_pad_ctl_pad_gpio_emc_23::HYS_W
• sw_pad_ctl_pad_gpio_emc_23::ODE_W
• sw_pad_ctl_pad_gpio_emc_23::PKE_W
• sw_pad_ctl_pad_gpio_emc_23::PUE_W
• sw_pad_ctl_pad_gpio_emc_23::PUS_W
• sw_pad_ctl_pad_gpio_emc_23::SPEED_W
• sw_pad_ctl_pad_gpio_emc_23::SRE_W
• sw_pad_ctl_pad_gpio_emc_24::DSE_W
• sw_pad_ctl_pad_gpio_emc_24::HYS_W
• sw_pad_ctl_pad_gpio_emc_24::ODE_W
• sw_pad_ctl_pad_gpio_emc_24::PKE_W
• sw_pad_ctl_pad_gpio_emc_24::PUE_W
• sw_pad_ctl_pad_gpio_emc_24::PUS_W
• sw_pad_ctl_pad_gpio_emc_24::SPEED_W
• sw_pad_ctl_pad_gpio_emc_24::SRE_W
• sw_pad_ctl_pad_gpio_emc_25::DSE_W
• sw_pad_ctl_pad_gpio_emc_25::HYS_W
• sw_pad_ctl_pad_gpio_emc_25::ODE_W
• sw_pad_ctl_pad_gpio_emc_25::PKE_W
• sw_pad_ctl_pad_gpio_emc_25::PUE_W
• sw_pad_ctl_pad_gpio_emc_25::PUS_W
• sw_pad_ctl_pad_gpio_emc_25::SPEED_W
• sw_pad_ctl_pad_gpio_emc_25::SRE_W
• sw_pad_ctl_pad_gpio_emc_26::DSE_W
• sw_pad_ctl_pad_gpio_emc_26::HYS_W
• sw_pad_ctl_pad_gpio_emc_26::ODE_W
• sw_pad_ctl_pad_gpio_emc_26::PKE_W
• sw_pad_ctl_pad_gpio_emc_26::PUE_W
• sw_pad_ctl_pad_gpio_emc_26::PUS_W
• sw_pad_ctl_pad_gpio_emc_26::SPEED_W
• sw_pad_ctl_pad_gpio_emc_26::SRE_W
• sw_pad_ctl_pad_gpio_emc_27::DSE_W
• sw_pad_ctl_pad_gpio_emc_27::HYS_W
• sw_pad_ctl_pad_gpio_emc_27::ODE_W
• sw_pad_ctl_pad_gpio_emc_27::PKE_W
• sw_pad_ctl_pad_gpio_emc_27::PUE_W
• sw_pad_ctl_pad_gpio_emc_27::PUS_W
• sw_pad_ctl_pad_gpio_emc_27::SPEED_W
• sw_pad_ctl_pad_gpio_emc_27::SRE_W
• sw_pad_ctl_pad_gpio_emc_28::DSE_W
• sw_pad_ctl_pad_gpio_emc_28::HYS_W
• sw_pad_ctl_pad_gpio_emc_28::ODE_W
• sw_pad_ctl_pad_gpio_emc_28::PKE_W
• sw_pad_ctl_pad_gpio_emc_28::PUE_W
• sw_pad_ctl_pad_gpio_emc_28::PUS_W
• sw_pad_ctl_pad_gpio_emc_28::SPEED_W
• sw_pad_ctl_pad_gpio_emc_28::SRE_W
• sw_pad_ctl_pad_gpio_emc_29::DSE_W
• sw_pad_ctl_pad_gpio_emc_29::HYS_W
• sw_pad_ctl_pad_gpio_emc_29::ODE_W
• sw_pad_ctl_pad_gpio_emc_29::PKE_W
• sw_pad_ctl_pad_gpio_emc_29::PUE_W
• sw_pad_ctl_pad_gpio_emc_29::PUS_W
• sw_pad_ctl_pad_gpio_emc_29::SPEED_W
• sw_pad_ctl_pad_gpio_emc_29::SRE_W
• sw_pad_ctl_pad_gpio_emc_30::DSE_W
• sw_pad_ctl_pad_gpio_emc_30::HYS_W
• sw_pad_ctl_pad_gpio_emc_30::ODE_W
• sw_pad_ctl_pad_gpio_emc_30::PKE_W
• sw_pad_ctl_pad_gpio_emc_30::PUE_W
• sw_pad_ctl_pad_gpio_emc_30::PUS_W
• sw_pad_ctl_pad_gpio_emc_30::SPEED_W
• sw_pad_ctl_pad_gpio_emc_30::SRE_W
• sw_pad_ctl_pad_gpio_emc_31::DSE_W
• sw_pad_ctl_pad_gpio_emc_31::HYS_W
• sw_pad_ctl_pad_gpio_emc_31::ODE_W
• sw_pad_ctl_pad_gpio_emc_31::PKE_W
• sw_pad_ctl_pad_gpio_emc_31::PUE_W
• sw_pad_ctl_pad_gpio_emc_31::PUS_W
• sw_pad_ctl_pad_gpio_emc_31::SPEED_W
• sw_pad_ctl_pad_gpio_emc_31::SRE_W
• sw_pad_ctl_pad_gpio_emc_32::DSE_W
• sw_pad_ctl_pad_gpio_emc_32::HYS_W
• sw_pad_ctl_pad_gpio_emc_32::ODE_W
• sw_pad_ctl_pad_gpio_emc_32::PKE_W
• sw_pad_ctl_pad_gpio_emc_32::PUE_W
• sw_pad_ctl_pad_gpio_emc_32::PUS_W
• sw_pad_ctl_pad_gpio_emc_32::SPEED_W
• sw_pad_ctl_pad_gpio_emc_32::SRE_W
• sw_pad_ctl_pad_gpio_emc_33::DSE_W
• sw_pad_ctl_pad_gpio_emc_33::HYS_W
• sw_pad_ctl_pad_gpio_emc_33::ODE_W
• sw_pad_ctl_pad_gpio_emc_33::PKE_W
• sw_pad_ctl_pad_gpio_emc_33::PUE_W
• sw_pad_ctl_pad_gpio_emc_33::PUS_W
• sw_pad_ctl_pad_gpio_emc_33::SPEED_W
• sw_pad_ctl_pad_gpio_emc_33::SRE_W
• sw_pad_ctl_pad_gpio_emc_34::DSE_W
• sw_pad_ctl_pad_gpio_emc_34::HYS_W
• sw_pad_ctl_pad_gpio_emc_34::ODE_W
• sw_pad_ctl_pad_gpio_emc_34::PKE_W
• sw_pad_ctl_pad_gpio_emc_34::PUE_W
• sw_pad_ctl_pad_gpio_emc_34::PUS_W
• sw_pad_ctl_pad_gpio_emc_34::SPEED_W
• sw_pad_ctl_pad_gpio_emc_34::SRE_W
• sw_pad_ctl_pad_gpio_emc_35::DSE_W
• sw_pad_ctl_pad_gpio_emc_35::HYS_W
• sw_pad_ctl_pad_gpio_emc_35::ODE_W
• sw_pad_ctl_pad_gpio_emc_35::PKE_W
• sw_pad_ctl_pad_gpio_emc_35::PUE_W
• sw_pad_ctl_pad_gpio_emc_35::PUS_W
• sw_pad_ctl_pad_gpio_emc_35::SPEED_W
• sw_pad_ctl_pad_gpio_emc_35::SRE_W
• sw_pad_ctl_pad_gpio_emc_36::DSE_W
• sw_pad_ctl_pad_gpio_emc_36::HYS_W
• sw_pad_ctl_pad_gpio_emc_36::ODE_W
• sw_pad_ctl_pad_gpio_emc_36::PKE_W
• sw_pad_ctl_pad_gpio_emc_36::PUE_W
• sw_pad_ctl_pad_gpio_emc_36::PUS_W
• sw_pad_ctl_pad_gpio_emc_36::SPEED_W
• sw_pad_ctl_pad_gpio_emc_36::SRE_W
• sw_pad_ctl_pad_gpio_emc_37::DSE_W
• sw_pad_ctl_pad_gpio_emc_37::HYS_W
• sw_pad_ctl_pad_gpio_emc_37::ODE_W
• sw_pad_ctl_pad_gpio_emc_37::PKE_W
• sw_pad_ctl_pad_gpio_emc_37::PUE_W
• sw_pad_ctl_pad_gpio_emc_37::PUS_W
• sw_pad_ctl_pad_gpio_emc_37::SPEED_W
• sw_pad_ctl_pad_gpio_emc_37::SRE_W
• sw_pad_ctl_pad_gpio_emc_38::DSE_W
• sw_pad_ctl_pad_gpio_emc_38::HYS_W
• sw_pad_ctl_pad_gpio_emc_38::ODE_W
• sw_pad_ctl_pad_gpio_emc_38::PKE_W
• sw_pad_ctl_pad_gpio_emc_38::PUE_W
• sw_pad_ctl_pad_gpio_emc_38::PUS_W
• sw_pad_ctl_pad_gpio_emc_38::SPEED_W
• sw_pad_ctl_pad_gpio_emc_38::SRE_W
• sw_pad_ctl_pad_gpio_emc_39::DSE_W
• sw_pad_ctl_pad_gpio_emc_39::HYS_W
• sw_pad_ctl_pad_gpio_emc_39::ODE_W
• sw_pad_ctl_pad_gpio_emc_39::PKE_W
• sw_pad_ctl_pad_gpio_emc_39::PUE_W
• sw_pad_ctl_pad_gpio_emc_39::PUS_W
• sw_pad_ctl_pad_gpio_emc_39::SPEED_W
• sw_pad_ctl_pad_gpio_emc_39::SRE_W
• sw_pad_ctl_pad_gpio_emc_40::DSE_W
• sw_pad_ctl_pad_gpio_emc_40::HYS_W
• sw_pad_ctl_pad_gpio_emc_40::ODE_W
• sw_pad_ctl_pad_gpio_emc_40::PKE_W
• sw_pad_ctl_pad_gpio_emc_40::PUE_W
• sw_pad_ctl_pad_gpio_emc_40::PUS_W
• sw_pad_ctl_pad_gpio_emc_40::SPEED_W
• sw_pad_ctl_pad_gpio_emc_40::SRE_W
• sw_pad_ctl_pad_gpio_emc_41::DSE_W
• sw_pad_ctl_pad_gpio_emc_41::HYS_W
• sw_pad_ctl_pad_gpio_emc_41::ODE_W
• sw_pad_ctl_pad_gpio_emc_41::PKE_W
• sw_pad_ctl_pad_gpio_emc_41::PUE_W
• sw_pad_ctl_pad_gpio_emc_41::PUS_W
• sw_pad_ctl_pad_gpio_emc_41::SPEED_W
• sw_pad_ctl_pad_gpio_emc_41::SRE_W
• sw_pad_ctl_pad_gpio_sd_b0_00::DSE_W
• sw_pad_ctl_pad_gpio_sd_b0_00::HYS_W
• sw_pad_ctl_pad_gpio_sd_b0_00::ODE_W
• sw_pad_ctl_pad_gpio_sd_b0_00::PKE_W
• sw_pad_ctl_pad_gpio_sd_b0_00::PUE_W
• sw_pad_ctl_pad_gpio_sd_b0_00::PUS_W
• sw_pad_ctl_pad_gpio_sd_b0_00::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b0_00::SRE_W
• sw_pad_ctl_pad_gpio_sd_b0_01::DSE_W
• sw_pad_ctl_pad_gpio_sd_b0_01::HYS_W
• sw_pad_ctl_pad_gpio_sd_b0_01::ODE_W
• sw_pad_ctl_pad_gpio_sd_b0_01::PKE_W
• sw_pad_ctl_pad_gpio_sd_b0_01::PUE_W
• sw_pad_ctl_pad_gpio_sd_b0_01::PUS_W
• sw_pad_ctl_pad_gpio_sd_b0_01::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b0_01::SRE_W
• sw_pad_ctl_pad_gpio_sd_b0_02::DSE_W
• sw_pad_ctl_pad_gpio_sd_b0_02::HYS_W
• sw_pad_ctl_pad_gpio_sd_b0_02::ODE_W
• sw_pad_ctl_pad_gpio_sd_b0_02::PKE_W
• sw_pad_ctl_pad_gpio_sd_b0_02::PUE_W
• sw_pad_ctl_pad_gpio_sd_b0_02::PUS_W
• sw_pad_ctl_pad_gpio_sd_b0_02::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b0_02::SRE_W
• sw_pad_ctl_pad_gpio_sd_b0_03::DSE_W
• sw_pad_ctl_pad_gpio_sd_b0_03::HYS_W
• sw_pad_ctl_pad_gpio_sd_b0_03::ODE_W
• sw_pad_ctl_pad_gpio_sd_b0_03::PKE_W
• sw_pad_ctl_pad_gpio_sd_b0_03::PUE_W
• sw_pad_ctl_pad_gpio_sd_b0_03::PUS_W
• sw_pad_ctl_pad_gpio_sd_b0_03::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b0_03::SRE_W
• sw_pad_ctl_pad_gpio_sd_b0_04::DSE_W
• sw_pad_ctl_pad_gpio_sd_b0_04::HYS_W
• sw_pad_ctl_pad_gpio_sd_b0_04::ODE_W
• sw_pad_ctl_pad_gpio_sd_b0_04::PKE_W
• sw_pad_ctl_pad_gpio_sd_b0_04::PUE_W
• sw_pad_ctl_pad_gpio_sd_b0_04::PUS_W
• sw_pad_ctl_pad_gpio_sd_b0_04::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b0_04::SRE_W
• sw_pad_ctl_pad_gpio_sd_b0_05::DSE_W
• sw_pad_ctl_pad_gpio_sd_b0_05::HYS_W
• sw_pad_ctl_pad_gpio_sd_b0_05::ODE_W
• sw_pad_ctl_pad_gpio_sd_b0_05::PKE_W
• sw_pad_ctl_pad_gpio_sd_b0_05::PUE_W
• sw_pad_ctl_pad_gpio_sd_b0_05::PUS_W
• sw_pad_ctl_pad_gpio_sd_b0_05::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b0_05::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_00::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_00::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_00::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_00::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_00::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_00::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_00::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_00::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_01::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_01::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_01::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_01::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_01::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_01::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_01::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_01::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_02::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_02::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_02::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_02::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_02::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_02::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_02::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_02::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_03::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_03::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_03::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_03::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_03::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_03::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_03::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_03::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_04::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_04::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_04::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_04::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_04::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_04::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_04::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_04::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_05::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_05::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_05::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_05::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_05::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_05::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_05::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_05::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_06::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_06::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_06::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_06::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_06::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_06::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_06::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_06::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_07::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_07::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_07::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_07::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_07::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_07::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_07::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_07::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_08::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_08::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_08::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_08::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_08::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_08::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_08::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_08::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_09::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_09::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_09::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_09::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_09::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_09::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_09::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_09::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_10::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_10::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_10::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_10::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_10::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_10::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_10::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_10::SRE_W
• sw_pad_ctl_pad_gpio_sd_b1_11::DSE_W
• sw_pad_ctl_pad_gpio_sd_b1_11::HYS_W
• sw_pad_ctl_pad_gpio_sd_b1_11::ODE_W
• sw_pad_ctl_pad_gpio_sd_b1_11::PKE_W
• sw_pad_ctl_pad_gpio_sd_b1_11::PUE_W
• sw_pad_ctl_pad_gpio_sd_b1_11::PUS_W
• sw_pad_ctl_pad_gpio_sd_b1_11::SPEED_W
• sw_pad_ctl_pad_gpio_sd_b1_11::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_00::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_00::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_00::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_00::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_00::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_00::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_00::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_00::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_01::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_01::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_01::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_01::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_01::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_01::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_01::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_01::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_02::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_02::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_02::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_02::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_02::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_02::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_02::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_02::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_03::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_03::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_03::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_03::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_03::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_03::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_03::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_03::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_04::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_04::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_04::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_04::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_04::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_04::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_04::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_04::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_05::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_05::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_05::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_05::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_05::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_05::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_05::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_05::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_06::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_06::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_06::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_06::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_06::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_06::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_06::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_06::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_07::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_07::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_07::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_07::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_07::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_07::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_07::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_07::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_08::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_08::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_08::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_08::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_08::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_08::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_08::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_08::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_09::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_09::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_09::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_09::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_09::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_09::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_09::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_09::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_10::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_10::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_10::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_10::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_10::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_10::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_10::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_10::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_11::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_11::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_11::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_11::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_11::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_11::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_11::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_11::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_12::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_12::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_12::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_12::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_12::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_12::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_12::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_12::SRE_W
• sw_pad_ctl_pad_gpio_spi_b0_13::DSE_W
• sw_pad_ctl_pad_gpio_spi_b0_13::HYS_W
• sw_pad_ctl_pad_gpio_spi_b0_13::ODE_W
• sw_pad_ctl_pad_gpio_spi_b0_13::PKE_W
• sw_pad_ctl_pad_gpio_spi_b0_13::PUE_W
• sw_pad_ctl_pad_gpio_spi_b0_13::PUS_W
• sw_pad_ctl_pad_gpio_spi_b0_13::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b0_13::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_00::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_00::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_00::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_00::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_00::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_00::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_00::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_00::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_01::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_01::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_01::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_01::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_01::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_01::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_01::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_01::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_02::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_02::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_02::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_02::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_02::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_02::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_02::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_02::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_03::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_03::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_03::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_03::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_03::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_03::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_03::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_03::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_04::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_04::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_04::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_04::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_04::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_04::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_04::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_04::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_05::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_05::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_05::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_05::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_05::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_05::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_05::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_05::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_06::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_06::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_06::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_06::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_06::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_06::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_06::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_06::SRE_W
• sw_pad_ctl_pad_gpio_spi_b1_07::DSE_W
• sw_pad_ctl_pad_gpio_spi_b1_07::HYS_W
• sw_pad_ctl_pad_gpio_spi_b1_07::ODE_W
• sw_pad_ctl_pad_gpio_spi_b1_07::PKE_W
• sw_pad_ctl_pad_gpio_spi_b1_07::PUE_W
• sw_pad_ctl_pad_gpio_spi_b1_07::PUS_W
• sw_pad_ctl_pad_gpio_spi_b1_07::SPEED_W
• sw_pad_ctl_pad_gpio_spi_b1_07::SRE_W
• usb_otg1_oc_select_input::DAISY_W
• usb_otg2_oc_select_input::DAISY_W
• usdhc1_cd_b_select_input::DAISY_W
• usdhc1_wp_select_input::DAISY_W
• usdhc2_cd_b_select_input::DAISY_W
• usdhc2_clk_select_input::DAISY_W
• usdhc2_cmd_select_input::DAISY_W
• usdhc2_data0_select_input::DAISY_W
• usdhc2_data1_select_input::DAISY_W
• usdhc2_data2_select_input::DAISY_W
• usdhc2_data3_select_input::DAISY_W
• usdhc2_data4_select_input::DAISY_W
• usdhc2_data5_select_input::DAISY_W
• usdhc2_data6_select_input::DAISY_W
• usdhc2_data7_select_input::DAISY_W
• usdhc2_wp_select_input::DAISY_W
• xbar1_in02_select_input::DAISY_W
• xbar1_in03_select_input::DAISY_W
• xbar1_in04_select_input::DAISY_W
• xbar1_in05_select_input::DAISY_W
• xbar1_in06_select_input::DAISY_W
• xbar1_in07_select_input::DAISY_W
• xbar1_in08_select_input::DAISY_W
• xbar1_in09_select_input::DAISY_W
• xbar1_in14_select_input::DAISY_W
• xbar1_in15_select_input::DAISY_W
• xbar1_in16_select_input::DAISY_W
• xbar1_in17_select_input::DAISY_W
• xbar1_in18_select_input::DAISY_W
• xbar1_in19_select_input::DAISY_W
• xbar1_in20_select_input::DAISY_W
• xbar1_in21_select_input::DAISY_W
• xbar1_in22_select_input::DAISY_W
• xbar1_in23_select_input::DAISY_W
• xbar1_in24_select_input::DAISY_W
• xbar1_in25_select_input::DAISY_W

Enums

• Variant
• anatop_usb_otg1_id_select_input::DAISY_A
• anatop_usb_otg2_id_select_input::DAISY_A
• canfd_ipp_ind_canrx_select_input::DAISY_A
• ccm_pmic_ready_select_input::DAISY_A
• csi_data02_select_input::DAISY_A
• csi_data03_select_input::DAISY_A
• csi_data04_select_input::DAISY_A
• csi_data05_select_input::DAISY_A
• csi_data06_select_input::DAISY_A
• csi_data07_select_input::DAISY_A
• csi_data08_select_input::DAISY_A
• csi_data09_select_input::DAISY_A
• csi_hsync_select_input::DAISY_A
• csi_pixclk_select_input::DAISY_A
• csi_vsync_select_input::DAISY_A
• enet0_rxdata_select_input::DAISY_A
• enet0_timer_select_input::DAISY_A
• enet1_rxdata_select_input::DAISY_A
• enet2_ipg_clk_rmii_select_input::DAISY_A
• enet2_ipp_ind_mac0_mdio_select_input::DAISY_A
• enet2_ipp_ind_mac0_rxdata_select_input_0::DAISY_A
• enet2_ipp_ind_mac0_rxdata_select_input_1::DAISY_A
• enet2_ipp_ind_mac0_rxen_select_input::DAISY_A
• enet2_ipp_ind_mac0_rxerr_select_input::DAISY_A
• enet2_ipp_ind_mac0_timer_select_input_0::DAISY_A
• enet2_ipp_ind_mac0_txclk_select_input::DAISY_A
• enet_ipg_clk_rmii_select_input::DAISY_A
• enet_mdio_select_input::DAISY_A
• enet_rxen_select_input::DAISY_A
• enet_rxerr_select_input::DAISY_A
• enet_txclk_select_input::DAISY_A
• flexcan1_rx_select_input::DAISY_A
• flexcan2_rx_select_input::DAISY_A
• flexpwm1_pwma0_select_input::DAISY_A
• flexpwm1_pwma1_select_input::DAISY_A
• flexpwm1_pwma2_select_input::DAISY_A
• flexpwm1_pwma3_select_input::DAISY_A
• flexpwm1_pwmb0_select_input::DAISY_A
• flexpwm1_pwmb1_select_input::DAISY_A
• flexpwm1_pwmb2_select_input::DAISY_A
• flexpwm1_pwmb3_select_input::DAISY_A
• flexpwm2_pwma0_select_input::DAISY_A
• flexpwm2_pwma1_select_input::DAISY_A
• flexpwm2_pwma2_select_input::DAISY_A
• flexpwm2_pwma3_select_input::DAISY_A
• flexpwm2_pwmb0_select_input::DAISY_A
• flexpwm2_pwmb1_select_input::DAISY_A
• flexpwm2_pwmb2_select_input::DAISY_A
• flexpwm2_pwmb3_select_input::DAISY_A
• flexpwm4_pwma0_select_input::DAISY_A
• flexpwm4_pwma1_select_input::DAISY_A
• flexpwm4_pwma2_select_input::DAISY_A
• flexpwm4_pwma3_select_input::DAISY_A
• flexspi2_ipp_ind_dqs_fa_select_input::DAISY_A
• flexspi2_ipp_ind_io_fa_bit0_select_input::DAISY_A
• flexspi2_ipp_ind_io_fa_bit1_select_input::DAISY_A
• flexspi2_ipp_ind_io_fa_bit2_select_input::DAISY_A
• flexspi2_ipp_ind_io_fa_bit3_select_input::DAISY_A
• flexspi2_ipp_ind_io_fb_bit0_select_input::DAISY_A
• flexspi2_ipp_ind_io_fb_bit1_select_input::DAISY_A
• flexspi2_ipp_ind_io_fb_bit2_select_input::DAISY_A
• flexspi2_ipp_ind_io_fb_bit3_select_input::DAISY_A
• flexspi2_ipp_ind_sck_fa_select_input::DAISY_A
• flexspi2_ipp_ind_sck_fb_select_input::DAISY_A
• flexspia_data0_select_input::DAISY_A
• flexspia_data1_select_input::DAISY_A
• flexspia_data2_select_input::DAISY_A
• flexspia_data3_select_input::DAISY_A
• flexspia_dqs_select_input::DAISY_A
• flexspia_sck_select_input::DAISY_A
• flexspib_data0_select_input::DAISY_A
• flexspib_data1_select_input::DAISY_A
• flexspib_data2_select_input::DAISY_A
• flexspib_data3_select_input::DAISY_A
• gpt1_ipp_ind_capin1_select_input::DAISY_A
• gpt1_ipp_ind_capin2_select_input::DAISY_A
• gpt1_ipp_ind_clkin_select_input::DAISY_A
• gpt2_ipp_ind_capin1_select_input::DAISY_A
• gpt2_ipp_ind_capin2_select_input::DAISY_A
• gpt2_ipp_ind_clkin_select_input::DAISY_A
• lpi2c1_scl_select_input::DAISY_A
• lpi2c1_sda_select_input::DAISY_A
• lpi2c2_scl_select_input::DAISY_A
• lpi2c2_sda_select_input::DAISY_A
• lpi2c3_scl_select_input::DAISY_A
• lpi2c3_sda_select_input::DAISY_A
• lpi2c4_scl_select_input::DAISY_A
• lpi2c4_sda_select_input::DAISY_A
• lpspi1_pcs0_select_input::DAISY_A
• lpspi1_sck_select_input::DAISY_A
• lpspi1_sdi_select_input::DAISY_A
• lpspi1_sdo_select_input::DAISY_A
• lpspi2_pcs0_select_input::DAISY_A
• lpspi2_sck_select_input::DAISY_A
• lpspi2_sdi_select_input::DAISY_A
• lpspi2_sdo_select_input::DAISY_A
• lpspi3_pcs0_select_input::DAISY_A
• lpspi3_sck_select_input::DAISY_A
• lpspi3_sdi_select_input::DAISY_A
• lpspi3_sdo_select_input::DAISY_A
• lpspi4_pcs0_select_input::DAISY_A
• lpspi4_sck_select_input::DAISY_A
• lpspi4_sdi_select_input::DAISY_A
• lpspi4_sdo_select_input::DAISY_A
• lpuart2_rx_select_input::DAISY_A
• lpuart2_tx_select_input::DAISY_A
• lpuart3_cts_b_select_input::DAISY_A
• lpuart3_rx_select_input::DAISY_A
• lpuart3_tx_select_input::DAISY_A
• lpuart4_rx_select_input::DAISY_A
• lpuart4_tx_select_input::DAISY_A
• lpuart5_rx_select_input::DAISY_A
• lpuart5_tx_select_input::DAISY_A
• lpuart6_rx_select_input::DAISY_A
• lpuart6_tx_select_input::DAISY_A
• lpuart7_rx_select_input::DAISY_A
• lpuart7_tx_select_input::DAISY_A
• lpuart8_rx_select_input::DAISY_A
• lpuart8_tx_select_input::DAISY_A
• nmi_select_input::DAISY_A
• qtimer2_timer0_select_input::DAISY_A
• qtimer2_timer1_select_input::DAISY_A
• qtimer2_timer2_select_input::DAISY_A
• qtimer2_timer3_select_input::DAISY_A
• qtimer3_timer0_select_input::DAISY_A
• qtimer3_timer1_select_input::DAISY_A
• qtimer3_timer2_select_input::DAISY_A
• qtimer3_timer3_select_input::DAISY_A
• sai1_mclk2_select_input::DAISY_A
• sai1_rx_bclk_select_input::DAISY_A
• sai1_rx_data0_select_input::DAISY_A
• sai1_rx_data1_select_input::DAISY_A
• sai1_rx_data2_select_input::DAISY_A
• sai1_rx_data3_select_input::DAISY_A
• sai1_rx_sync_select_input::DAISY_A
• sai1_tx_bclk_select_input::DAISY_A
• sai1_tx_sync_select_input::DAISY_A
• sai2_mclk2_select_input::DAISY_A
• sai2_rx_bclk_select_input::DAISY_A
• sai2_rx_data0_select_input::DAISY_A
• sai2_rx_sync_select_input::DAISY_A
• sai2_tx_bclk_select_input::DAISY_A
• sai2_tx_sync_select_input::DAISY_A
• sai3_ipg_clk_sai_mclk_select_input_2::DAISY_A
• sai3_ipp_ind_sai_rxbclk_select_input::DAISY_A
• sai3_ipp_ind_sai_rxdata_select_input_0::DAISY_A
• sai3_ipp_ind_sai_rxsync_select_input::DAISY_A
• sai3_ipp_ind_sai_txbclk_select_input::DAISY_A
• sai3_ipp_ind_sai_txsync_select_input::DAISY_A
• semc_i_ipp_ind_dqs4_select_input::DAISY_A
• spdif_in_select_input::DAISY_A
• sw_mux_ctl_pad_gpio_ad_b0_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_00::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_01::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_02::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_03::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_04::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_05::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_06::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_07::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_08::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_09::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_10::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_11::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_12::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_12::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_13::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_13::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_14::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_14::SION_A
• sw_mux_ctl_pad_gpio_ad_b0_15::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b0_15::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_00::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_01::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_02::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_03::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_04::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_05::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_06::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_07::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_08::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_09::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_10::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_11::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_12::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_12::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_13::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_13::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_14::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_14::SION_A
• sw_mux_ctl_pad_gpio_ad_b1_15::MUX_MODE_A
• sw_mux_ctl_pad_gpio_ad_b1_15::SION_A
• sw_mux_ctl_pad_gpio_b0_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_00::SION_A
• sw_mux_ctl_pad_gpio_b0_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_01::SION_A
• sw_mux_ctl_pad_gpio_b0_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_02::SION_A
• sw_mux_ctl_pad_gpio_b0_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_03::SION_A
• sw_mux_ctl_pad_gpio_b0_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_04::SION_A
• sw_mux_ctl_pad_gpio_b0_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_05::SION_A
• sw_mux_ctl_pad_gpio_b0_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_06::SION_A
• sw_mux_ctl_pad_gpio_b0_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_07::SION_A
• sw_mux_ctl_pad_gpio_b0_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_08::SION_A
• sw_mux_ctl_pad_gpio_b0_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_09::SION_A
• sw_mux_ctl_pad_gpio_b0_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_10::SION_A
• sw_mux_ctl_pad_gpio_b0_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_11::SION_A
• sw_mux_ctl_pad_gpio_b0_12::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_12::SION_A
• sw_mux_ctl_pad_gpio_b0_13::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_13::SION_A
• sw_mux_ctl_pad_gpio_b0_14::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_14::SION_A
• sw_mux_ctl_pad_gpio_b0_15::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b0_15::SION_A
• sw_mux_ctl_pad_gpio_b1_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_00::SION_A
• sw_mux_ctl_pad_gpio_b1_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_01::SION_A
• sw_mux_ctl_pad_gpio_b1_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_02::SION_A
• sw_mux_ctl_pad_gpio_b1_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_03::SION_A
• sw_mux_ctl_pad_gpio_b1_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_04::SION_A
• sw_mux_ctl_pad_gpio_b1_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_05::SION_A
• sw_mux_ctl_pad_gpio_b1_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_06::SION_A
• sw_mux_ctl_pad_gpio_b1_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_07::SION_A
• sw_mux_ctl_pad_gpio_b1_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_08::SION_A
• sw_mux_ctl_pad_gpio_b1_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_09::SION_A
• sw_mux_ctl_pad_gpio_b1_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_10::SION_A
• sw_mux_ctl_pad_gpio_b1_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_11::SION_A
• sw_mux_ctl_pad_gpio_b1_12::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_12::SION_A
• sw_mux_ctl_pad_gpio_b1_13::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_13::SION_A
• sw_mux_ctl_pad_gpio_b1_14::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_14::SION_A
• sw_mux_ctl_pad_gpio_b1_15::MUX_MODE_A
• sw_mux_ctl_pad_gpio_b1_15::SION_A
• sw_mux_ctl_pad_gpio_emc_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_00::SION_A
• sw_mux_ctl_pad_gpio_emc_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_01::SION_A
• sw_mux_ctl_pad_gpio_emc_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_02::SION_A
• sw_mux_ctl_pad_gpio_emc_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_03::SION_A
• sw_mux_ctl_pad_gpio_emc_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_04::SION_A
• sw_mux_ctl_pad_gpio_emc_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_05::SION_A
• sw_mux_ctl_pad_gpio_emc_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_06::SION_A
• sw_mux_ctl_pad_gpio_emc_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_07::SION_A
• sw_mux_ctl_pad_gpio_emc_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_08::SION_A
• sw_mux_ctl_pad_gpio_emc_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_09::SION_A
• sw_mux_ctl_pad_gpio_emc_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_10::SION_A
• sw_mux_ctl_pad_gpio_emc_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_11::SION_A
• sw_mux_ctl_pad_gpio_emc_12::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_12::SION_A
• sw_mux_ctl_pad_gpio_emc_13::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_13::SION_A
• sw_mux_ctl_pad_gpio_emc_14::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_14::SION_A
• sw_mux_ctl_pad_gpio_emc_15::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_15::SION_A
• sw_mux_ctl_pad_gpio_emc_16::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_16::SION_A
• sw_mux_ctl_pad_gpio_emc_17::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_17::SION_A
• sw_mux_ctl_pad_gpio_emc_18::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_18::SION_A
• sw_mux_ctl_pad_gpio_emc_19::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_19::SION_A
• sw_mux_ctl_pad_gpio_emc_20::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_20::SION_A
• sw_mux_ctl_pad_gpio_emc_21::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_21::SION_A
• sw_mux_ctl_pad_gpio_emc_22::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_22::SION_A
• sw_mux_ctl_pad_gpio_emc_23::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_23::SION_A
• sw_mux_ctl_pad_gpio_emc_24::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_24::SION_A
• sw_mux_ctl_pad_gpio_emc_25::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_25::SION_A
• sw_mux_ctl_pad_gpio_emc_26::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_26::SION_A
• sw_mux_ctl_pad_gpio_emc_27::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_27::SION_A
• sw_mux_ctl_pad_gpio_emc_28::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_28::SION_A
• sw_mux_ctl_pad_gpio_emc_29::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_29::SION_A
• sw_mux_ctl_pad_gpio_emc_30::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_30::SION_A
• sw_mux_ctl_pad_gpio_emc_31::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_31::SION_A
• sw_mux_ctl_pad_gpio_emc_32::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_32::SION_A
• sw_mux_ctl_pad_gpio_emc_33::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_33::SION_A
• sw_mux_ctl_pad_gpio_emc_34::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_34::SION_A
• sw_mux_ctl_pad_gpio_emc_35::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_35::SION_A
• sw_mux_ctl_pad_gpio_emc_36::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_36::SION_A
• sw_mux_ctl_pad_gpio_emc_37::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_37::SION_A
• sw_mux_ctl_pad_gpio_emc_38::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_38::SION_A
• sw_mux_ctl_pad_gpio_emc_39::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_39::SION_A
• sw_mux_ctl_pad_gpio_emc_40::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_40::SION_A
• sw_mux_ctl_pad_gpio_emc_41::MUX_MODE_A
• sw_mux_ctl_pad_gpio_emc_41::SION_A
• sw_mux_ctl_pad_gpio_sd_b0_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b0_00::SION_A
• sw_mux_ctl_pad_gpio_sd_b0_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b0_01::SION_A
• sw_mux_ctl_pad_gpio_sd_b0_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b0_02::SION_A
• sw_mux_ctl_pad_gpio_sd_b0_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b0_03::SION_A
• sw_mux_ctl_pad_gpio_sd_b0_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b0_04::SION_A
• sw_mux_ctl_pad_gpio_sd_b0_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b0_05::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_00::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_01::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_02::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_03::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_04::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_05::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_06::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_07::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_08::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_09::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_10::SION_A
• sw_mux_ctl_pad_gpio_sd_b1_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_sd_b1_11::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_00::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_01::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_02::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_03::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_04::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_05::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_06::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_07::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_07::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_08::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_08::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_09::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_09::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_10::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_10::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_11::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_11::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_12::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b0_12::SION_A
• sw_mux_ctl_pad_gpio_spi_b0_13::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_00::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_00::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_01::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_01::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_02::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_02::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_03::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_03::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_04::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_04::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_05::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_05::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_06::MUX_MODE_A
• sw_mux_ctl_pad_gpio_spi_b1_06::SION_A
• sw_mux_ctl_pad_gpio_spi_b1_07::SION_A
• sw_pad_ctl_pad_gpio_ad_b0_00::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_00::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_00::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_00::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_00::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_00::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_00::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_00::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_01::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_01::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_01::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_01::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_01::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_01::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_01::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_01::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_02::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_02::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_02::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_02::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_02::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_02::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_02::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_02::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_03::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_03::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_03::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_03::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_03::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_03::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_03::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_03::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_04::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_04::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_04::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_04::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_04::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_04::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_04::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_04::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_05::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_05::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_05::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_05::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_05::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_05::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_05::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_05::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_06::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_06::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_06::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_06::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_06::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_06::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_06::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_06::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_07::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_07::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_07::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_07::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_07::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_07::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_07::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_07::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_08::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_08::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_08::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_08::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_08::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_08::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_08::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_08::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_09::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_09::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_09::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_09::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_09::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_09::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_09::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_09::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_10::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_10::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_10::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_10::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_10::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_10::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_10::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_10::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_11::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_11::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_11::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_11::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_11::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_11::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_11::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_11::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_12::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_12::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_12::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_12::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_12::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_12::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_12::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_12::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_13::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_13::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_13::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_13::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_13::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_13::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_13::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_13::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_14::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_14::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_14::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_14::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_14::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_14::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_14::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_14::SRE_A
• sw_pad_ctl_pad_gpio_ad_b0_15::DSE_A
• sw_pad_ctl_pad_gpio_ad_b0_15::HYS_A
• sw_pad_ctl_pad_gpio_ad_b0_15::ODE_A
• sw_pad_ctl_pad_gpio_ad_b0_15::PKE_A
• sw_pad_ctl_pad_gpio_ad_b0_15::PUE_A
• sw_pad_ctl_pad_gpio_ad_b0_15::PUS_A
• sw_pad_ctl_pad_gpio_ad_b0_15::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b0_15::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_00::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_00::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_00::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_00::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_00::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_00::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_00::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_00::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_01::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_01::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_01::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_01::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_01::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_01::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_01::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_01::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_02::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_02::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_02::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_02::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_02::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_02::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_02::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_02::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_03::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_03::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_03::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_03::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_03::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_03::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_03::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_03::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_04::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_04::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_04::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_04::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_04::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_04::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_04::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_04::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_05::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_05::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_05::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_05::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_05::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_05::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_05::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_05::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_06::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_06::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_06::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_06::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_06::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_06::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_06::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_06::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_07::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_07::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_07::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_07::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_07::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_07::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_07::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_07::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_08::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_08::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_08::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_08::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_08::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_08::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_08::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_08::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_09::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_09::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_09::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_09::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_09::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_09::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_09::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_09::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_10::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_10::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_10::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_10::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_10::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_10::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_10::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_10::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_11::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_11::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_11::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_11::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_11::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_11::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_11::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_11::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_12::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_12::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_12::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_12::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_12::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_12::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_12::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_12::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_13::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_13::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_13::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_13::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_13::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_13::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_13::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_13::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_14::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_14::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_14::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_14::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_14::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_14::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_14::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_14::SRE_A
• sw_pad_ctl_pad_gpio_ad_b1_15::DSE_A
• sw_pad_ctl_pad_gpio_ad_b1_15::HYS_A
• sw_pad_ctl_pad_gpio_ad_b1_15::ODE_A
• sw_pad_ctl_pad_gpio_ad_b1_15::PKE_A
• sw_pad_ctl_pad_gpio_ad_b1_15::PUE_A
• sw_pad_ctl_pad_gpio_ad_b1_15::PUS_A
• sw_pad_ctl_pad_gpio_ad_b1_15::SPEED_A
• sw_pad_ctl_pad_gpio_ad_b1_15::SRE_A
• sw_pad_ctl_pad_gpio_b0_00::DSE_A
• sw_pad_ctl_pad_gpio_b0_00::HYS_A
• sw_pad_ctl_pad_gpio_b0_00::ODE_A
• sw_pad_ctl_pad_gpio_b0_00::PKE_A
• sw_pad_ctl_pad_gpio_b0_00::PUE_A
• sw_pad_ctl_pad_gpio_b0_00::PUS_A
• sw_pad_ctl_pad_gpio_b0_00::SPEED_A
• sw_pad_ctl_pad_gpio_b0_00::SRE_A
• sw_pad_ctl_pad_gpio_b0_01::DSE_A
• sw_pad_ctl_pad_gpio_b0_01::HYS_A
• sw_pad_ctl_pad_gpio_b0_01::ODE_A
• sw_pad_ctl_pad_gpio_b0_01::PKE_A
• sw_pad_ctl_pad_gpio_b0_01::PUE_A
• sw_pad_ctl_pad_gpio_b0_01::PUS_A
• sw_pad_ctl_pad_gpio_b0_01::SPEED_A
• sw_pad_ctl_pad_gpio_b0_01::SRE_A
• sw_pad_ctl_pad_gpio_b0_02::DSE_A
• sw_pad_ctl_pad_gpio_b0_02::HYS_A
• sw_pad_ctl_pad_gpio_b0_02::ODE_A
• sw_pad_ctl_pad_gpio_b0_02::PKE_A
• sw_pad_ctl_pad_gpio_b0_02::PUE_A
• sw_pad_ctl_pad_gpio_b0_02::PUS_A
• sw_pad_ctl_pad_gpio_b0_02::SPEED_A
• sw_pad_ctl_pad_gpio_b0_02::SRE_A
• sw_pad_ctl_pad_gpio_b0_03::DSE_A
• sw_pad_ctl_pad_gpio_b0_03::HYS_A
• sw_pad_ctl_pad_gpio_b0_03::ODE_A
• sw_pad_ctl_pad_gpio_b0_03::PKE_A
• sw_pad_ctl_pad_gpio_b0_03::PUE_A
• sw_pad_ctl_pad_gpio_b0_03::PUS_A
• sw_pad_ctl_pad_gpio_b0_03::SPEED_A
• sw_pad_ctl_pad_gpio_b0_03::SRE_A
• sw_pad_ctl_pad_gpio_b0_04::DSE_A
• sw_pad_ctl_pad_gpio_b0_04::HYS_A
• sw_pad_ctl_pad_gpio_b0_04::ODE_A
• sw_pad_ctl_pad_gpio_b0_04::PKE_A
• sw_pad_ctl_pad_gpio_b0_04::PUE_A
• sw_pad_ctl_pad_gpio_b0_04::PUS_A
• sw_pad_ctl_pad_gpio_b0_04::SPEED_A
• sw_pad_ctl_pad_gpio_b0_04::SRE_A
• sw_pad_ctl_pad_gpio_b0_05::DSE_A
• sw_pad_ctl_pad_gpio_b0_05::HYS_A
• sw_pad_ctl_pad_gpio_b0_05::ODE_A
• sw_pad_ctl_pad_gpio_b0_05::PKE_A
• sw_pad_ctl_pad_gpio_b0_05::PUE_A
• sw_pad_ctl_pad_gpio_b0_05::PUS_A
• sw_pad_ctl_pad_gpio_b0_05::SPEED_A
• sw_pad_ctl_pad_gpio_b0_05::SRE_A
• sw_pad_ctl_pad_gpio_b0_06::DSE_A
• sw_pad_ctl_pad_gpio_b0_06::HYS_A
• sw_pad_ctl_pad_gpio_b0_06::ODE_A
• sw_pad_ctl_pad_gpio_b0_06::PKE_A
• sw_pad_ctl_pad_gpio_b0_06::PUE_A
• sw_pad_ctl_pad_gpio_b0_06::PUS_A
• sw_pad_ctl_pad_gpio_b0_06::SPEED_A
• sw_pad_ctl_pad_gpio_b0_06::SRE_A
• sw_pad_ctl_pad_gpio_b0_07::DSE_A
• sw_pad_ctl_pad_gpio_b0_07::HYS_A
• sw_pad_ctl_pad_gpio_b0_07::ODE_A
• sw_pad_ctl_pad_gpio_b0_07::PKE_A
• sw_pad_ctl_pad_gpio_b0_07::PUE_A
• sw_pad_ctl_pad_gpio_b0_07::PUS_A
• sw_pad_ctl_pad_gpio_b0_07::SPEED_A
• sw_pad_ctl_pad_gpio_b0_07::SRE_A
• sw_pad_ctl_pad_gpio_b0_08::DSE_A
• sw_pad_ctl_pad_gpio_b0_08::HYS_A
• sw_pad_ctl_pad_gpio_b0_08::ODE_A
• sw_pad_ctl_pad_gpio_b0_08::PKE_A
• sw_pad_ctl_pad_gpio_b0_08::PUE_A
• sw_pad_ctl_pad_gpio_b0_08::PUS_A
• sw_pad_ctl_pad_gpio_b0_08::SPEED_A
• sw_pad_ctl_pad_gpio_b0_08::SRE_A
• sw_pad_ctl_pad_gpio_b0_09::DSE_A
• sw_pad_ctl_pad_gpio_b0_09::HYS_A
• sw_pad_ctl_pad_gpio_b0_09::ODE_A
• sw_pad_ctl_pad_gpio_b0_09::PKE_A
• sw_pad_ctl_pad_gpio_b0_09::PUE_A
• sw_pad_ctl_pad_gpio_b0_09::PUS_A
• sw_pad_ctl_pad_gpio_b0_09::SPEED_A
• sw_pad_ctl_pad_gpio_b0_09::SRE_A
• sw_pad_ctl_pad_gpio_b0_10::DSE_A
• sw_pad_ctl_pad_gpio_b0_10::HYS_A
• sw_pad_ctl_pad_gpio_b0_10::ODE_A
• sw_pad_ctl_pad_gpio_b0_10::PKE_A
• sw_pad_ctl_pad_gpio_b0_10::PUE_A
• sw_pad_ctl_pad_gpio_b0_10::PUS_A
• sw_pad_ctl_pad_gpio_b0_10::SPEED_A
• sw_pad_ctl_pad_gpio_b0_10::SRE_A
• sw_pad_ctl_pad_gpio_b0_11::DSE_A
• sw_pad_ctl_pad_gpio_b0_11::HYS_A
• sw_pad_ctl_pad_gpio_b0_11::ODE_A
• sw_pad_ctl_pad_gpio_b0_11::PKE_A
• sw_pad_ctl_pad_gpio_b0_11::PUE_A
• sw_pad_ctl_pad_gpio_b0_11::PUS_A
• sw_pad_ctl_pad_gpio_b0_11::SPEED_A
• sw_pad_ctl_pad_gpio_b0_11::SRE_A
• sw_pad_ctl_pad_gpio_b0_12::DSE_A
• sw_pad_ctl_pad_gpio_b0_12::HYS_A
• sw_pad_ctl_pad_gpio_b0_12::ODE_A
• sw_pad_ctl_pad_gpio_b0_12::PKE_A
• sw_pad_ctl_pad_gpio_b0_12::PUE_A
• sw_pad_ctl_pad_gpio_b0_12::PUS_A
• sw_pad_ctl_pad_gpio_b0_12::SPEED_A
• sw_pad_ctl_pad_gpio_b0_12::SRE_A
• sw_pad_ctl_pad_gpio_b0_13::DSE_A
• sw_pad_ctl_pad_gpio_b0_13::HYS_A
• sw_pad_ctl_pad_gpio_b0_13::ODE_A
• sw_pad_ctl_pad_gpio_b0_13::PKE_A
• sw_pad_ctl_pad_gpio_b0_13::PUE_A
• sw_pad_ctl_pad_gpio_b0_13::PUS_A
• sw_pad_ctl_pad_gpio_b0_13::SPEED_A
• sw_pad_ctl_pad_gpio_b0_13::SRE_A
• sw_pad_ctl_pad_gpio_b0_14::DSE_A
• sw_pad_ctl_pad_gpio_b0_14::HYS_A
• sw_pad_ctl_pad_gpio_b0_14::ODE_A
• sw_pad_ctl_pad_gpio_b0_14::PKE_A
• sw_pad_ctl_pad_gpio_b0_14::PUE_A
• sw_pad_ctl_pad_gpio_b0_14::PUS_A
• sw_pad_ctl_pad_gpio_b0_14::SPEED_A
• sw_pad_ctl_pad_gpio_b0_14::SRE_A
• sw_pad_ctl_pad_gpio_b0_15::DSE_A
• sw_pad_ctl_pad_gpio_b0_15::HYS_A
• sw_pad_ctl_pad_gpio_b0_15::ODE_A
• sw_pad_ctl_pad_gpio_b0_15::PKE_A
• sw_pad_ctl_pad_gpio_b0_15::PUE_A
• sw_pad_ctl_pad_gpio_b0_15::PUS_A
• sw_pad_ctl_pad_gpio_b0_15::SPEED_A
• sw_pad_ctl_pad_gpio_b0_15::SRE_A
• sw_pad_ctl_pad_gpio_b1_00::DSE_A
• sw_pad_ctl_pad_gpio_b1_00::HYS_A
• sw_pad_ctl_pad_gpio_b1_00::ODE_A
• sw_pad_ctl_pad_gpio_b1_00::PKE_A
• sw_pad_ctl_pad_gpio_b1_00::PUE_A
• sw_pad_ctl_pad_gpio_b1_00::PUS_A
• sw_pad_ctl_pad_gpio_b1_00::SPEED_A
• sw_pad_ctl_pad_gpio_b1_00::SRE_A
• sw_pad_ctl_pad_gpio_b1_01::DSE_A
• sw_pad_ctl_pad_gpio_b1_01::HYS_A
• sw_pad_ctl_pad_gpio_b1_01::ODE_A
• sw_pad_ctl_pad_gpio_b1_01::PKE_A
• sw_pad_ctl_pad_gpio_b1_01::PUE_A
• sw_pad_ctl_pad_gpio_b1_01::PUS_A
• sw_pad_ctl_pad_gpio_b1_01::SPEED_A
• sw_pad_ctl_pad_gpio_b1_01::SRE_A
• sw_pad_ctl_pad_gpio_b1_02::DSE_A
• sw_pad_ctl_pad_gpio_b1_02::HYS_A
• sw_pad_ctl_pad_gpio_b1_02::ODE_A
• sw_pad_ctl_pad_gpio_b1_02::PKE_A
• sw_pad_ctl_pad_gpio_b1_02::PUE_A
• sw_pad_ctl_pad_gpio_b1_02::PUS_A
• sw_pad_ctl_pad_gpio_b1_02::SPEED_A
• sw_pad_ctl_pad_gpio_b1_02::SRE_A
• sw_pad_ctl_pad_gpio_b1_03::DSE_A
• sw_pad_ctl_pad_gpio_b1_03::HYS_A
• sw_pad_ctl_pad_gpio_b1_03::ODE_A
• sw_pad_ctl_pad_gpio_b1_03::PKE_A
• sw_pad_ctl_pad_gpio_b1_03::PUE_A
• sw_pad_ctl_pad_gpio_b1_03::PUS_A
• sw_pad_ctl_pad_gpio_b1_03::SPEED_A
• sw_pad_ctl_pad_gpio_b1_03::SRE_A
• sw_pad_ctl_pad_gpio_b1_04::DSE_A
• sw_pad_ctl_pad_gpio_b1_04::HYS_A
• sw_pad_ctl_pad_gpio_b1_04::ODE_A
• sw_pad_ctl_pad_gpio_b1_04::PKE_A
• sw_pad_ctl_pad_gpio_b1_04::PUE_A
• sw_pad_ctl_pad_gpio_b1_04::PUS_A
• sw_pad_ctl_pad_gpio_b1_04::SPEED_A
• sw_pad_ctl_pad_gpio_b1_04::SRE_A
• sw_pad_ctl_pad_gpio_b1_05::DSE_A
• sw_pad_ctl_pad_gpio_b1_05::HYS_A
• sw_pad_ctl_pad_gpio_b1_05::ODE_A
• sw_pad_ctl_pad_gpio_b1_05::PKE_A
• sw_pad_ctl_pad_gpio_b1_05::PUE_A
• sw_pad_ctl_pad_gpio_b1_05::PUS_A
• sw_pad_ctl_pad_gpio_b1_05::SPEED_A
• sw_pad_ctl_pad_gpio_b1_05::SRE_A
• sw_pad_ctl_pad_gpio_b1_06::DSE_A
• sw_pad_ctl_pad_gpio_b1_06::HYS_A
• sw_pad_ctl_pad_gpio_b1_06::ODE_A
• sw_pad_ctl_pad_gpio_b1_06::PKE_A
• sw_pad_ctl_pad_gpio_b1_06::PUE_A
• sw_pad_ctl_pad_gpio_b1_06::PUS_A
• sw_pad_ctl_pad_gpio_b1_06::SPEED_A
• sw_pad_ctl_pad_gpio_b1_06::SRE_A
• sw_pad_ctl_pad_gpio_b1_07::DSE_A
• sw_pad_ctl_pad_gpio_b1_07::HYS_A
• sw_pad_ctl_pad_gpio_b1_07::ODE_A
• sw_pad_ctl_pad_gpio_b1_07::PKE_A
• sw_pad_ctl_pad_gpio_b1_07::PUE_A
• sw_pad_ctl_pad_gpio_b1_07::PUS_A
• sw_pad_ctl_pad_gpio_b1_07::SPEED_A
• sw_pad_ctl_pad_gpio_b1_07::SRE_A
• sw_pad_ctl_pad_gpio_b1_08::DSE_A
• sw_pad_ctl_pad_gpio_b1_08::HYS_A
• sw_pad_ctl_pad_gpio_b1_08::ODE_A
• sw_pad_ctl_pad_gpio_b1_08::PKE_A
• sw_pad_ctl_pad_gpio_b1_08::PUE_A
• sw_pad_ctl_pad_gpio_b1_08::PUS_A
• sw_pad_ctl_pad_gpio_b1_08::SPEED_A
• sw_pad_ctl_pad_gpio_b1_08::SRE_A
• sw_pad_ctl_pad_gpio_b1_09::DSE_A
• sw_pad_ctl_pad_gpio_b1_09::HYS_A
• sw_pad_ctl_pad_gpio_b1_09::ODE_A
• sw_pad_ctl_pad_gpio_b1_09::PKE_A
• sw_pad_ctl_pad_gpio_b1_09::PUE_A
• sw_pad_ctl_pad_gpio_b1_09::PUS_A
• sw_pad_ctl_pad_gpio_b1_09::SPEED_A
• sw_pad_ctl_pad_gpio_b1_09::SRE_A
• sw_pad_ctl_pad_gpio_b1_10::DSE_A
• sw_pad_ctl_pad_gpio_b1_10::HYS_A
• sw_pad_ctl_pad_gpio_b1_10::ODE_A
• sw_pad_ctl_pad_gpio_b1_10::PKE_A
• sw_pad_ctl_pad_gpio_b1_10::PUE_A
• sw_pad_ctl_pad_gpio_b1_10::PUS_A
• sw_pad_ctl_pad_gpio_b1_10::SPEED_A
• sw_pad_ctl_pad_gpio_b1_10::SRE_A
• sw_pad_ctl_pad_gpio_b1_11::DSE_A
• sw_pad_ctl_pad_gpio_b1_11::HYS_A
• sw_pad_ctl_pad_gpio_b1_11::ODE_A
• sw_pad_ctl_pad_gpio_b1_11::PKE_A
• sw_pad_ctl_pad_gpio_b1_11::PUE_A
• sw_pad_ctl_pad_gpio_b1_11::PUS_A
• sw_pad_ctl_pad_gpio_b1_11::SPEED_A
• sw_pad_ctl_pad_gpio_b1_11::SRE_A
• sw_pad_ctl_pad_gpio_b1_12::DSE_A
• sw_pad_ctl_pad_gpio_b1_12::HYS_A
• sw_pad_ctl_pad_gpio_b1_12::ODE_A
• sw_pad_ctl_pad_gpio_b1_12::PKE_A
• sw_pad_ctl_pad_gpio_b1_12::PUE_A
• sw_pad_ctl_pad_gpio_b1_12::PUS_A
• sw_pad_ctl_pad_gpio_b1_12::SPEED_A
• sw_pad_ctl_pad_gpio_b1_12::SRE_A
• sw_pad_ctl_pad_gpio_b1_13::DSE_A
• sw_pad_ctl_pad_gpio_b1_13::HYS_A
• sw_pad_ctl_pad_gpio_b1_13::ODE_A
• sw_pad_ctl_pad_gpio_b1_13::PKE_A
• sw_pad_ctl_pad_gpio_b1_13::PUE_A
• sw_pad_ctl_pad_gpio_b1_13::PUS_A
• sw_pad_ctl_pad_gpio_b1_13::SPEED_A
• sw_pad_ctl_pad_gpio_b1_13::SRE_A
• sw_pad_ctl_pad_gpio_b1_14::DSE_A
• sw_pad_ctl_pad_gpio_b1_14::HYS_A
• sw_pad_ctl_pad_gpio_b1_14::ODE_A
• sw_pad_ctl_pad_gpio_b1_14::PKE_A
• sw_pad_ctl_pad_gpio_b1_14::PUE_A
• sw_pad_ctl_pad_gpio_b1_14::PUS_A
• sw_pad_ctl_pad_gpio_b1_14::SPEED_A
• sw_pad_ctl_pad_gpio_b1_14::SRE_A
• sw_pad_ctl_pad_gpio_b1_15::DSE_A
• sw_pad_ctl_pad_gpio_b1_15::HYS_A
• sw_pad_ctl_pad_gpio_b1_15::ODE_A
• sw_pad_ctl_pad_gpio_b1_15::PKE_A
• sw_pad_ctl_pad_gpio_b1_15::PUE_A
• sw_pad_ctl_pad_gpio_b1_15::PUS_A
• sw_pad_ctl_pad_gpio_b1_15::SPEED_A
• sw_pad_ctl_pad_gpio_b1_15::SRE_A
• sw_pad_ctl_pad_gpio_emc_00::DSE_A
• sw_pad_ctl_pad_gpio_emc_00::HYS_A
• sw_pad_ctl_pad_gpio_emc_00::ODE_A
• sw_pad_ctl_pad_gpio_emc_00::PKE_A
• sw_pad_ctl_pad_gpio_emc_00::PUE_A
• sw_pad_ctl_pad_gpio_emc_00::PUS_A
• sw_pad_ctl_pad_gpio_emc_00::SPEED_A
• sw_pad_ctl_pad_gpio_emc_00::SRE_A
• sw_pad_ctl_pad_gpio_emc_01::DSE_A
• sw_pad_ctl_pad_gpio_emc_01::HYS_A
• sw_pad_ctl_pad_gpio_emc_01::ODE_A
• sw_pad_ctl_pad_gpio_emc_01::PKE_A
• sw_pad_ctl_pad_gpio_emc_01::PUE_A
• sw_pad_ctl_pad_gpio_emc_01::PUS_A
• sw_pad_ctl_pad_gpio_emc_01::SPEED_A
• sw_pad_ctl_pad_gpio_emc_01::SRE_A
• sw_pad_ctl_pad_gpio_emc_02::DSE_A
• sw_pad_ctl_pad_gpio_emc_02::HYS_A
• sw_pad_ctl_pad_gpio_emc_02::ODE_A
• sw_pad_ctl_pad_gpio_emc_02::PKE_A
• sw_pad_ctl_pad_gpio_emc_02::PUE_A
• sw_pad_ctl_pad_gpio_emc_02::PUS_A
• sw_pad_ctl_pad_gpio_emc_02::SPEED_A
• sw_pad_ctl_pad_gpio_emc_02::SRE_A
• sw_pad_ctl_pad_gpio_emc_03::DSE_A
• sw_pad_ctl_pad_gpio_emc_03::HYS_A
• sw_pad_ctl_pad_gpio_emc_03::ODE_A
• sw_pad_ctl_pad_gpio_emc_03::PKE_A
• sw_pad_ctl_pad_gpio_emc_03::PUE_A
• sw_pad_ctl_pad_gpio_emc_03::PUS_A
• sw_pad_ctl_pad_gpio_emc_03::SPEED_A
• sw_pad_ctl_pad_gpio_emc_03::SRE_A
• sw_pad_ctl_pad_gpio_emc_04::DSE_A
• sw_pad_ctl_pad_gpio_emc_04::HYS_A
• sw_pad_ctl_pad_gpio_emc_04::ODE_A
• sw_pad_ctl_pad_gpio_emc_04::PKE_A
• sw_pad_ctl_pad_gpio_emc_04::PUE_A
• sw_pad_ctl_pad_gpio_emc_04::PUS_A
• sw_pad_ctl_pad_gpio_emc_04::SPEED_A
• sw_pad_ctl_pad_gpio_emc_04::SRE_A
• sw_pad_ctl_pad_gpio_emc_05::DSE_A
• sw_pad_ctl_pad_gpio_emc_05::HYS_A
• sw_pad_ctl_pad_gpio_emc_05::ODE_A
• sw_pad_ctl_pad_gpio_emc_05::PKE_A
• sw_pad_ctl_pad_gpio_emc_05::PUE_A
• sw_pad_ctl_pad_gpio_emc_05::PUS_A
• sw_pad_ctl_pad_gpio_emc_05::SPEED_A
• sw_pad_ctl_pad_gpio_emc_05::SRE_A
• sw_pad_ctl_pad_gpio_emc_06::DSE_A
• sw_pad_ctl_pad_gpio_emc_06::HYS_A
• sw_pad_ctl_pad_gpio_emc_06::ODE_A
• sw_pad_ctl_pad_gpio_emc_06::PKE_A
• sw_pad_ctl_pad_gpio_emc_06::PUE_A
• sw_pad_ctl_pad_gpio_emc_06::PUS_A
• sw_pad_ctl_pad_gpio_emc_06::SPEED_A
• sw_pad_ctl_pad_gpio_emc_06::SRE_A
• sw_pad_ctl_pad_gpio_emc_07::DSE_A
• sw_pad_ctl_pad_gpio_emc_07::HYS_A
• sw_pad_ctl_pad_gpio_emc_07::ODE_A
• sw_pad_ctl_pad_gpio_emc_07::PKE_A
• sw_pad_ctl_pad_gpio_emc_07::PUE_A
• sw_pad_ctl_pad_gpio_emc_07::PUS_A
• sw_pad_ctl_pad_gpio_emc_07::SPEED_A
• sw_pad_ctl_pad_gpio_emc_07::SRE_A
• sw_pad_ctl_pad_gpio_emc_08::DSE_A
• sw_pad_ctl_pad_gpio_emc_08::HYS_A
• sw_pad_ctl_pad_gpio_emc_08::ODE_A
• sw_pad_ctl_pad_gpio_emc_08::PKE_A
• sw_pad_ctl_pad_gpio_emc_08::PUE_A
• sw_pad_ctl_pad_gpio_emc_08::PUS_A
• sw_pad_ctl_pad_gpio_emc_08::SPEED_A
• sw_pad_ctl_pad_gpio_emc_08::SRE_A
• sw_pad_ctl_pad_gpio_emc_09::DSE_A
• sw_pad_ctl_pad_gpio_emc_09::HYS_A
• sw_pad_ctl_pad_gpio_emc_09::ODE_A
• sw_pad_ctl_pad_gpio_emc_09::PKE_A
• sw_pad_ctl_pad_gpio_emc_09::PUE_A
• sw_pad_ctl_pad_gpio_emc_09::PUS_A
• sw_pad_ctl_pad_gpio_emc_09::SPEED_A
• sw_pad_ctl_pad_gpio_emc_09::SRE_A
• sw_pad_ctl_pad_gpio_emc_10::DSE_A
• sw_pad_ctl_pad_gpio_emc_10::HYS_A
• sw_pad_ctl_pad_gpio_emc_10::ODE_A
• sw_pad_ctl_pad_gpio_emc_10::PKE_A
• sw_pad_ctl_pad_gpio_emc_10::PUE_A
• sw_pad_ctl_pad_gpio_emc_10::PUS_A
• sw_pad_ctl_pad_gpio_emc_10::SPEED_A
• sw_pad_ctl_pad_gpio_emc_10::SRE_A
• sw_pad_ctl_pad_gpio_emc_11::DSE_A
• sw_pad_ctl_pad_gpio_emc_11::HYS_A
• sw_pad_ctl_pad_gpio_emc_11::ODE_A
• sw_pad_ctl_pad_gpio_emc_11::PKE_A
• sw_pad_ctl_pad_gpio_emc_11::PUE_A
• sw_pad_ctl_pad_gpio_emc_11::PUS_A
• sw_pad_ctl_pad_gpio_emc_11::SPEED_A
• sw_pad_ctl_pad_gpio_emc_11::SRE_A
• sw_pad_ctl_pad_gpio_emc_12::DSE_A
• sw_pad_ctl_pad_gpio_emc_12::HYS_A
• sw_pad_ctl_pad_gpio_emc_12::ODE_A
• sw_pad_ctl_pad_gpio_emc_12::PKE_A
• sw_pad_ctl_pad_gpio_emc_12::PUE_A
• sw_pad_ctl_pad_gpio_emc_12::PUS_A
• sw_pad_ctl_pad_gpio_emc_12::SPEED_A
• sw_pad_ctl_pad_gpio_emc_12::SRE_A
• sw_pad_ctl_pad_gpio_emc_13::DSE_A
• sw_pad_ctl_pad_gpio_emc_13::HYS_A
• sw_pad_ctl_pad_gpio_emc_13::ODE_A
• sw_pad_ctl_pad_gpio_emc_13::PKE_A
• sw_pad_ctl_pad_gpio_emc_13::PUE_A
• sw_pad_ctl_pad_gpio_emc_13::PUS_A
• sw_pad_ctl_pad_gpio_emc_13::SPEED_A
• sw_pad_ctl_pad_gpio_emc_13::SRE_A
• sw_pad_ctl_pad_gpio_emc_14::DSE_A
• sw_pad_ctl_pad_gpio_emc_14::HYS_A
• sw_pad_ctl_pad_gpio_emc_14::ODE_A
• sw_pad_ctl_pad_gpio_emc_14::PKE_A
• sw_pad_ctl_pad_gpio_emc_14::PUE_A
• sw_pad_ctl_pad_gpio_emc_14::PUS_A
• sw_pad_ctl_pad_gpio_emc_14::SPEED_A
• sw_pad_ctl_pad_gpio_emc_14::SRE_A
• sw_pad_ctl_pad_gpio_emc_15::DSE_A
• sw_pad_ctl_pad_gpio_emc_15::HYS_A
• sw_pad_ctl_pad_gpio_emc_15::ODE_A
• sw_pad_ctl_pad_gpio_emc_15::PKE_A
• sw_pad_ctl_pad_gpio_emc_15::PUE_A
• sw_pad_ctl_pad_gpio_emc_15::PUS_A
• sw_pad_ctl_pad_gpio_emc_15::SPEED_A
• sw_pad_ctl_pad_gpio_emc_15::SRE_A
• sw_pad_ctl_pad_gpio_emc_16::DSE_A
• sw_pad_ctl_pad_gpio_emc_16::HYS_A
• sw_pad_ctl_pad_gpio_emc_16::ODE_A
• sw_pad_ctl_pad_gpio_emc_16::PKE_A
• sw_pad_ctl_pad_gpio_emc_16::PUE_A
• sw_pad_ctl_pad_gpio_emc_16::PUS_A
• sw_pad_ctl_pad_gpio_emc_16::SPEED_A
• sw_pad_ctl_pad_gpio_emc_16::SRE_A
• sw_pad_ctl_pad_gpio_emc_17::DSE_A
• sw_pad_ctl_pad_gpio_emc_17::HYS_A
• sw_pad_ctl_pad_gpio_emc_17::ODE_A
• sw_pad_ctl_pad_gpio_emc_17::PKE_A
• sw_pad_ctl_pad_gpio_emc_17::PUE_A
• sw_pad_ctl_pad_gpio_emc_17::PUS_A
• sw_pad_ctl_pad_gpio_emc_17::SPEED_A
• sw_pad_ctl_pad_gpio_emc_17::SRE_A
• sw_pad_ctl_pad_gpio_emc_18::DSE_A
• sw_pad_ctl_pad_gpio_emc_18::HYS_A
• sw_pad_ctl_pad_gpio_emc_18::ODE_A
• sw_pad_ctl_pad_gpio_emc_18::PKE_A
• sw_pad_ctl_pad_gpio_emc_18::PUE_A
• sw_pad_ctl_pad_gpio_emc_18::PUS_A
• sw_pad_ctl_pad_gpio_emc_18::SPEED_A
• sw_pad_ctl_pad_gpio_emc_18::SRE_A
• sw_pad_ctl_pad_gpio_emc_19::DSE_A
• sw_pad_ctl_pad_gpio_emc_19::HYS_A
• sw_pad_ctl_pad_gpio_emc_19::ODE_A
• sw_pad_ctl_pad_gpio_emc_19::PKE_A
• sw_pad_ctl_pad_gpio_emc_19::PUE_A
• sw_pad_ctl_pad_gpio_emc_19::PUS_A
• sw_pad_ctl_pad_gpio_emc_19::SPEED_A
• sw_pad_ctl_pad_gpio_emc_19::SRE_A
• sw_pad_ctl_pad_gpio_emc_20::DSE_A
• sw_pad_ctl_pad_gpio_emc_20::HYS_A
• sw_pad_ctl_pad_gpio_emc_20::ODE_A
• sw_pad_ctl_pad_gpio_emc_20::PKE_A
• sw_pad_ctl_pad_gpio_emc_20::PUE_A
• sw_pad_ctl_pad_gpio_emc_20::PUS_A
• sw_pad_ctl_pad_gpio_emc_20::SPEED_A
• sw_pad_ctl_pad_gpio_emc_20::SRE_A
• sw_pad_ctl_pad_gpio_emc_21::DSE_A
• sw_pad_ctl_pad_gpio_emc_21::HYS_A
• sw_pad_ctl_pad_gpio_emc_21::ODE_A
• sw_pad_ctl_pad_gpio_emc_21::PKE_A
• sw_pad_ctl_pad_gpio_emc_21::PUE_A
• sw_pad_ctl_pad_gpio_emc_21::PUS_A
• sw_pad_ctl_pad_gpio_emc_21::SPEED_A
• sw_pad_ctl_pad_gpio_emc_21::SRE_A
• sw_pad_ctl_pad_gpio_emc_22::DSE_A
• sw_pad_ctl_pad_gpio_emc_22::HYS_A
• sw_pad_ctl_pad_gpio_emc_22::ODE_A
• sw_pad_ctl_pad_gpio_emc_22::PKE_A
• sw_pad_ctl_pad_gpio_emc_22::PUE_A
• sw_pad_ctl_pad_gpio_emc_22::PUS_A
• sw_pad_ctl_pad_gpio_emc_22::SPEED_A
• sw_pad_ctl_pad_gpio_emc_22::SRE_A
• sw_pad_ctl_pad_gpio_emc_23::DSE_A
• sw_pad_ctl_pad_gpio_emc_23::HYS_A
• sw_pad_ctl_pad_gpio_emc_23::ODE_A
• sw_pad_ctl_pad_gpio_emc_23::PKE_A
• sw_pad_ctl_pad_gpio_emc_23::PUE_A
• sw_pad_ctl_pad_gpio_emc_23::PUS_A
• sw_pad_ctl_pad_gpio_emc_23::SPEED_A
• sw_pad_ctl_pad_gpio_emc_23::SRE_A
• sw_pad_ctl_pad_gpio_emc_24::DSE_A
• sw_pad_ctl_pad_gpio_emc_24::HYS_A
• sw_pad_ctl_pad_gpio_emc_24::ODE_A
• sw_pad_ctl_pad_gpio_emc_24::PKE_A
• sw_pad_ctl_pad_gpio_emc_24::PUE_A
• sw_pad_ctl_pad_gpio_emc_24::PUS_A
• sw_pad_ctl_pad_gpio_emc_24::SPEED_A
• sw_pad_ctl_pad_gpio_emc_24::SRE_A
• sw_pad_ctl_pad_gpio_emc_25::DSE_A
• sw_pad_ctl_pad_gpio_emc_25::HYS_A
• sw_pad_ctl_pad_gpio_emc_25::ODE_A
• sw_pad_ctl_pad_gpio_emc_25::PKE_A
• sw_pad_ctl_pad_gpio_emc_25::PUE_A
• sw_pad_ctl_pad_gpio_emc_25::PUS_A
• sw_pad_ctl_pad_gpio_emc_25::SPEED_A
• sw_pad_ctl_pad_gpio_emc_25::SRE_A
• sw_pad_ctl_pad_gpio_emc_26::DSE_A
• sw_pad_ctl_pad_gpio_emc_26::HYS_A
• sw_pad_ctl_pad_gpio_emc_26::ODE_A
• sw_pad_ctl_pad_gpio_emc_26::PKE_A
• sw_pad_ctl_pad_gpio_emc_26::PUE_A
• sw_pad_ctl_pad_gpio_emc_26::PUS_A
• sw_pad_ctl_pad_gpio_emc_26::SPEED_A
• sw_pad_ctl_pad_gpio_emc_26::SRE_A
• sw_pad_ctl_pad_gpio_emc_27::DSE_A
• sw_pad_ctl_pad_gpio_emc_27::HYS_A
• sw_pad_ctl_pad_gpio_emc_27::ODE_A
• sw_pad_ctl_pad_gpio_emc_27::PKE_A
• sw_pad_ctl_pad_gpio_emc_27::PUE_A
• sw_pad_ctl_pad_gpio_emc_27::PUS_A
• sw_pad_ctl_pad_gpio_emc_27::SPEED_A
• sw_pad_ctl_pad_gpio_emc_27::SRE_A
• sw_pad_ctl_pad_gpio_emc_28::DSE_A
• sw_pad_ctl_pad_gpio_emc_28::HYS_A
• sw_pad_ctl_pad_gpio_emc_28::ODE_A
• sw_pad_ctl_pad_gpio_emc_28::PKE_A
• sw_pad_ctl_pad_gpio_emc_28::PUE_A
• sw_pad_ctl_pad_gpio_emc_28::PUS_A
• sw_pad_ctl_pad_gpio_emc_28::SPEED_A
• sw_pad_ctl_pad_gpio_emc_28::SRE_A
• sw_pad_ctl_pad_gpio_emc_29::DSE_A
• sw_pad_ctl_pad_gpio_emc_29::HYS_A
• sw_pad_ctl_pad_gpio_emc_29::ODE_A
• sw_pad_ctl_pad_gpio_emc_29::PKE_A
• sw_pad_ctl_pad_gpio_emc_29::PUE_A
• sw_pad_ctl_pad_gpio_emc_29::PUS_A
• sw_pad_ctl_pad_gpio_emc_29::SPEED_A
• sw_pad_ctl_pad_gpio_emc_29::SRE_A
• sw_pad_ctl_pad_gpio_emc_30::DSE_A
• sw_pad_ctl_pad_gpio_emc_30::HYS_A
• sw_pad_ctl_pad_gpio_emc_30::ODE_A
• sw_pad_ctl_pad_gpio_emc_30::PKE_A
• sw_pad_ctl_pad_gpio_emc_30::PUE_A
• sw_pad_ctl_pad_gpio_emc_30::PUS_A
• sw_pad_ctl_pad_gpio_emc_30::SPEED_A
• sw_pad_ctl_pad_gpio_emc_30::SRE_A
• sw_pad_ctl_pad_gpio_emc_31::DSE_A
• sw_pad_ctl_pad_gpio_emc_31::HYS_A
• sw_pad_ctl_pad_gpio_emc_31::ODE_A
• sw_pad_ctl_pad_gpio_emc_31::PKE_A
• sw_pad_ctl_pad_gpio_emc_31::PUE_A
• sw_pad_ctl_pad_gpio_emc_31::PUS_A
• sw_pad_ctl_pad_gpio_emc_31::SPEED_A
• sw_pad_ctl_pad_gpio_emc_31::SRE_A
• sw_pad_ctl_pad_gpio_emc_32::DSE_A
• sw_pad_ctl_pad_gpio_emc_32::HYS_A
• sw_pad_ctl_pad_gpio_emc_32::ODE_A
• sw_pad_ctl_pad_gpio_emc_32::PKE_A
• sw_pad_ctl_pad_gpio_emc_32::PUE_A
• sw_pad_ctl_pad_gpio_emc_32::PUS_A
• sw_pad_ctl_pad_gpio_emc_32::SPEED_A
• sw_pad_ctl_pad_gpio_emc_32::SRE_A
• sw_pad_ctl_pad_gpio_emc_33::DSE_A
• sw_pad_ctl_pad_gpio_emc_33::HYS_A
• sw_pad_ctl_pad_gpio_emc_33::ODE_A
• sw_pad_ctl_pad_gpio_emc_33::PKE_A
• sw_pad_ctl_pad_gpio_emc_33::PUE_A
• sw_pad_ctl_pad_gpio_emc_33::PUS_A
• sw_pad_ctl_pad_gpio_emc_33::SPEED_A
• sw_pad_ctl_pad_gpio_emc_33::SRE_A
• sw_pad_ctl_pad_gpio_emc_34::DSE_A
• sw_pad_ctl_pad_gpio_emc_34::HYS_A
• sw_pad_ctl_pad_gpio_emc_34::ODE_A
• sw_pad_ctl_pad_gpio_emc_34::PKE_A
• sw_pad_ctl_pad_gpio_emc_34::PUE_A
• sw_pad_ctl_pad_gpio_emc_34::PUS_A
• sw_pad_ctl_pad_gpio_emc_34::SPEED_A
• sw_pad_ctl_pad_gpio_emc_34::SRE_A
• sw_pad_ctl_pad_gpio_emc_35::DSE_A
• sw_pad_ctl_pad_gpio_emc_35::HYS_A
• sw_pad_ctl_pad_gpio_emc_35::ODE_A
• sw_pad_ctl_pad_gpio_emc_35::PKE_A
• sw_pad_ctl_pad_gpio_emc_35::PUE_A
• sw_pad_ctl_pad_gpio_emc_35::PUS_A
• sw_pad_ctl_pad_gpio_emc_35::SPEED_A
• sw_pad_ctl_pad_gpio_emc_35::SRE_A
• sw_pad_ctl_pad_gpio_emc_36::DSE_A
• sw_pad_ctl_pad_gpio_emc_36::HYS_A
• sw_pad_ctl_pad_gpio_emc_36::ODE_A
• sw_pad_ctl_pad_gpio_emc_36::PKE_A
• sw_pad_ctl_pad_gpio_emc_36::PUE_A
• sw_pad_ctl_pad_gpio_emc_36::PUS_A
• sw_pad_ctl_pad_gpio_emc_36::SPEED_A
• sw_pad_ctl_pad_gpio_emc_36::SRE_A
• sw_pad_ctl_pad_gpio_emc_37::DSE_A
• sw_pad_ctl_pad_gpio_emc_37::HYS_A
• sw_pad_ctl_pad_gpio_emc_37::ODE_A
• sw_pad_ctl_pad_gpio_emc_37::PKE_A
• sw_pad_ctl_pad_gpio_emc_37::PUE_A
• sw_pad_ctl_pad_gpio_emc_37::PUS_A
• sw_pad_ctl_pad_gpio_emc_37::SPEED_A
• sw_pad_ctl_pad_gpio_emc_37::SRE_A
• sw_pad_ctl_pad_gpio_emc_38::DSE_A
• sw_pad_ctl_pad_gpio_emc_38::HYS_A
• sw_pad_ctl_pad_gpio_emc_38::ODE_A
• sw_pad_ctl_pad_gpio_emc_38::PKE_A
• sw_pad_ctl_pad_gpio_emc_38::PUE_A
• sw_pad_ctl_pad_gpio_emc_38::PUS_A
• sw_pad_ctl_pad_gpio_emc_38::SPEED_A
• sw_pad_ctl_pad_gpio_emc_38::SRE_A
• sw_pad_ctl_pad_gpio_emc_39::DSE_A
• sw_pad_ctl_pad_gpio_emc_39::HYS_A
• sw_pad_ctl_pad_gpio_emc_39::ODE_A
• sw_pad_ctl_pad_gpio_emc_39::PKE_A
• sw_pad_ctl_pad_gpio_emc_39::PUE_A
• sw_pad_ctl_pad_gpio_emc_39::PUS_A
• sw_pad_ctl_pad_gpio_emc_39::SPEED_A
• sw_pad_ctl_pad_gpio_emc_39::SRE_A
• sw_pad_ctl_pad_gpio_emc_40::DSE_A
• sw_pad_ctl_pad_gpio_emc_40::HYS_A
• sw_pad_ctl_pad_gpio_emc_40::ODE_A
• sw_pad_ctl_pad_gpio_emc_40::PKE_A
• sw_pad_ctl_pad_gpio_emc_40::PUE_A
• sw_pad_ctl_pad_gpio_emc_40::PUS_A
• sw_pad_ctl_pad_gpio_emc_40::SPEED_A
• sw_pad_ctl_pad_gpio_emc_40::SRE_A
• sw_pad_ctl_pad_gpio_emc_41::DSE_A
• sw_pad_ctl_pad_gpio_emc_41::HYS_A
• sw_pad_ctl_pad_gpio_emc_41::ODE_A
• sw_pad_ctl_pad_gpio_emc_41::PKE_A
• sw_pad_ctl_pad_gpio_emc_41::PUE_A
• sw_pad_ctl_pad_gpio_emc_41::PUS_A
• sw_pad_ctl_pad_gpio_emc_41::SPEED_A
• sw_pad_ctl_pad_gpio_emc_41::SRE_A
• sw_pad_ctl_pad_gpio_sd_b0_00::DSE_A
• sw_pad_ctl_pad_gpio_sd_b0_00::HYS_A
• sw_pad_ctl_pad_gpio_sd_b0_00::ODE_A
• sw_pad_ctl_pad_gpio_sd_b0_00::PKE_A
• sw_pad_ctl_pad_gpio_sd_b0_00::PUE_A
• sw_pad_ctl_pad_gpio_sd_b0_00::PUS_A
• sw_pad_ctl_pad_gpio_sd_b0_00::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b0_00::SRE_A
• sw_pad_ctl_pad_gpio_sd_b0_01::DSE_A
• sw_pad_ctl_pad_gpio_sd_b0_01::HYS_A
• sw_pad_ctl_pad_gpio_sd_b0_01::ODE_A
• sw_pad_ctl_pad_gpio_sd_b0_01::PKE_A
• sw_pad_ctl_pad_gpio_sd_b0_01::PUE_A
• sw_pad_ctl_pad_gpio_sd_b0_01::PUS_A
• sw_pad_ctl_pad_gpio_sd_b0_01::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b0_01::SRE_A
• sw_pad_ctl_pad_gpio_sd_b0_02::DSE_A
• sw_pad_ctl_pad_gpio_sd_b0_02::HYS_A
• sw_pad_ctl_pad_gpio_sd_b0_02::ODE_A
• sw_pad_ctl_pad_gpio_sd_b0_02::PKE_A
• sw_pad_ctl_pad_gpio_sd_b0_02::PUE_A
• sw_pad_ctl_pad_gpio_sd_b0_02::PUS_A
• sw_pad_ctl_pad_gpio_sd_b0_02::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b0_02::SRE_A
• sw_pad_ctl_pad_gpio_sd_b0_03::DSE_A
• sw_pad_ctl_pad_gpio_sd_b0_03::HYS_A
• sw_pad_ctl_pad_gpio_sd_b0_03::ODE_A
• sw_pad_ctl_pad_gpio_sd_b0_03::PKE_A
• sw_pad_ctl_pad_gpio_sd_b0_03::PUE_A
• sw_pad_ctl_pad_gpio_sd_b0_03::PUS_A
• sw_pad_ctl_pad_gpio_sd_b0_03::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b0_03::SRE_A
• sw_pad_ctl_pad_gpio_sd_b0_04::DSE_A
• sw_pad_ctl_pad_gpio_sd_b0_04::HYS_A
• sw_pad_ctl_pad_gpio_sd_b0_04::ODE_A
• sw_pad_ctl_pad_gpio_sd_b0_04::PKE_A
• sw_pad_ctl_pad_gpio_sd_b0_04::PUE_A
• sw_pad_ctl_pad_gpio_sd_b0_04::PUS_A
• sw_pad_ctl_pad_gpio_sd_b0_04::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b0_04::SRE_A
• sw_pad_ctl_pad_gpio_sd_b0_05::DSE_A
• sw_pad_ctl_pad_gpio_sd_b0_05::HYS_A
• sw_pad_ctl_pad_gpio_sd_b0_05::ODE_A
• sw_pad_ctl_pad_gpio_sd_b0_05::PKE_A
• sw_pad_ctl_pad_gpio_sd_b0_05::PUE_A
• sw_pad_ctl_pad_gpio_sd_b0_05::PUS_A
• sw_pad_ctl_pad_gpio_sd_b0_05::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b0_05::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_00::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_00::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_00::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_00::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_00::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_00::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_00::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_00::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_01::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_01::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_01::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_01::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_01::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_01::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_01::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_01::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_02::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_02::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_02::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_02::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_02::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_02::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_02::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_02::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_03::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_03::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_03::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_03::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_03::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_03::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_03::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_03::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_04::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_04::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_04::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_04::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_04::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_04::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_04::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_04::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_05::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_05::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_05::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_05::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_05::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_05::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_05::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_05::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_06::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_06::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_06::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_06::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_06::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_06::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_06::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_06::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_07::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_07::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_07::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_07::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_07::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_07::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_07::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_07::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_08::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_08::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_08::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_08::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_08::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_08::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_08::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_08::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_09::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_09::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_09::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_09::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_09::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_09::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_09::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_09::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_10::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_10::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_10::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_10::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_10::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_10::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_10::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_10::SRE_A
• sw_pad_ctl_pad_gpio_sd_b1_11::DSE_A
• sw_pad_ctl_pad_gpio_sd_b1_11::HYS_A
• sw_pad_ctl_pad_gpio_sd_b1_11::ODE_A
• sw_pad_ctl_pad_gpio_sd_b1_11::PKE_A
• sw_pad_ctl_pad_gpio_sd_b1_11::PUE_A
• sw_pad_ctl_pad_gpio_sd_b1_11::PUS_A
• sw_pad_ctl_pad_gpio_sd_b1_11::SPEED_A
• sw_pad_ctl_pad_gpio_sd_b1_11::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_00::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_00::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_00::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_00::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_00::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_00::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_00::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_00::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_01::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_01::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_01::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_01::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_01::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_01::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_01::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_01::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_02::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_02::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_02::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_02::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_02::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_02::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_02::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_02::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_03::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_03::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_03::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_03::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_03::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_03::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_03::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_03::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_04::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_04::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_04::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_04::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_04::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_04::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_04::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_04::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_05::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_05::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_05::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_05::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_05::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_05::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_05::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_05::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_06::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_06::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_06::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_06::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_06::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_06::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_06::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_06::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_07::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_07::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_07::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_07::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_07::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_07::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_07::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_07::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_08::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_08::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_08::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_08::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_08::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_08::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_08::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_08::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_09::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_09::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_09::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_09::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_09::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_09::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_09::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_09::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_10::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_10::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_10::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_10::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_10::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_10::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_10::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_10::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_11::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_11::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_11::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_11::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_11::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_11::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_11::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_11::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_12::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_12::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_12::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_12::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_12::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_12::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_12::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_12::SRE_A
• sw_pad_ctl_pad_gpio_spi_b0_13::DSE_A
• sw_pad_ctl_pad_gpio_spi_b0_13::HYS_A
• sw_pad_ctl_pad_gpio_spi_b0_13::ODE_A
• sw_pad_ctl_pad_gpio_spi_b0_13::PKE_A
• sw_pad_ctl_pad_gpio_spi_b0_13::PUE_A
• sw_pad_ctl_pad_gpio_spi_b0_13::PUS_A
• sw_pad_ctl_pad_gpio_spi_b0_13::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b0_13::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_00::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_00::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_00::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_00::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_00::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_00::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_00::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_00::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_01::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_01::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_01::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_01::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_01::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_01::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_01::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_01::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_02::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_02::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_02::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_02::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_02::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_02::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_02::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_02::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_03::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_03::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_03::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_03::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_03::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_03::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_03::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_03::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_04::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_04::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_04::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_04::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_04::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_04::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_04::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_04::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_05::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_05::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_05::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_05::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_05::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_05::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_05::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_05::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_06::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_06::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_06::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_06::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_06::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_06::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_06::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_06::SRE_A
• sw_pad_ctl_pad_gpio_spi_b1_07::DSE_A
• sw_pad_ctl_pad_gpio_spi_b1_07::HYS_A
• sw_pad_ctl_pad_gpio_spi_b1_07::ODE_A
• sw_pad_ctl_pad_gpio_spi_b1_07::PKE_A
• sw_pad_ctl_pad_gpio_spi_b1_07::PUE_A
• sw_pad_ctl_pad_gpio_spi_b1_07::PUS_A
• sw_pad_ctl_pad_gpio_spi_b1_07::SPEED_A
• sw_pad_ctl_pad_gpio_spi_b1_07::SRE_A
• usb_otg1_oc_select_input::DAISY_A
• usb_otg2_oc_select_input::DAISY_A
• usdhc1_cd_b_select_input::DAISY_A
• usdhc1_wp_select_input::DAISY_A
• usdhc2_cd_b_select_input::DAISY_A
• usdhc2_clk_select_input::DAISY_A
• usdhc2_cmd_select_input::DAISY_A
• usdhc2_data0_select_input::DAISY_A
• usdhc2_data1_select_input::DAISY_A
• usdhc2_data2_select_input::DAISY_A
• usdhc2_data3_select_input::DAISY_A
• usdhc2_data4_select_input::DAISY_A
• usdhc2_data5_select_input::DAISY_A
• usdhc2_data6_select_input::DAISY_A
• usdhc2_data7_select_input::DAISY_A
• usdhc2_wp_select_input::DAISY_A
• xbar1_in02_select_input::DAISY_A
• xbar1_in03_select_input::DAISY_A
• xbar1_in04_select_input::DAISY_A
• xbar1_in05_select_input::DAISY_A
• xbar1_in06_select_input::DAISY_A
• xbar1_in07_select_input::DAISY_A
• xbar1_in08_select_input::DAISY_A
• xbar1_in09_select_input::DAISY_A
• xbar1_in14_select_input::DAISY_A
• xbar1_in15_select_input::DAISY_A
• xbar1_in16_select_input::DAISY_A
• xbar1_in17_select_input::DAISY_A
• xbar1_in18_select_input::DAISY_A
• xbar1_in19_select_input::DAISY_A
• xbar1_in20_select_input::DAISY_A
• xbar1_in21_select_input::DAISY_A
• xbar1_in22_select_input::DAISY_A
• xbar1_in23_select_input::DAISY_A
• xbar1_in24_select_input::DAISY_A
• xbar1_in25_select_input::DAISY_A

Traits

• Readable
• ResetValue
• Writable

Typedefs

• ANATOP_USB_OTG1_ID_SELECT_INPUT
• ANATOP_USB_OTG2_ID_SELECT_INPUT
• CANFD_IPP_IND_CANRX_SELECT_INPUT
• CCM_PMIC_READY_SELECT_INPUT
• CSI_DATA02_SELECT_INPUT
• CSI_DATA03_SELECT_INPUT
• CSI_DATA04_SELECT_INPUT
• CSI_DATA05_SELECT_INPUT
• CSI_DATA06_SELECT_INPUT
• CSI_DATA07_SELECT_INPUT
• CSI_DATA08_SELECT_INPUT
• CSI_DATA09_SELECT_INPUT
• CSI_HSYNC_SELECT_INPUT
• CSI_PIXCLK_SELECT_INPUT
• CSI_VSYNC_SELECT_INPUT
• ENET0_RXDATA_SELECT_INPUT
• ENET0_TIMER_SELECT_INPUT
• ENET1_RXDATA_SELECT_INPUT
• ENET2_IPG_CLK_RMII_SELECT_INPUT
• ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT
• ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0
• ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1
• ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT
• ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT
• ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0
• ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT
• ENET_IPG_CLK_RMII_SELECT_INPUT
• ENET_MDIO_SELECT_INPUT
• ENET_RXEN_SELECT_INPUT
• ENET_RXERR_SELECT_INPUT
• ENET_TXCLK_SELECT_INPUT
• FLEXCAN1_RX_SELECT_INPUT
• FLEXCAN2_RX_SELECT_INPUT
• FLEXPWM1_PWMA0_SELECT_INPUT
• FLEXPWM1_PWMA1_SELECT_INPUT
• FLEXPWM1_PWMA2_SELECT_INPUT
• FLEXPWM1_PWMA3_SELECT_INPUT
• FLEXPWM1_PWMB0_SELECT_INPUT
• FLEXPWM1_PWMB1_SELECT_INPUT
• FLEXPWM1_PWMB2_SELECT_INPUT
• FLEXPWM1_PWMB3_SELECT_INPUT
• FLEXPWM2_PWMA0_SELECT_INPUT
• FLEXPWM2_PWMA1_SELECT_INPUT
• FLEXPWM2_PWMA2_SELECT_INPUT
• FLEXPWM2_PWMA3_SELECT_INPUT
• FLEXPWM2_PWMB0_SELECT_INPUT
• FLEXPWM2_PWMB1_SELECT_INPUT
• FLEXPWM2_PWMB2_SELECT_INPUT
• FLEXPWM2_PWMB3_SELECT_INPUT
• FLEXPWM4_PWMA0_SELECT_INPUT
• FLEXPWM4_PWMA1_SELECT_INPUT
• FLEXPWM4_PWMA2_SELECT_INPUT
• FLEXPWM4_PWMA3_SELECT_INPUT
• FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT
• FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT
• FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT
• FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT
• FLEXSPIA_DATA0_SELECT_INPUT
• FLEXSPIA_DATA1_SELECT_INPUT
• FLEXSPIA_DATA2_SELECT_INPUT
• FLEXSPIA_DATA3_SELECT_INPUT
• FLEXSPIA_DQS_SELECT_INPUT
• FLEXSPIA_SCK_SELECT_INPUT
• FLEXSPIB_DATA0_SELECT_INPUT
• FLEXSPIB_DATA1_SELECT_INPUT
• FLEXSPIB_DATA2_SELECT_INPUT
• FLEXSPIB_DATA3_SELECT_INPUT
• GPT1_IPP_IND_CAPIN1_SELECT_INPUT
• GPT1_IPP_IND_CAPIN2_SELECT_INPUT
• GPT1_IPP_IND_CLKIN_SELECT_INPUT
• GPT2_IPP_IND_CAPIN1_SELECT_INPUT
• GPT2_IPP_IND_CAPIN2_SELECT_INPUT
• GPT2_IPP_IND_CLKIN_SELECT_INPUT
• LPI2C1_SCL_SELECT_INPUT
• LPI2C1_SDA_SELECT_INPUT
• LPI2C2_SCL_SELECT_INPUT
• LPI2C2_SDA_SELECT_INPUT
• LPI2C3_SCL_SELECT_INPUT
• LPI2C3_SDA_SELECT_INPUT
• LPI2C4_SCL_SELECT_INPUT
• LPI2C4_SDA_SELECT_INPUT
• LPSPI1_PCS0_SELECT_INPUT
• LPSPI1_SCK_SELECT_INPUT
• LPSPI1_SDI_SELECT_INPUT
• LPSPI1_SDO_SELECT_INPUT
• LPSPI2_PCS0_SELECT_INPUT
• LPSPI2_SCK_SELECT_INPUT
• LPSPI2_SDI_SELECT_INPUT
• LPSPI2_SDO_SELECT_INPUT
• LPSPI3_PCS0_SELECT_INPUT
• LPSPI3_SCK_SELECT_INPUT
• LPSPI3_SDI_SELECT_INPUT
• LPSPI3_SDO_SELECT_INPUT
• LPSPI4_PCS0_SELECT_INPUT
• LPSPI4_SCK_SELECT_INPUT
• LPSPI4_SDI_SELECT_INPUT
• LPSPI4_SDO_SELECT_INPUT
• LPUART2_RX_SELECT_INPUT
• LPUART2_TX_SELECT_INPUT
• LPUART3_CTS_B_SELECT_INPUT
• LPUART3_RX_SELECT_INPUT
• LPUART3_TX_SELECT_INPUT
• LPUART4_RX_SELECT_INPUT
• LPUART4_TX_SELECT_INPUT
• LPUART5_RX_SELECT_INPUT
• LPUART5_TX_SELECT_INPUT
• LPUART6_RX_SELECT_INPUT
• LPUART6_TX_SELECT_INPUT
• LPUART7_RX_SELECT_INPUT
• LPUART7_TX_SELECT_INPUT
• LPUART8_RX_SELECT_INPUT
• LPUART8_TX_SELECT_INPUT
• NMI_SELECT_INPUT
• QTIMER2_TIMER0_SELECT_INPUT
• QTIMER2_TIMER1_SELECT_INPUT
• QTIMER2_TIMER2_SELECT_INPUT
• QTIMER2_TIMER3_SELECT_INPUT
• QTIMER3_TIMER0_SELECT_INPUT
• QTIMER3_TIMER1_SELECT_INPUT
• QTIMER3_TIMER2_SELECT_INPUT
• QTIMER3_TIMER3_SELECT_INPUT
• SAI1_MCLK2_SELECT_INPUT
• SAI1_RX_BCLK_SELECT_INPUT
• SAI1_RX_DATA0_SELECT_INPUT
• SAI1_RX_DATA1_SELECT_INPUT
• SAI1_RX_DATA2_SELECT_INPUT
• SAI1_RX_DATA3_SELECT_INPUT
• SAI1_RX_SYNC_SELECT_INPUT
• SAI1_TX_BCLK_SELECT_INPUT
• SAI1_TX_SYNC_SELECT_INPUT
• SAI2_MCLK2_SELECT_INPUT
• SAI2_RX_BCLK_SELECT_INPUT
• SAI2_RX_DATA0_SELECT_INPUT
• SAI2_RX_SYNC_SELECT_INPUT
• SAI2_TX_BCLK_SELECT_INPUT
• SAI2_TX_SYNC_SELECT_INPUT
• SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2
• SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT
• SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0
• SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT
• SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT
• SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT
• SEMC_I_IPP_IND_DQS4_SELECT_INPUT
• SPDIF_IN_SELECT_INPUT
• SW_MUX_CTL_PAD_GPIO_AD_B0_00
• SW_MUX_CTL_PAD_GPIO_AD_B0_01
• SW_MUX_CTL_PAD_GPIO_AD_B0_02
• SW_MUX_CTL_PAD_GPIO_AD_B0_03
• SW_MUX_CTL_PAD_GPIO_AD_B0_04
• SW_MUX_CTL_PAD_GPIO_AD_B0_05
• SW_MUX_CTL_PAD_GPIO_AD_B0_06
• SW_MUX_CTL_PAD_GPIO_AD_B0_07
• SW_MUX_CTL_PAD_GPIO_AD_B0_08
• SW_MUX_CTL_PAD_GPIO_AD_B0_09
• SW_MUX_CTL_PAD_GPIO_AD_B0_10
• SW_MUX_CTL_PAD_GPIO_AD_B0_11
• SW_MUX_CTL_PAD_GPIO_AD_B0_12
• SW_MUX_CTL_PAD_GPIO_AD_B0_13
• SW_MUX_CTL_PAD_GPIO_AD_B0_14
• SW_MUX_CTL_PAD_GPIO_AD_B0_15
• SW_MUX_CTL_PAD_GPIO_AD_B1_00
• SW_MUX_CTL_PAD_GPIO_AD_B1_01
• SW_MUX_CTL_PAD_GPIO_AD_B1_02
• SW_MUX_CTL_PAD_GPIO_AD_B1_03
• SW_MUX_CTL_PAD_GPIO_AD_B1_04
• SW_MUX_CTL_PAD_GPIO_AD_B1_05
• SW_MUX_CTL_PAD_GPIO_AD_B1_06
• SW_MUX_CTL_PAD_GPIO_AD_B1_07
• SW_MUX_CTL_PAD_GPIO_AD_B1_08
• SW_MUX_CTL_PAD_GPIO_AD_B1_09
• SW_MUX_CTL_PAD_GPIO_AD_B1_10
• SW_MUX_CTL_PAD_GPIO_AD_B1_11
• SW_MUX_CTL_PAD_GPIO_AD_B1_12
• SW_MUX_CTL_PAD_GPIO_AD_B1_13
• SW_MUX_CTL_PAD_GPIO_AD_B1_14
• SW_MUX_CTL_PAD_GPIO_AD_B1_15
• SW_MUX_CTL_PAD_GPIO_B0_00
• SW_MUX_CTL_PAD_GPIO_B0_01
• SW_MUX_CTL_PAD_GPIO_B0_02
• SW_MUX_CTL_PAD_GPIO_B0_03
• SW_MUX_CTL_PAD_GPIO_B0_04
• SW_MUX_CTL_PAD_GPIO_B0_05
• SW_MUX_CTL_PAD_GPIO_B0_06
• SW_MUX_CTL_PAD_GPIO_B0_07
• SW_MUX_CTL_PAD_GPIO_B0_08
• SW_MUX_CTL_PAD_GPIO_B0_09
• SW_MUX_CTL_PAD_GPIO_B0_10
• SW_MUX_CTL_PAD_GPIO_B0_11
• SW_MUX_CTL_PAD_GPIO_B0_12
• SW_MUX_CTL_PAD_GPIO_B0_13
• SW_MUX_CTL_PAD_GPIO_B0_14
• SW_MUX_CTL_PAD_GPIO_B0_15
• SW_MUX_CTL_PAD_GPIO_B1_00
• SW_MUX_CTL_PAD_GPIO_B1_01
• SW_MUX_CTL_PAD_GPIO_B1_02
• SW_MUX_CTL_PAD_GPIO_B1_03
• SW_MUX_CTL_PAD_GPIO_B1_04
• SW_MUX_CTL_PAD_GPIO_B1_05
• SW_MUX_CTL_PAD_GPIO_B1_06
• SW_MUX_CTL_PAD_GPIO_B1_07
• SW_MUX_CTL_PAD_GPIO_B1_08
• SW_MUX_CTL_PAD_GPIO_B1_09
• SW_MUX_CTL_PAD_GPIO_B1_10
• SW_MUX_CTL_PAD_GPIO_B1_11
• SW_MUX_CTL_PAD_GPIO_B1_12
• SW_MUX_CTL_PAD_GPIO_B1_13
• SW_MUX_CTL_PAD_GPIO_B1_14
• SW_MUX_CTL_PAD_GPIO_B1_15
• SW_MUX_CTL_PAD_GPIO_EMC_00
• SW_MUX_CTL_PAD_GPIO_EMC_01
• SW_MUX_CTL_PAD_GPIO_EMC_02
• SW_MUX_CTL_PAD_GPIO_EMC_03
• SW_MUX_CTL_PAD_GPIO_EMC_04
• SW_MUX_CTL_PAD_GPIO_EMC_05
• SW_MUX_CTL_PAD_GPIO_EMC_06
• SW_MUX_CTL_PAD_GPIO_EMC_07
• SW_MUX_CTL_PAD_GPIO_EMC_08
• SW_MUX_CTL_PAD_GPIO_EMC_09
• SW_MUX_CTL_PAD_GPIO_EMC_10
• SW_MUX_CTL_PAD_GPIO_EMC_11
• SW_MUX_CTL_PAD_GPIO_EMC_12
• SW_MUX_CTL_PAD_GPIO_EMC_13
• SW_MUX_CTL_PAD_GPIO_EMC_14
• SW_MUX_CTL_PAD_GPIO_EMC_15
• SW_MUX_CTL_PAD_GPIO_EMC_16
• SW_MUX_CTL_PAD_GPIO_EMC_17
• SW_MUX_CTL_PAD_GPIO_EMC_18
• SW_MUX_CTL_PAD_GPIO_EMC_19
• SW_MUX_CTL_PAD_GPIO_EMC_20
• SW_MUX_CTL_PAD_GPIO_EMC_21
• SW_MUX_CTL_PAD_GPIO_EMC_22
• SW_MUX_CTL_PAD_GPIO_EMC_23
• SW_MUX_CTL_PAD_GPIO_EMC_24
• SW_MUX_CTL_PAD_GPIO_EMC_25
• SW_MUX_CTL_PAD_GPIO_EMC_26
• SW_MUX_CTL_PAD_GPIO_EMC_27
• SW_MUX_CTL_PAD_GPIO_EMC_28
• SW_MUX_CTL_PAD_GPIO_EMC_29
• SW_MUX_CTL_PAD_GPIO_EMC_30
• SW_MUX_CTL_PAD_GPIO_EMC_31
• SW_MUX_CTL_PAD_GPIO_EMC_32
• SW_MUX_CTL_PAD_GPIO_EMC_33
• SW_MUX_CTL_PAD_GPIO_EMC_34
• SW_MUX_CTL_PAD_GPIO_EMC_35
• SW_MUX_CTL_PAD_GPIO_EMC_36
• SW_MUX_CTL_PAD_GPIO_EMC_37
• SW_MUX_CTL_PAD_GPIO_EMC_38
• SW_MUX_CTL_PAD_GPIO_EMC_39
• SW_MUX_CTL_PAD_GPIO_EMC_40
• SW_MUX_CTL_PAD_GPIO_EMC_41
• SW_MUX_CTL_PAD_GPIO_SD_B0_00
• SW_MUX_CTL_PAD_GPIO_SD_B0_01
• SW_MUX_CTL_PAD_GPIO_SD_B0_02
• SW_MUX_CTL_PAD_GPIO_SD_B0_03
• SW_MUX_CTL_PAD_GPIO_SD_B0_04
• SW_MUX_CTL_PAD_GPIO_SD_B0_05
• SW_MUX_CTL_PAD_GPIO_SD_B1_00
• SW_MUX_CTL_PAD_GPIO_SD_B1_01
• SW_MUX_CTL_PAD_GPIO_SD_B1_02
• SW_MUX_CTL_PAD_GPIO_SD_B1_03
• SW_MUX_CTL_PAD_GPIO_SD_B1_04
• SW_MUX_CTL_PAD_GPIO_SD_B1_05
• SW_MUX_CTL_PAD_GPIO_SD_B1_06
• SW_MUX_CTL_PAD_GPIO_SD_B1_07
• SW_MUX_CTL_PAD_GPIO_SD_B1_08
• SW_MUX_CTL_PAD_GPIO_SD_B1_09
• SW_MUX_CTL_PAD_GPIO_SD_B1_10
• SW_MUX_CTL_PAD_GPIO_SD_B1_11
• SW_MUX_CTL_PAD_GPIO_SPI_B0_00
• SW_MUX_CTL_PAD_GPIO_SPI_B0_01
• SW_MUX_CTL_PAD_GPIO_SPI_B0_02
• SW_MUX_CTL_PAD_GPIO_SPI_B0_03
• SW_MUX_CTL_PAD_GPIO_SPI_B0_04
• SW_MUX_CTL_PAD_GPIO_SPI_B0_05
• SW_MUX_CTL_PAD_GPIO_SPI_B0_06
• SW_MUX_CTL_PAD_GPIO_SPI_B0_07
• SW_MUX_CTL_PAD_GPIO_SPI_B0_08
• SW_MUX_CTL_PAD_GPIO_SPI_B0_09
• SW_MUX_CTL_PAD_GPIO_SPI_B0_10
• SW_MUX_CTL_PAD_GPIO_SPI_B0_11
• SW_MUX_CTL_PAD_GPIO_SPI_B0_12
• SW_MUX_CTL_PAD_GPIO_SPI_B0_13
• SW_MUX_CTL_PAD_GPIO_SPI_B1_00
• SW_MUX_CTL_PAD_GPIO_SPI_B1_01
• SW_MUX_CTL_PAD_GPIO_SPI_B1_02
• SW_MUX_CTL_PAD_GPIO_SPI_B1_03
• SW_MUX_CTL_PAD_GPIO_SPI_B1_04
• SW_MUX_CTL_PAD_GPIO_SPI_B1_05
• SW_MUX_CTL_PAD_GPIO_SPI_B1_06
• SW_MUX_CTL_PAD_GPIO_SPI_B1_07
• SW_PAD_CTL_PAD_GPIO_AD_B0_00
• SW_PAD_CTL_PAD_GPIO_AD_B0_01
• SW_PAD_CTL_PAD_GPIO_AD_B0_02
• SW_PAD_CTL_PAD_GPIO_AD_B0_03
• SW_PAD_CTL_PAD_GPIO_AD_B0_04
• SW_PAD_CTL_PAD_GPIO_AD_B0_05
• SW_PAD_CTL_PAD_GPIO_AD_B0_06
• SW_PAD_CTL_PAD_GPIO_AD_B0_07
• SW_PAD_CTL_PAD_GPIO_AD_B0_08
• SW_PAD_CTL_PAD_GPIO_AD_B0_09
• SW_PAD_CTL_PAD_GPIO_AD_B0_10
• SW_PAD_CTL_PAD_GPIO_AD_B0_11
• SW_PAD_CTL_PAD_GPIO_AD_B0_12
• SW_PAD_CTL_PAD_GPIO_AD_B0_13
• SW_PAD_CTL_PAD_GPIO_AD_B0_14
• SW_PAD_CTL_PAD_GPIO_AD_B0_15
• SW_PAD_CTL_PAD_GPIO_AD_B1_00
• SW_PAD_CTL_PAD_GPIO_AD_B1_01
• SW_PAD_CTL_PAD_GPIO_AD_B1_02
• SW_PAD_CTL_PAD_GPIO_AD_B1_03
• SW_PAD_CTL_PAD_GPIO_AD_B1_04
• SW_PAD_CTL_PAD_GPIO_AD_B1_05
• SW_PAD_CTL_PAD_GPIO_AD_B1_06
• SW_PAD_CTL_PAD_GPIO_AD_B1_07
• SW_PAD_CTL_PAD_GPIO_AD_B1_08
• SW_PAD_CTL_PAD_GPIO_AD_B1_09
• SW_PAD_CTL_PAD_GPIO_AD_B1_10
• SW_PAD_CTL_PAD_GPIO_AD_B1_11
• SW_PAD_CTL_PAD_GPIO_AD_B1_12
• SW_PAD_CTL_PAD_GPIO_AD_B1_13
• SW_PAD_CTL_PAD_GPIO_AD_B1_14
• SW_PAD_CTL_PAD_GPIO_AD_B1_15
• SW_PAD_CTL_PAD_GPIO_B0_00
• SW_PAD_CTL_PAD_GPIO_B0_01
• SW_PAD_CTL_PAD_GPIO_B0_02
• SW_PAD_CTL_PAD_GPIO_B0_03
• SW_PAD_CTL_PAD_GPIO_B0_04
• SW_PAD_CTL_PAD_GPIO_B0_05
• SW_PAD_CTL_PAD_GPIO_B0_06
• SW_PAD_CTL_PAD_GPIO_B0_07
• SW_PAD_CTL_PAD_GPIO_B0_08
• SW_PAD_CTL_PAD_GPIO_B0_09
• SW_PAD_CTL_PAD_GPIO_B0_10
• SW_PAD_CTL_PAD_GPIO_B0_11
• SW_PAD_CTL_PAD_GPIO_B0_12
• SW_PAD_CTL_PAD_GPIO_B0_13
• SW_PAD_CTL_PAD_GPIO_B0_14
• SW_PAD_CTL_PAD_GPIO_B0_15
• SW_PAD_CTL_PAD_GPIO_B1_00
• SW_PAD_CTL_PAD_GPIO_B1_01
• SW_PAD_CTL_PAD_GPIO_B1_02
• SW_PAD_CTL_PAD_GPIO_B1_03
• SW_PAD_CTL_PAD_GPIO_B1_04
• SW_PAD_CTL_PAD_GPIO_B1_05
• SW_PAD_CTL_PAD_GPIO_B1_06
• SW_PAD_CTL_PAD_GPIO_B1_07
• SW_PAD_CTL_PAD_GPIO_B1_08
• SW_PAD_CTL_PAD_GPIO_B1_09
• SW_PAD_CTL_PAD_GPIO_B1_10
• SW_PAD_CTL_PAD_GPIO_B1_11
• SW_PAD_CTL_PAD_GPIO_B1_12
• SW_PAD_CTL_PAD_GPIO_B1_13
• SW_PAD_CTL_PAD_GPIO_B1_14
• SW_PAD_CTL_PAD_GPIO_B1_15
• SW_PAD_CTL_PAD_GPIO_EMC_00
• SW_PAD_CTL_PAD_GPIO_EMC_01
• SW_PAD_CTL_PAD_GPIO_EMC_02
• SW_PAD_CTL_PAD_GPIO_EMC_03
• SW_PAD_CTL_PAD_GPIO_EMC_04
• SW_PAD_CTL_PAD_GPIO_EMC_05
• SW_PAD_CTL_PAD_GPIO_EMC_06
• SW_PAD_CTL_PAD_GPIO_EMC_07
• SW_PAD_CTL_PAD_GPIO_EMC_08
• SW_PAD_CTL_PAD_GPIO_EMC_09
• SW_PAD_CTL_PAD_GPIO_EMC_10
• SW_PAD_CTL_PAD_GPIO_EMC_11
• SW_PAD_CTL_PAD_GPIO_EMC_12
• SW_PAD_CTL_PAD_GPIO_EMC_13
• SW_PAD_CTL_PAD_GPIO_EMC_14
• SW_PAD_CTL_PAD_GPIO_EMC_15
• SW_PAD_CTL_PAD_GPIO_EMC_16
• SW_PAD_CTL_PAD_GPIO_EMC_17
• SW_PAD_CTL_PAD_GPIO_EMC_18
• SW_PAD_CTL_PAD_GPIO_EMC_19
• SW_PAD_CTL_PAD_GPIO_EMC_20
• SW_PAD_CTL_PAD_GPIO_EMC_21
• SW_PAD_CTL_PAD_GPIO_EMC_22
• SW_PAD_CTL_PAD_GPIO_EMC_23
• SW_PAD_CTL_PAD_GPIO_EMC_24
• SW_PAD_CTL_PAD_GPIO_EMC_25
• SW_PAD_CTL_PAD_GPIO_EMC_26
• SW_PAD_CTL_PAD_GPIO_EMC_27
• SW_PAD_CTL_PAD_GPIO_EMC_28
• SW_PAD_CTL_PAD_GPIO_EMC_29
• SW_PAD_CTL_PAD_GPIO_EMC_30
• SW_PAD_CTL_PAD_GPIO_EMC_31
• SW_PAD_CTL_PAD_GPIO_EMC_32
• SW_PAD_CTL_PAD_GPIO_EMC_33
• SW_PAD_CTL_PAD_GPIO_EMC_34
• SW_PAD_CTL_PAD_GPIO_EMC_35
• SW_PAD_CTL_PAD_GPIO_EMC_36
• SW_PAD_CTL_PAD_GPIO_EMC_37
• SW_PAD_CTL_PAD_GPIO_EMC_38
• SW_PAD_CTL_PAD_GPIO_EMC_39
• SW_PAD_CTL_PAD_GPIO_EMC_40
• SW_PAD_CTL_PAD_GPIO_EMC_41
• SW_PAD_CTL_PAD_GPIO_SD_B0_00
• SW_PAD_CTL_PAD_GPIO_SD_B0_01
• SW_PAD_CTL_PAD_GPIO_SD_B0_02
• SW_PAD_CTL_PAD_GPIO_SD_B0_03
• SW_PAD_CTL_PAD_GPIO_SD_B0_04
• SW_PAD_CTL_PAD_GPIO_SD_B0_05
• SW_PAD_CTL_PAD_GPIO_SD_B1_00
• SW_PAD_CTL_PAD_GPIO_SD_B1_01
• SW_PAD_CTL_PAD_GPIO_SD_B1_02
• SW_PAD_CTL_PAD_GPIO_SD_B1_03
• SW_PAD_CTL_PAD_GPIO_SD_B1_04
• SW_PAD_CTL_PAD_GPIO_SD_B1_05
• SW_PAD_CTL_PAD_GPIO_SD_B1_06
• SW_PAD_CTL_PAD_GPIO_SD_B1_07
• SW_PAD_CTL_PAD_GPIO_SD_B1_08
• SW_PAD_CTL_PAD_GPIO_SD_B1_09
• SW_PAD_CTL_PAD_GPIO_SD_B1_10
• SW_PAD_CTL_PAD_GPIO_SD_B1_11
• SW_PAD_CTL_PAD_GPIO_SPI_B0_00
• SW_PAD_CTL_PAD_GPIO_SPI_B0_01
• SW_PAD_CTL_PAD_GPIO_SPI_B0_02
• SW_PAD_CTL_PAD_GPIO_SPI_B0_03
• SW_PAD_CTL_PAD_GPIO_SPI_B0_04
• SW_PAD_CTL_PAD_GPIO_SPI_B0_05
• SW_PAD_CTL_PAD_GPIO_SPI_B0_06
• SW_PAD_CTL_PAD_GPIO_SPI_B0_07
• SW_PAD_CTL_PAD_GPIO_SPI_B0_08
• SW_PAD_CTL_PAD_GPIO_SPI_B0_09
• SW_PAD_CTL_PAD_GPIO_SPI_B0_10
• SW_PAD_CTL_PAD_GPIO_SPI_B0_11
• SW_PAD_CTL_PAD_GPIO_SPI_B0_12
• SW_PAD_CTL_PAD_GPIO_SPI_B0_13
• SW_PAD_CTL_PAD_GPIO_SPI_B1_00
• SW_PAD_CTL_PAD_GPIO_SPI_B1_01
• SW_PAD_CTL_PAD_GPIO_SPI_B1_02
• SW_PAD_CTL_PAD_GPIO_SPI_B1_03
• SW_PAD_CTL_PAD_GPIO_SPI_B1_04
• SW_PAD_CTL_PAD_GPIO_SPI_B1_05
• SW_PAD_CTL_PAD_GPIO_SPI_B1_06
• SW_PAD_CTL_PAD_GPIO_SPI_B1_07
• USB_OTG1_OC_SELECT_INPUT
• USB_OTG2_OC_SELECT_INPUT
• USDHC1_CD_B_SELECT_INPUT
• USDHC1_WP_SELECT_INPUT
• USDHC2_CD_B_SELECT_INPUT
• USDHC2_CLK_SELECT_INPUT
• USDHC2_CMD_SELECT_INPUT
• USDHC2_DATA0_SELECT_INPUT
• USDHC2_DATA1_SELECT_INPUT
• USDHC2_DATA2_SELECT_INPUT
• USDHC2_DATA3_SELECT_INPUT
• USDHC2_DATA4_SELECT_INPUT
• USDHC2_DATA5_SELECT_INPUT
• USDHC2_DATA6_SELECT_INPUT
• USDHC2_DATA7_SELECT_INPUT
• USDHC2_WP_SELECT_INPUT
• XBAR1_IN02_SELECT_INPUT
• XBAR1_IN03_SELECT_INPUT
• XBAR1_IN04_SELECT_INPUT
• XBAR1_IN05_SELECT_INPUT
• XBAR1_IN06_SELECT_INPUT
• XBAR1_IN07_SELECT_INPUT
• XBAR1_IN08_SELECT_INPUT
• XBAR1_IN09_SELECT_INPUT
• XBAR1_IN14_SELECT_INPUT
• XBAR1_IN15_SELECT_INPUT
• XBAR1_IN16_SELECT_INPUT
• XBAR1_IN17_SELECT_INPUT
• XBAR1_IN18_SELECT_INPUT
• XBAR1_IN19_SELECT_INPUT
• XBAR1_IN20_SELECT_INPUT
• XBAR1_IN21_SELECT_INPUT
• XBAR1_IN22_SELECT_INPUT
• XBAR1_IN23_SELECT_INPUT
• XBAR1_IN24_SELECT_INPUT
• XBAR1_IN25_SELECT_INPUT
• anatop_usb_otg1_id_select_input::DAISY_R
• anatop_usb_otg1_id_select_input::R
• anatop_usb_otg1_id_select_input::W
• anatop_usb_otg2_id_select_input::DAISY_R
• anatop_usb_otg2_id_select_input::R
• anatop_usb_otg2_id_select_input::W
• canfd_ipp_ind_canrx_select_input::DAISY_R
• canfd_ipp_ind_canrx_select_input::R
• canfd_ipp_ind_canrx_select_input::W
• ccm_pmic_ready_select_input::DAISY_R
• ccm_pmic_ready_select_input::R
• ccm_pmic_ready_select_input::W
• csi_data02_select_input::DAISY_R
• csi_data02_select_input::R
• csi_data02_select_input::W
• csi_data03_select_input::DAISY_R
• csi_data03_select_input::R
• csi_data03_select_input::W
• csi_data04_select_input::DAISY_R
• csi_data04_select_input::R
• csi_data04_select_input::W
• csi_data05_select_input::DAISY_R
• csi_data05_select_input::R
• csi_data05_select_input::W
• csi_data06_select_input::DAISY_R
• csi_data06_select_input::R
• csi_data06_select_input::W
• csi_data07_select_input::DAISY_R
• csi_data07_select_input::R
• csi_data07_select_input::W
• csi_data08_select_input::DAISY_R
• csi_data08_select_input::R
• csi_data08_select_input::W
• csi_data09_select_input::DAISY_R
• csi_data09_select_input::R
• csi_data09_select_input::W
• csi_hsync_select_input::DAISY_R
• csi_hsync_select_input::R
• csi_hsync_select_input::W
• csi_pixclk_select_input::DAISY_R
• csi_pixclk_select_input::R
• csi_pixclk_select_input::W
• csi_vsync_select_input::DAISY_R
• csi_vsync_select_input::R
• csi_vsync_select_input::W
• enet0_rxdata_select_input::DAISY_R
• enet0_rxdata_select_input::R
• enet0_rxdata_select_input::W
• enet0_timer_select_input::DAISY_R
• enet0_timer_select_input::R
• enet0_timer_select_input::W
• enet1_rxdata_select_input::DAISY_R
• enet1_rxdata_select_input::R
• enet1_rxdata_select_input::W
• enet2_ipg_clk_rmii_select_input::DAISY_R
• enet2_ipg_clk_rmii_select_input::R
• enet2_ipg_clk_rmii_select_input::W
• enet2_ipp_ind_mac0_mdio_select_input::DAISY_R
• enet2_ipp_ind_mac0_mdio_select_input::R
• enet2_ipp_ind_mac0_mdio_select_input::W
• enet2_ipp_ind_mac0_rxdata_select_input_0::DAISY_R
• enet2_ipp_ind_mac0_rxdata_select_input_0::R
• enet2_ipp_ind_mac0_rxdata_select_input_0::W
• enet2_ipp_ind_mac0_rxdata_select_input_1::DAISY_R
• enet2_ipp_ind_mac0_rxdata_select_input_1::R
• enet2_ipp_ind_mac0_rxdata_select_input_1::W
• enet2_ipp_ind_mac0_rxen_select_input::DAISY_R
• enet2_ipp_ind_mac0_rxen_select_input::R
• enet2_ipp_ind_mac0_rxen_select_input::W
• enet2_ipp_ind_mac0_rxerr_select_input::DAISY_R
• enet2_ipp_ind_mac0_rxerr_select_input::R
• enet2_ipp_ind_mac0_rxerr_select_input::W
• enet2_ipp_ind_mac0_timer_select_input_0::DAISY_R
• enet2_ipp_ind_mac0_timer_select_input_0::R
• enet2_ipp_ind_mac0_timer_select_input_0::W
• enet2_ipp_ind_mac0_txclk_select_input::DAISY_R
• enet2_ipp_ind_mac0_txclk_select_input::R
• enet2_ipp_ind_mac0_txclk_select_input::W
• enet_ipg_clk_rmii_select_input::DAISY_R
• enet_ipg_clk_rmii_select_input::R
• enet_ipg_clk_rmii_select_input::W
• enet_mdio_select_input::DAISY_R
• enet_mdio_select_input::R
• enet_mdio_select_input::W
• enet_rxen_select_input::DAISY_R
• enet_rxen_select_input::R
• enet_rxen_select_input::W
• enet_rxerr_select_input::DAISY_R
• enet_rxerr_select_input::R
• enet_rxerr_select_input::W
• enet_txclk_select_input::DAISY_R
• enet_txclk_select_input::R
• enet_txclk_select_input::W
• flexcan1_rx_select_input::DAISY_R
• flexcan1_rx_select_input::R
• flexcan1_rx_select_input::W
• flexcan2_rx_select_input::DAISY_R
• flexcan2_rx_select_input::R
• flexcan2_rx_select_input::W
• flexpwm1_pwma0_select_input::DAISY_R
• flexpwm1_pwma0_select_input::R
• flexpwm1_pwma0_select_input::W
• flexpwm1_pwma1_select_input::DAISY_R
• flexpwm1_pwma1_select_input::R
• flexpwm1_pwma1_select_input::W
• flexpwm1_pwma2_select_input::DAISY_R
• flexpwm1_pwma2_select_input::R
• flexpwm1_pwma2_select_input::W
• flexpwm1_pwma3_select_input::DAISY_R
• flexpwm1_pwma3_select_input::R
• flexpwm1_pwma3_select_input::W
• flexpwm1_pwmb0_select_input::DAISY_R
• flexpwm1_pwmb0_select_input::R
• flexpwm1_pwmb0_select_input::W
• flexpwm1_pwmb1_select_input::DAISY_R
• flexpwm1_pwmb1_select_input::R
• flexpwm1_pwmb1_select_input::W
• flexpwm1_pwmb2_select_input::DAISY_R
• flexpwm1_pwmb2_select_input::R
• flexpwm1_pwmb2_select_input::W
• flexpwm1_pwmb3_select_input::DAISY_R
• flexpwm1_pwmb3_select_input::R
• flexpwm1_pwmb3_select_input::W
• flexpwm2_pwma0_select_input::DAISY_R
• flexpwm2_pwma0_select_input::R
• flexpwm2_pwma0_select_input::W
• flexpwm2_pwma1_select_input::DAISY_R
• flexpwm2_pwma1_select_input::R
• flexpwm2_pwma1_select_input::W
• flexpwm2_pwma2_select_input::DAISY_R
• flexpwm2_pwma2_select_input::R
• flexpwm2_pwma2_select_input::W
• flexpwm2_pwma3_select_input::DAISY_R
• flexpwm2_pwma3_select_input::R
• flexpwm2_pwma3_select_input::W
• flexpwm2_pwmb0_select_input::DAISY_R
• flexpwm2_pwmb0_select_input::R
• flexpwm2_pwmb0_select_input::W
• flexpwm2_pwmb1_select_input::DAISY_R
• flexpwm2_pwmb1_select_input::R
• flexpwm2_pwmb1_select_input::W
• flexpwm2_pwmb2_select_input::DAISY_R
• flexpwm2_pwmb2_select_input::R
• flexpwm2_pwmb2_select_input::W
• flexpwm2_pwmb3_select_input::DAISY_R
• flexpwm2_pwmb3_select_input::R
• flexpwm2_pwmb3_select_input::W
• flexpwm4_pwma0_select_input::DAISY_R
• flexpwm4_pwma0_select_input::R
• flexpwm4_pwma0_select_input::W
• flexpwm4_pwma1_select_input::DAISY_R
• flexpwm4_pwma1_select_input::R
• flexpwm4_pwma1_select_input::W
• flexpwm4_pwma2_select_input::DAISY_R
• flexpwm4_pwma2_select_input::R
• flexpwm4_pwma2_select_input::W
• flexpwm4_pwma3_select_input::DAISY_R
• flexpwm4_pwma3_select_input::R
• flexpwm4_pwma3_select_input::W
• flexspi2_ipp_ind_dqs_fa_select_input::DAISY_R
• flexspi2_ipp_ind_dqs_fa_select_input::R
• flexspi2_ipp_ind_dqs_fa_select_input::W
• flexspi2_ipp_ind_io_fa_bit0_select_input::DAISY_R
• flexspi2_ipp_ind_io_fa_bit0_select_input::R
• flexspi2_ipp_ind_io_fa_bit0_select_input::W
• flexspi2_ipp_ind_io_fa_bit1_select_input::DAISY_R
• flexspi2_ipp_ind_io_fa_bit1_select_input::R
• flexspi2_ipp_ind_io_fa_bit1_select_input::W
• flexspi2_ipp_ind_io_fa_bit2_select_input::DAISY_R
• flexspi2_ipp_ind_io_fa_bit2_select_input::R
• flexspi2_ipp_ind_io_fa_bit2_select_input::W
• flexspi2_ipp_ind_io_fa_bit3_select_input::DAISY_R
• flexspi2_ipp_ind_io_fa_bit3_select_input::R
• flexspi2_ipp_ind_io_fa_bit3_select_input::W
• flexspi2_ipp_ind_io_fb_bit0_select_input::DAISY_R
• flexspi2_ipp_ind_io_fb_bit0_select_input::R
• flexspi2_ipp_ind_io_fb_bit0_select_input::W
• flexspi2_ipp_ind_io_fb_bit1_select_input::DAISY_R
• flexspi2_ipp_ind_io_fb_bit1_select_input::R
• flexspi2_ipp_ind_io_fb_bit1_select_input::W
• flexspi2_ipp_ind_io_fb_bit2_select_input::DAISY_R
• flexspi2_ipp_ind_io_fb_bit2_select_input::R
• flexspi2_ipp_ind_io_fb_bit2_select_input::W
• flexspi2_ipp_ind_io_fb_bit3_select_input::DAISY_R
• flexspi2_ipp_ind_io_fb_bit3_select_input::R
• flexspi2_ipp_ind_io_fb_bit3_select_input::W
• flexspi2_ipp_ind_sck_fa_select_input::DAISY_R
• flexspi2_ipp_ind_sck_fa_select_input::R
• flexspi2_ipp_ind_sck_fa_select_input::W
• flexspi2_ipp_ind_sck_fb_select_input::DAISY_R
• flexspi2_ipp_ind_sck_fb_select_input::R
• flexspi2_ipp_ind_sck_fb_select_input::W
• flexspia_data0_select_input::DAISY_R
• flexspia_data0_select_input::R
• flexspia_data0_select_input::W
• flexspia_data1_select_input::DAISY_R
• flexspia_data1_select_input::R
• flexspia_data1_select_input::W
• flexspia_data2_select_input::DAISY_R
• flexspia_data2_select_input::R
• flexspia_data2_select_input::W
• flexspia_data3_select_input::DAISY_R
• flexspia_data3_select_input::R
• flexspia_data3_select_input::W
• flexspia_dqs_select_input::DAISY_R
• flexspia_dqs_select_input::R
• flexspia_dqs_select_input::W
• flexspia_sck_select_input::DAISY_R
• flexspia_sck_select_input::R
• flexspia_sck_select_input::W
• flexspib_data0_select_input::DAISY_R
• flexspib_data0_select_input::R
• flexspib_data0_select_input::W
• flexspib_data1_select_input::DAISY_R
• flexspib_data1_select_input::R
• flexspib_data1_select_input::W
• flexspib_data2_select_input::DAISY_R
• flexspib_data2_select_input::R
• flexspib_data2_select_input::W
• flexspib_data3_select_input::DAISY_R
• flexspib_data3_select_input::R
• flexspib_data3_select_input::W
• gpt1_ipp_ind_capin1_select_input::DAISY_R
• gpt1_ipp_ind_capin1_select_input::R
• gpt1_ipp_ind_capin1_select_input::W
• gpt1_ipp_ind_capin2_select_input::DAISY_R
• gpt1_ipp_ind_capin2_select_input::R
• gpt1_ipp_ind_capin2_select_input::W
• gpt1_ipp_ind_clkin_select_input::DAISY_R
• gpt1_ipp_ind_clkin_select_input::R
• gpt1_ipp_ind_clkin_select_input::W
• gpt2_ipp_ind_capin1_select_input::DAISY_R
• gpt2_ipp_ind_capin1_select_input::R
• gpt2_ipp_ind_capin1_select_input::W
• gpt2_ipp_ind_capin2_select_input::DAISY_R
• gpt2_ipp_ind_capin2_select_input::R
• gpt2_ipp_ind_capin2_select_input::W
• gpt2_ipp_ind_clkin_select_input::DAISY_R
• gpt2_ipp_ind_clkin_select_input::R
• gpt2_ipp_ind_clkin_select_input::W
• lpi2c1_scl_select_input::DAISY_R
• lpi2c1_scl_select_input::R
• lpi2c1_scl_select_input::W
• lpi2c1_sda_select_input::DAISY_R
• lpi2c1_sda_select_input::R
• lpi2c1_sda_select_input::W
• lpi2c2_scl_select_input::DAISY_R
• lpi2c2_scl_select_input::R
• lpi2c2_scl_select_input::W
• lpi2c2_sda_select_input::DAISY_R
• lpi2c2_sda_select_input::R
• lpi2c2_sda_select_input::W
• lpi2c3_scl_select_input::DAISY_R
• lpi2c3_scl_select_input::R
• lpi2c3_scl_select_input::W
• lpi2c3_sda_select_input::DAISY_R
• lpi2c3_sda_select_input::R
• lpi2c3_sda_select_input::W
• lpi2c4_scl_select_input::DAISY_R
• lpi2c4_scl_select_input::R
• lpi2c4_scl_select_input::W
• lpi2c4_sda_select_input::DAISY_R
• lpi2c4_sda_select_input::R
• lpi2c4_sda_select_input::W
• lpspi1_pcs0_select_input::DAISY_R
• lpspi1_pcs0_select_input::R
• lpspi1_pcs0_select_input::W
• lpspi1_sck_select_input::DAISY_R
• lpspi1_sck_select_input::R
• lpspi1_sck_select_input::W
• lpspi1_sdi_select_input::DAISY_R
• lpspi1_sdi_select_input::R
• lpspi1_sdi_select_input::W
• lpspi1_sdo_select_input::DAISY_R
• lpspi1_sdo_select_input::R
• lpspi1_sdo_select_input::W
• lpspi2_pcs0_select_input::DAISY_R
• lpspi2_pcs0_select_input::R
• lpspi2_pcs0_select_input::W
• lpspi2_sck_select_input::DAISY_R
• lpspi2_sck_select_input::R
• lpspi2_sck_select_input::W
• lpspi2_sdi_select_input::DAISY_R
• lpspi2_sdi_select_input::R
• lpspi2_sdi_select_input::W
• lpspi2_sdo_select_input::DAISY_R
• lpspi2_sdo_select_input::R
• lpspi2_sdo_select_input::W
• lpspi3_pcs0_select_input::DAISY_R
• lpspi3_pcs0_select_input::R
• lpspi3_pcs0_select_input::W
• lpspi3_sck_select_input::DAISY_R
• lpspi3_sck_select_input::R
• lpspi3_sck_select_input::W
• lpspi3_sdi_select_input::DAISY_R
• lpspi3_sdi_select_input::R
• lpspi3_sdi_select_input::W
• lpspi3_sdo_select_input::DAISY_R
• lpspi3_sdo_select_input::R
• lpspi3_sdo_select_input::W
• lpspi4_pcs0_select_input::DAISY_R
• lpspi4_pcs0_select_input::R
• lpspi4_pcs0_select_input::W
• lpspi4_sck_select_input::DAISY_R
• lpspi4_sck_select_input::R
• lpspi4_sck_select_input::W
• lpspi4_sdi_select_input::DAISY_R
• lpspi4_sdi_select_input::R
• lpspi4_sdi_select_input::W
• lpspi4_sdo_select_input::DAISY_R
• lpspi4_sdo_select_input::R
• lpspi4_sdo_select_input::W
• lpuart2_rx_select_input::DAISY_R
• lpuart2_rx_select_input::R
• lpuart2_rx_select_input::W
• lpuart2_tx_select_input::DAISY_R
• lpuart2_tx_select_input::R
• lpuart2_tx_select_input::W
• lpuart3_cts_b_select_input::DAISY_R
• lpuart3_cts_b_select_input::R
• lpuart3_cts_b_select_input::W
• lpuart3_rx_select_input::DAISY_R
• lpuart3_rx_select_input::R
• lpuart3_rx_select_input::W
• lpuart3_tx_select_input::DAISY_R
• lpuart3_tx_select_input::R
• lpuart3_tx_select_input::W
• lpuart4_rx_select_input::DAISY_R
• lpuart4_rx_select_input::R
• lpuart4_rx_select_input::W
• lpuart4_tx_select_input::DAISY_R
• lpuart4_tx_select_input::R
• lpuart4_tx_select_input::W
• lpuart5_rx_select_input::DAISY_R
• lpuart5_rx_select_input::R
• lpuart5_rx_select_input::W
• lpuart5_tx_select_input::DAISY_R
• lpuart5_tx_select_input::R
• lpuart5_tx_select_input::W
• lpuart6_rx_select_input::DAISY_R
• lpuart6_rx_select_input::R
• lpuart6_rx_select_input::W
• lpuart6_tx_select_input::DAISY_R
• lpuart6_tx_select_input::R
• lpuart6_tx_select_input::W
• lpuart7_rx_select_input::DAISY_R
• lpuart7_rx_select_input::R
• lpuart7_rx_select_input::W
• lpuart7_tx_select_input::DAISY_R
• lpuart7_tx_select_input::R
• lpuart7_tx_select_input::W
• lpuart8_rx_select_input::DAISY_R
• lpuart8_rx_select_input::R
• lpuart8_rx_select_input::W
• lpuart8_tx_select_input::DAISY_R
• lpuart8_tx_select_input::R
• lpuart8_tx_select_input::W
• nmi_select_input::DAISY_R
• nmi_select_input::R
• nmi_select_input::W
• qtimer2_timer0_select_input::DAISY_R
• qtimer2_timer0_select_input::R
• qtimer2_timer0_select_input::W
• qtimer2_timer1_select_input::DAISY_R
• qtimer2_timer1_select_input::R
• qtimer2_timer1_select_input::W
• qtimer2_timer2_select_input::DAISY_R
• qtimer2_timer2_select_input::R
• qtimer2_timer2_select_input::W
• qtimer2_timer3_select_input::DAISY_R
• qtimer2_timer3_select_input::R
• qtimer2_timer3_select_input::W
• qtimer3_timer0_select_input::DAISY_R
• qtimer3_timer0_select_input::R
• qtimer3_timer0_select_input::W
• qtimer3_timer1_select_input::DAISY_R
• qtimer3_timer1_select_input::R
• qtimer3_timer1_select_input::W
• qtimer3_timer2_select_input::DAISY_R
• qtimer3_timer2_select_input::R
• qtimer3_timer2_select_input::W
• qtimer3_timer3_select_input::DAISY_R
• qtimer3_timer3_select_input::R
• qtimer3_timer3_select_input::W
• sai1_mclk2_select_input::DAISY_R
• sai1_mclk2_select_input::R
• sai1_mclk2_select_input::W
• sai1_rx_bclk_select_input::DAISY_R
• sai1_rx_bclk_select_input::R
• sai1_rx_bclk_select_input::W
• sai1_rx_data0_select_input::DAISY_R
• sai1_rx_data0_select_input::R
• sai1_rx_data0_select_input::W
• sai1_rx_data1_select_input::DAISY_R
• sai1_rx_data1_select_input::R
• sai1_rx_data1_select_input::W
• sai1_rx_data2_select_input::DAISY_R
• sai1_rx_data2_select_input::R
• sai1_rx_data2_select_input::W
• sai1_rx_data3_select_input::DAISY_R
• sai1_rx_data3_select_input::R
• sai1_rx_data3_select_input::W
• sai1_rx_sync_select_input::DAISY_R
• sai1_rx_sync_select_input::R
• sai1_rx_sync_select_input::W
• sai1_tx_bclk_select_input::DAISY_R
• sai1_tx_bclk_select_input::R
• sai1_tx_bclk_select_input::W
• sai1_tx_sync_select_input::DAISY_R
• sai1_tx_sync_select_input::R
• sai1_tx_sync_select_input::W
• sai2_mclk2_select_input::DAISY_R
• sai2_mclk2_select_input::R
• sai2_mclk2_select_input::W
• sai2_rx_bclk_select_input::DAISY_R
• sai2_rx_bclk_select_input::R
• sai2_rx_bclk_select_input::W
• sai2_rx_data0_select_input::DAISY_R
• sai2_rx_data0_select_input::R
• sai2_rx_data0_select_input::W
• sai2_rx_sync_select_input::DAISY_R
• sai2_rx_sync_select_input::R
• sai2_rx_sync_select_input::W
• sai2_tx_bclk_select_input::DAISY_R
• sai2_tx_bclk_select_input::R
• sai2_tx_bclk_select_input::W
• sai2_tx_sync_select_input::DAISY_R
• sai2_tx_sync_select_input::R
• sai2_tx_sync_select_input::W
• sai3_ipg_clk_sai_mclk_select_input_2::DAISY_R
• sai3_ipg_clk_sai_mclk_select_input_2::R
• sai3_ipg_clk_sai_mclk_select_input_2::W
• sai3_ipp_ind_sai_rxbclk_select_input::DAISY_R
• sai3_ipp_ind_sai_rxbclk_select_input::R
• sai3_ipp_ind_sai_rxbclk_select_input::W
• sai3_ipp_ind_sai_rxdata_select_input_0::DAISY_R
• sai3_ipp_ind_sai_rxdata_select_input_0::R
• sai3_ipp_ind_sai_rxdata_select_input_0::W
• sai3_ipp_ind_sai_rxsync_select_input::DAISY_R
• sai3_ipp_ind_sai_rxsync_select_input::R
• sai3_ipp_ind_sai_rxsync_select_input::W
• sai3_ipp_ind_sai_txbclk_select_input::DAISY_R
• sai3_ipp_ind_sai_txbclk_select_input::R
• sai3_ipp_ind_sai_txbclk_select_input::W
• sai3_ipp_ind_sai_txsync_select_input::DAISY_R
• sai3_ipp_ind_sai_txsync_select_input::R
• sai3_ipp_ind_sai_txsync_select_input::W
• semc_i_ipp_ind_dqs4_select_input::DAISY_R
• semc_i_ipp_ind_dqs4_select_input::R
• semc_i_ipp_ind_dqs4_select_input::W
• spdif_in_select_input::DAISY_R
• spdif_in_select_input::R
• spdif_in_select_input::W
• sw_mux_ctl_pad_gpio_ad_b0_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_00::R
• sw_mux_ctl_pad_gpio_ad_b0_00::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_00::W
• sw_mux_ctl_pad_gpio_ad_b0_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_01::R
• sw_mux_ctl_pad_gpio_ad_b0_01::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_01::W
• sw_mux_ctl_pad_gpio_ad_b0_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_02::R
• sw_mux_ctl_pad_gpio_ad_b0_02::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_02::W
• sw_mux_ctl_pad_gpio_ad_b0_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_03::R
• sw_mux_ctl_pad_gpio_ad_b0_03::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_03::W
• sw_mux_ctl_pad_gpio_ad_b0_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_04::R
• sw_mux_ctl_pad_gpio_ad_b0_04::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_04::W
• sw_mux_ctl_pad_gpio_ad_b0_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_05::R
• sw_mux_ctl_pad_gpio_ad_b0_05::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_05::W
• sw_mux_ctl_pad_gpio_ad_b0_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_06::R
• sw_mux_ctl_pad_gpio_ad_b0_06::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_06::W
• sw_mux_ctl_pad_gpio_ad_b0_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_07::R
• sw_mux_ctl_pad_gpio_ad_b0_07::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_07::W
• sw_mux_ctl_pad_gpio_ad_b0_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_08::R
• sw_mux_ctl_pad_gpio_ad_b0_08::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_08::W
• sw_mux_ctl_pad_gpio_ad_b0_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_09::R
• sw_mux_ctl_pad_gpio_ad_b0_09::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_09::W
• sw_mux_ctl_pad_gpio_ad_b0_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_10::R
• sw_mux_ctl_pad_gpio_ad_b0_10::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_10::W
• sw_mux_ctl_pad_gpio_ad_b0_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_11::R
• sw_mux_ctl_pad_gpio_ad_b0_11::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_11::W
• sw_mux_ctl_pad_gpio_ad_b0_12::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_12::R
• sw_mux_ctl_pad_gpio_ad_b0_12::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_12::W
• sw_mux_ctl_pad_gpio_ad_b0_13::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_13::R
• sw_mux_ctl_pad_gpio_ad_b0_13::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_13::W
• sw_mux_ctl_pad_gpio_ad_b0_14::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_14::R
• sw_mux_ctl_pad_gpio_ad_b0_14::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_14::W
• sw_mux_ctl_pad_gpio_ad_b0_15::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b0_15::R
• sw_mux_ctl_pad_gpio_ad_b0_15::SION_R
• sw_mux_ctl_pad_gpio_ad_b0_15::W
• sw_mux_ctl_pad_gpio_ad_b1_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_00::R
• sw_mux_ctl_pad_gpio_ad_b1_00::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_00::W
• sw_mux_ctl_pad_gpio_ad_b1_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_01::R
• sw_mux_ctl_pad_gpio_ad_b1_01::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_01::W
• sw_mux_ctl_pad_gpio_ad_b1_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_02::R
• sw_mux_ctl_pad_gpio_ad_b1_02::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_02::W
• sw_mux_ctl_pad_gpio_ad_b1_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_03::R
• sw_mux_ctl_pad_gpio_ad_b1_03::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_03::W
• sw_mux_ctl_pad_gpio_ad_b1_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_04::R
• sw_mux_ctl_pad_gpio_ad_b1_04::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_04::W
• sw_mux_ctl_pad_gpio_ad_b1_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_05::R
• sw_mux_ctl_pad_gpio_ad_b1_05::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_05::W
• sw_mux_ctl_pad_gpio_ad_b1_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_06::R
• sw_mux_ctl_pad_gpio_ad_b1_06::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_06::W
• sw_mux_ctl_pad_gpio_ad_b1_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_07::R
• sw_mux_ctl_pad_gpio_ad_b1_07::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_07::W
• sw_mux_ctl_pad_gpio_ad_b1_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_08::R
• sw_mux_ctl_pad_gpio_ad_b1_08::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_08::W
• sw_mux_ctl_pad_gpio_ad_b1_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_09::R
• sw_mux_ctl_pad_gpio_ad_b1_09::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_09::W
• sw_mux_ctl_pad_gpio_ad_b1_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_10::R
• sw_mux_ctl_pad_gpio_ad_b1_10::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_10::W
• sw_mux_ctl_pad_gpio_ad_b1_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_11::R
• sw_mux_ctl_pad_gpio_ad_b1_11::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_11::W
• sw_mux_ctl_pad_gpio_ad_b1_12::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_12::R
• sw_mux_ctl_pad_gpio_ad_b1_12::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_12::W
• sw_mux_ctl_pad_gpio_ad_b1_13::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_13::R
• sw_mux_ctl_pad_gpio_ad_b1_13::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_13::W
• sw_mux_ctl_pad_gpio_ad_b1_14::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_14::R
• sw_mux_ctl_pad_gpio_ad_b1_14::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_14::W
• sw_mux_ctl_pad_gpio_ad_b1_15::MUX_MODE_R
• sw_mux_ctl_pad_gpio_ad_b1_15::R
• sw_mux_ctl_pad_gpio_ad_b1_15::SION_R
• sw_mux_ctl_pad_gpio_ad_b1_15::W
• sw_mux_ctl_pad_gpio_b0_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_00::R
• sw_mux_ctl_pad_gpio_b0_00::SION_R
• sw_mux_ctl_pad_gpio_b0_00::W
• sw_mux_ctl_pad_gpio_b0_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_01::R
• sw_mux_ctl_pad_gpio_b0_01::SION_R
• sw_mux_ctl_pad_gpio_b0_01::W
• sw_mux_ctl_pad_gpio_b0_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_02::R
• sw_mux_ctl_pad_gpio_b0_02::SION_R
• sw_mux_ctl_pad_gpio_b0_02::W
• sw_mux_ctl_pad_gpio_b0_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_03::R
• sw_mux_ctl_pad_gpio_b0_03::SION_R
• sw_mux_ctl_pad_gpio_b0_03::W
• sw_mux_ctl_pad_gpio_b0_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_04::R
• sw_mux_ctl_pad_gpio_b0_04::SION_R
• sw_mux_ctl_pad_gpio_b0_04::W
• sw_mux_ctl_pad_gpio_b0_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_05::R
• sw_mux_ctl_pad_gpio_b0_05::SION_R
• sw_mux_ctl_pad_gpio_b0_05::W
• sw_mux_ctl_pad_gpio_b0_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_06::R
• sw_mux_ctl_pad_gpio_b0_06::SION_R
• sw_mux_ctl_pad_gpio_b0_06::W
• sw_mux_ctl_pad_gpio_b0_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_07::R
• sw_mux_ctl_pad_gpio_b0_07::SION_R
• sw_mux_ctl_pad_gpio_b0_07::W
• sw_mux_ctl_pad_gpio_b0_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_08::R
• sw_mux_ctl_pad_gpio_b0_08::SION_R
• sw_mux_ctl_pad_gpio_b0_08::W
• sw_mux_ctl_pad_gpio_b0_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_09::R
• sw_mux_ctl_pad_gpio_b0_09::SION_R
• sw_mux_ctl_pad_gpio_b0_09::W
• sw_mux_ctl_pad_gpio_b0_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_10::R
• sw_mux_ctl_pad_gpio_b0_10::SION_R
• sw_mux_ctl_pad_gpio_b0_10::W
• sw_mux_ctl_pad_gpio_b0_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_11::R
• sw_mux_ctl_pad_gpio_b0_11::SION_R
• sw_mux_ctl_pad_gpio_b0_11::W
• sw_mux_ctl_pad_gpio_b0_12::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_12::R
• sw_mux_ctl_pad_gpio_b0_12::SION_R
• sw_mux_ctl_pad_gpio_b0_12::W
• sw_mux_ctl_pad_gpio_b0_13::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_13::R
• sw_mux_ctl_pad_gpio_b0_13::SION_R
• sw_mux_ctl_pad_gpio_b0_13::W
• sw_mux_ctl_pad_gpio_b0_14::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_14::R
• sw_mux_ctl_pad_gpio_b0_14::SION_R
• sw_mux_ctl_pad_gpio_b0_14::W
• sw_mux_ctl_pad_gpio_b0_15::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b0_15::R
• sw_mux_ctl_pad_gpio_b0_15::SION_R
• sw_mux_ctl_pad_gpio_b0_15::W
• sw_mux_ctl_pad_gpio_b1_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_00::R
• sw_mux_ctl_pad_gpio_b1_00::SION_R
• sw_mux_ctl_pad_gpio_b1_00::W
• sw_mux_ctl_pad_gpio_b1_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_01::R
• sw_mux_ctl_pad_gpio_b1_01::SION_R
• sw_mux_ctl_pad_gpio_b1_01::W
• sw_mux_ctl_pad_gpio_b1_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_02::R
• sw_mux_ctl_pad_gpio_b1_02::SION_R
• sw_mux_ctl_pad_gpio_b1_02::W
• sw_mux_ctl_pad_gpio_b1_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_03::R
• sw_mux_ctl_pad_gpio_b1_03::SION_R
• sw_mux_ctl_pad_gpio_b1_03::W
• sw_mux_ctl_pad_gpio_b1_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_04::R
• sw_mux_ctl_pad_gpio_b1_04::SION_R
• sw_mux_ctl_pad_gpio_b1_04::W
• sw_mux_ctl_pad_gpio_b1_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_05::R
• sw_mux_ctl_pad_gpio_b1_05::SION_R
• sw_mux_ctl_pad_gpio_b1_05::W
• sw_mux_ctl_pad_gpio_b1_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_06::R
• sw_mux_ctl_pad_gpio_b1_06::SION_R
• sw_mux_ctl_pad_gpio_b1_06::W
• sw_mux_ctl_pad_gpio_b1_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_07::R
• sw_mux_ctl_pad_gpio_b1_07::SION_R
• sw_mux_ctl_pad_gpio_b1_07::W
• sw_mux_ctl_pad_gpio_b1_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_08::R
• sw_mux_ctl_pad_gpio_b1_08::SION_R
• sw_mux_ctl_pad_gpio_b1_08::W
• sw_mux_ctl_pad_gpio_b1_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_09::R
• sw_mux_ctl_pad_gpio_b1_09::SION_R
• sw_mux_ctl_pad_gpio_b1_09::W
• sw_mux_ctl_pad_gpio_b1_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_10::R
• sw_mux_ctl_pad_gpio_b1_10::SION_R
• sw_mux_ctl_pad_gpio_b1_10::W
• sw_mux_ctl_pad_gpio_b1_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_11::R
• sw_mux_ctl_pad_gpio_b1_11::SION_R
• sw_mux_ctl_pad_gpio_b1_11::W
• sw_mux_ctl_pad_gpio_b1_12::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_12::R
• sw_mux_ctl_pad_gpio_b1_12::SION_R
• sw_mux_ctl_pad_gpio_b1_12::W
• sw_mux_ctl_pad_gpio_b1_13::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_13::R
• sw_mux_ctl_pad_gpio_b1_13::SION_R
• sw_mux_ctl_pad_gpio_b1_13::W
• sw_mux_ctl_pad_gpio_b1_14::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_14::R
• sw_mux_ctl_pad_gpio_b1_14::SION_R
• sw_mux_ctl_pad_gpio_b1_14::W
• sw_mux_ctl_pad_gpio_b1_15::MUX_MODE_R
• sw_mux_ctl_pad_gpio_b1_15::R
• sw_mux_ctl_pad_gpio_b1_15::SION_R
• sw_mux_ctl_pad_gpio_b1_15::W
• sw_mux_ctl_pad_gpio_emc_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_00::R
• sw_mux_ctl_pad_gpio_emc_00::SION_R
• sw_mux_ctl_pad_gpio_emc_00::W
• sw_mux_ctl_pad_gpio_emc_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_01::R
• sw_mux_ctl_pad_gpio_emc_01::SION_R
• sw_mux_ctl_pad_gpio_emc_01::W
• sw_mux_ctl_pad_gpio_emc_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_02::R
• sw_mux_ctl_pad_gpio_emc_02::SION_R
• sw_mux_ctl_pad_gpio_emc_02::W
• sw_mux_ctl_pad_gpio_emc_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_03::R
• sw_mux_ctl_pad_gpio_emc_03::SION_R
• sw_mux_ctl_pad_gpio_emc_03::W
• sw_mux_ctl_pad_gpio_emc_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_04::R
• sw_mux_ctl_pad_gpio_emc_04::SION_R
• sw_mux_ctl_pad_gpio_emc_04::W
• sw_mux_ctl_pad_gpio_emc_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_05::R
• sw_mux_ctl_pad_gpio_emc_05::SION_R
• sw_mux_ctl_pad_gpio_emc_05::W
• sw_mux_ctl_pad_gpio_emc_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_06::R
• sw_mux_ctl_pad_gpio_emc_06::SION_R
• sw_mux_ctl_pad_gpio_emc_06::W
• sw_mux_ctl_pad_gpio_emc_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_07::R
• sw_mux_ctl_pad_gpio_emc_07::SION_R
• sw_mux_ctl_pad_gpio_emc_07::W
• sw_mux_ctl_pad_gpio_emc_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_08::R
• sw_mux_ctl_pad_gpio_emc_08::SION_R
• sw_mux_ctl_pad_gpio_emc_08::W
• sw_mux_ctl_pad_gpio_emc_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_09::R
• sw_mux_ctl_pad_gpio_emc_09::SION_R
• sw_mux_ctl_pad_gpio_emc_09::W
• sw_mux_ctl_pad_gpio_emc_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_10::R
• sw_mux_ctl_pad_gpio_emc_10::SION_R
• sw_mux_ctl_pad_gpio_emc_10::W
• sw_mux_ctl_pad_gpio_emc_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_11::R
• sw_mux_ctl_pad_gpio_emc_11::SION_R
• sw_mux_ctl_pad_gpio_emc_11::W
• sw_mux_ctl_pad_gpio_emc_12::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_12::R
• sw_mux_ctl_pad_gpio_emc_12::SION_R
• sw_mux_ctl_pad_gpio_emc_12::W
• sw_mux_ctl_pad_gpio_emc_13::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_13::R
• sw_mux_ctl_pad_gpio_emc_13::SION_R
• sw_mux_ctl_pad_gpio_emc_13::W
• sw_mux_ctl_pad_gpio_emc_14::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_14::R
• sw_mux_ctl_pad_gpio_emc_14::SION_R
• sw_mux_ctl_pad_gpio_emc_14::W
• sw_mux_ctl_pad_gpio_emc_15::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_15::R
• sw_mux_ctl_pad_gpio_emc_15::SION_R
• sw_mux_ctl_pad_gpio_emc_15::W
• sw_mux_ctl_pad_gpio_emc_16::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_16::R
• sw_mux_ctl_pad_gpio_emc_16::SION_R
• sw_mux_ctl_pad_gpio_emc_16::W
• sw_mux_ctl_pad_gpio_emc_17::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_17::R
• sw_mux_ctl_pad_gpio_emc_17::SION_R
• sw_mux_ctl_pad_gpio_emc_17::W
• sw_mux_ctl_pad_gpio_emc_18::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_18::R
• sw_mux_ctl_pad_gpio_emc_18::SION_R
• sw_mux_ctl_pad_gpio_emc_18::W
• sw_mux_ctl_pad_gpio_emc_19::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_19::R
• sw_mux_ctl_pad_gpio_emc_19::SION_R
• sw_mux_ctl_pad_gpio_emc_19::W
• sw_mux_ctl_pad_gpio_emc_20::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_20::R
• sw_mux_ctl_pad_gpio_emc_20::SION_R
• sw_mux_ctl_pad_gpio_emc_20::W
• sw_mux_ctl_pad_gpio_emc_21::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_21::R
• sw_mux_ctl_pad_gpio_emc_21::SION_R
• sw_mux_ctl_pad_gpio_emc_21::W
• sw_mux_ctl_pad_gpio_emc_22::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_22::R
• sw_mux_ctl_pad_gpio_emc_22::SION_R
• sw_mux_ctl_pad_gpio_emc_22::W
• sw_mux_ctl_pad_gpio_emc_23::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_23::R
• sw_mux_ctl_pad_gpio_emc_23::SION_R
• sw_mux_ctl_pad_gpio_emc_23::W
• sw_mux_ctl_pad_gpio_emc_24::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_24::R
• sw_mux_ctl_pad_gpio_emc_24::SION_R
• sw_mux_ctl_pad_gpio_emc_24::W
• sw_mux_ctl_pad_gpio_emc_25::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_25::R
• sw_mux_ctl_pad_gpio_emc_25::SION_R
• sw_mux_ctl_pad_gpio_emc_25::W
• sw_mux_ctl_pad_gpio_emc_26::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_26::R
• sw_mux_ctl_pad_gpio_emc_26::SION_R
• sw_mux_ctl_pad_gpio_emc_26::W
• sw_mux_ctl_pad_gpio_emc_27::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_27::R
• sw_mux_ctl_pad_gpio_emc_27::SION_R
• sw_mux_ctl_pad_gpio_emc_27::W
• sw_mux_ctl_pad_gpio_emc_28::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_28::R
• sw_mux_ctl_pad_gpio_emc_28::SION_R
• sw_mux_ctl_pad_gpio_emc_28::W
• sw_mux_ctl_pad_gpio_emc_29::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_29::R
• sw_mux_ctl_pad_gpio_emc_29::SION_R
• sw_mux_ctl_pad_gpio_emc_29::W
• sw_mux_ctl_pad_gpio_emc_30::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_30::R
• sw_mux_ctl_pad_gpio_emc_30::SION_R
• sw_mux_ctl_pad_gpio_emc_30::W
• sw_mux_ctl_pad_gpio_emc_31::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_31::R
• sw_mux_ctl_pad_gpio_emc_31::SION_R
• sw_mux_ctl_pad_gpio_emc_31::W
• sw_mux_ctl_pad_gpio_emc_32::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_32::R
• sw_mux_ctl_pad_gpio_emc_32::SION_R
• sw_mux_ctl_pad_gpio_emc_32::W
• sw_mux_ctl_pad_gpio_emc_33::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_33::R
• sw_mux_ctl_pad_gpio_emc_33::SION_R
• sw_mux_ctl_pad_gpio_emc_33::W
• sw_mux_ctl_pad_gpio_emc_34::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_34::R
• sw_mux_ctl_pad_gpio_emc_34::SION_R
• sw_mux_ctl_pad_gpio_emc_34::W
• sw_mux_ctl_pad_gpio_emc_35::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_35::R
• sw_mux_ctl_pad_gpio_emc_35::SION_R
• sw_mux_ctl_pad_gpio_emc_35::W
• sw_mux_ctl_pad_gpio_emc_36::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_36::R
• sw_mux_ctl_pad_gpio_emc_36::SION_R
• sw_mux_ctl_pad_gpio_emc_36::W
• sw_mux_ctl_pad_gpio_emc_37::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_37::R
• sw_mux_ctl_pad_gpio_emc_37::SION_R
• sw_mux_ctl_pad_gpio_emc_37::W
• sw_mux_ctl_pad_gpio_emc_38::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_38::R
• sw_mux_ctl_pad_gpio_emc_38::SION_R
• sw_mux_ctl_pad_gpio_emc_38::W
• sw_mux_ctl_pad_gpio_emc_39::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_39::R
• sw_mux_ctl_pad_gpio_emc_39::SION_R
• sw_mux_ctl_pad_gpio_emc_39::W
• sw_mux_ctl_pad_gpio_emc_40::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_40::R
• sw_mux_ctl_pad_gpio_emc_40::SION_R
• sw_mux_ctl_pad_gpio_emc_40::W
• sw_mux_ctl_pad_gpio_emc_41::MUX_MODE_R
• sw_mux_ctl_pad_gpio_emc_41::R
• sw_mux_ctl_pad_gpio_emc_41::SION_R
• sw_mux_ctl_pad_gpio_emc_41::W
• sw_mux_ctl_pad_gpio_sd_b0_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b0_00::R
• sw_mux_ctl_pad_gpio_sd_b0_00::SION_R
• sw_mux_ctl_pad_gpio_sd_b0_00::W
• sw_mux_ctl_pad_gpio_sd_b0_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b0_01::R
• sw_mux_ctl_pad_gpio_sd_b0_01::SION_R
• sw_mux_ctl_pad_gpio_sd_b0_01::W
• sw_mux_ctl_pad_gpio_sd_b0_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b0_02::R
• sw_mux_ctl_pad_gpio_sd_b0_02::SION_R
• sw_mux_ctl_pad_gpio_sd_b0_02::W
• sw_mux_ctl_pad_gpio_sd_b0_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b0_03::R
• sw_mux_ctl_pad_gpio_sd_b0_03::SION_R
• sw_mux_ctl_pad_gpio_sd_b0_03::W
• sw_mux_ctl_pad_gpio_sd_b0_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b0_04::R
• sw_mux_ctl_pad_gpio_sd_b0_04::SION_R
• sw_mux_ctl_pad_gpio_sd_b0_04::W
• sw_mux_ctl_pad_gpio_sd_b0_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b0_05::R
• sw_mux_ctl_pad_gpio_sd_b0_05::SION_R
• sw_mux_ctl_pad_gpio_sd_b0_05::W
• sw_mux_ctl_pad_gpio_sd_b1_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_00::R
• sw_mux_ctl_pad_gpio_sd_b1_00::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_00::W
• sw_mux_ctl_pad_gpio_sd_b1_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_01::R
• sw_mux_ctl_pad_gpio_sd_b1_01::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_01::W
• sw_mux_ctl_pad_gpio_sd_b1_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_02::R
• sw_mux_ctl_pad_gpio_sd_b1_02::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_02::W
• sw_mux_ctl_pad_gpio_sd_b1_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_03::R
• sw_mux_ctl_pad_gpio_sd_b1_03::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_03::W
• sw_mux_ctl_pad_gpio_sd_b1_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_04::R
• sw_mux_ctl_pad_gpio_sd_b1_04::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_04::W
• sw_mux_ctl_pad_gpio_sd_b1_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_05::R
• sw_mux_ctl_pad_gpio_sd_b1_05::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_05::W
• sw_mux_ctl_pad_gpio_sd_b1_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_06::R
• sw_mux_ctl_pad_gpio_sd_b1_06::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_06::W
• sw_mux_ctl_pad_gpio_sd_b1_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_07::R
• sw_mux_ctl_pad_gpio_sd_b1_07::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_07::W
• sw_mux_ctl_pad_gpio_sd_b1_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_08::R
• sw_mux_ctl_pad_gpio_sd_b1_08::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_08::W
• sw_mux_ctl_pad_gpio_sd_b1_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_09::R
• sw_mux_ctl_pad_gpio_sd_b1_09::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_09::W
• sw_mux_ctl_pad_gpio_sd_b1_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_10::R
• sw_mux_ctl_pad_gpio_sd_b1_10::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_10::W
• sw_mux_ctl_pad_gpio_sd_b1_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_sd_b1_11::R
• sw_mux_ctl_pad_gpio_sd_b1_11::SION_R
• sw_mux_ctl_pad_gpio_sd_b1_11::W
• sw_mux_ctl_pad_gpio_spi_b0_00::R
• sw_mux_ctl_pad_gpio_spi_b0_00::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_00::W
• sw_mux_ctl_pad_gpio_spi_b0_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_01::R
• sw_mux_ctl_pad_gpio_spi_b0_01::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_01::W
• sw_mux_ctl_pad_gpio_spi_b0_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_02::R
• sw_mux_ctl_pad_gpio_spi_b0_02::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_02::W
• sw_mux_ctl_pad_gpio_spi_b0_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_03::R
• sw_mux_ctl_pad_gpio_spi_b0_03::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_03::W
• sw_mux_ctl_pad_gpio_spi_b0_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_04::R
• sw_mux_ctl_pad_gpio_spi_b0_04::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_04::W
• sw_mux_ctl_pad_gpio_spi_b0_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_05::R
• sw_mux_ctl_pad_gpio_spi_b0_05::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_05::W
• sw_mux_ctl_pad_gpio_spi_b0_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_06::R
• sw_mux_ctl_pad_gpio_spi_b0_06::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_06::W
• sw_mux_ctl_pad_gpio_spi_b0_07::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_07::R
• sw_mux_ctl_pad_gpio_spi_b0_07::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_07::W
• sw_mux_ctl_pad_gpio_spi_b0_08::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_08::R
• sw_mux_ctl_pad_gpio_spi_b0_08::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_08::W
• sw_mux_ctl_pad_gpio_spi_b0_09::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_09::R
• sw_mux_ctl_pad_gpio_spi_b0_09::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_09::W
• sw_mux_ctl_pad_gpio_spi_b0_10::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_10::R
• sw_mux_ctl_pad_gpio_spi_b0_10::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_10::W
• sw_mux_ctl_pad_gpio_spi_b0_11::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_11::R
• sw_mux_ctl_pad_gpio_spi_b0_11::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_11::W
• sw_mux_ctl_pad_gpio_spi_b0_12::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b0_12::R
• sw_mux_ctl_pad_gpio_spi_b0_12::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_12::W
• sw_mux_ctl_pad_gpio_spi_b0_13::R
• sw_mux_ctl_pad_gpio_spi_b0_13::SION_R
• sw_mux_ctl_pad_gpio_spi_b0_13::W
• sw_mux_ctl_pad_gpio_spi_b1_00::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_00::R
• sw_mux_ctl_pad_gpio_spi_b1_00::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_00::W
• sw_mux_ctl_pad_gpio_spi_b1_01::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_01::R
• sw_mux_ctl_pad_gpio_spi_b1_01::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_01::W
• sw_mux_ctl_pad_gpio_spi_b1_02::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_02::R
• sw_mux_ctl_pad_gpio_spi_b1_02::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_02::W
• sw_mux_ctl_pad_gpio_spi_b1_03::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_03::R
• sw_mux_ctl_pad_gpio_spi_b1_03::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_03::W
• sw_mux_ctl_pad_gpio_spi_b1_04::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_04::R
• sw_mux_ctl_pad_gpio_spi_b1_04::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_04::W
• sw_mux_ctl_pad_gpio_spi_b1_05::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_05::R
• sw_mux_ctl_pad_gpio_spi_b1_05::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_05::W
• sw_mux_ctl_pad_gpio_spi_b1_06::MUX_MODE_R
• sw_mux_ctl_pad_gpio_spi_b1_06::R
• sw_mux_ctl_pad_gpio_spi_b1_06::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_06::W
• sw_mux_ctl_pad_gpio_spi_b1_07::R
• sw_mux_ctl_pad_gpio_spi_b1_07::SION_R
• sw_mux_ctl_pad_gpio_spi_b1_07::W
• sw_pad_ctl_pad_gpio_ad_b0_00::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_00::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_00::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_00::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_00::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_00::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_00::R
• sw_pad_ctl_pad_gpio_ad_b0_00::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_00::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_00::W
• sw_pad_ctl_pad_gpio_ad_b0_01::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_01::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_01::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_01::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_01::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_01::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_01::R
• sw_pad_ctl_pad_gpio_ad_b0_01::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_01::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_01::W
• sw_pad_ctl_pad_gpio_ad_b0_02::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_02::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_02::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_02::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_02::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_02::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_02::R
• sw_pad_ctl_pad_gpio_ad_b0_02::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_02::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_02::W
• sw_pad_ctl_pad_gpio_ad_b0_03::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_03::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_03::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_03::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_03::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_03::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_03::R
• sw_pad_ctl_pad_gpio_ad_b0_03::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_03::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_03::W
• sw_pad_ctl_pad_gpio_ad_b0_04::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_04::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_04::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_04::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_04::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_04::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_04::R
• sw_pad_ctl_pad_gpio_ad_b0_04::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_04::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_04::W
• sw_pad_ctl_pad_gpio_ad_b0_05::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_05::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_05::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_05::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_05::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_05::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_05::R
• sw_pad_ctl_pad_gpio_ad_b0_05::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_05::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_05::W
• sw_pad_ctl_pad_gpio_ad_b0_06::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_06::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_06::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_06::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_06::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_06::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_06::R
• sw_pad_ctl_pad_gpio_ad_b0_06::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_06::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_06::W
• sw_pad_ctl_pad_gpio_ad_b0_07::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_07::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_07::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_07::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_07::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_07::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_07::R
• sw_pad_ctl_pad_gpio_ad_b0_07::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_07::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_07::W
• sw_pad_ctl_pad_gpio_ad_b0_08::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_08::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_08::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_08::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_08::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_08::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_08::R
• sw_pad_ctl_pad_gpio_ad_b0_08::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_08::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_08::W
• sw_pad_ctl_pad_gpio_ad_b0_09::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_09::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_09::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_09::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_09::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_09::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_09::R
• sw_pad_ctl_pad_gpio_ad_b0_09::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_09::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_09::W
• sw_pad_ctl_pad_gpio_ad_b0_10::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_10::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_10::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_10::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_10::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_10::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_10::R
• sw_pad_ctl_pad_gpio_ad_b0_10::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_10::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_10::W
• sw_pad_ctl_pad_gpio_ad_b0_11::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_11::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_11::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_11::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_11::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_11::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_11::R
• sw_pad_ctl_pad_gpio_ad_b0_11::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_11::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_11::W
• sw_pad_ctl_pad_gpio_ad_b0_12::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_12::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_12::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_12::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_12::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_12::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_12::R
• sw_pad_ctl_pad_gpio_ad_b0_12::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_12::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_12::W
• sw_pad_ctl_pad_gpio_ad_b0_13::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_13::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_13::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_13::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_13::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_13::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_13::R
• sw_pad_ctl_pad_gpio_ad_b0_13::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_13::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_13::W
• sw_pad_ctl_pad_gpio_ad_b0_14::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_14::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_14::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_14::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_14::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_14::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_14::R
• sw_pad_ctl_pad_gpio_ad_b0_14::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_14::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_14::W
• sw_pad_ctl_pad_gpio_ad_b0_15::DSE_R
• sw_pad_ctl_pad_gpio_ad_b0_15::HYS_R
• sw_pad_ctl_pad_gpio_ad_b0_15::ODE_R
• sw_pad_ctl_pad_gpio_ad_b0_15::PKE_R
• sw_pad_ctl_pad_gpio_ad_b0_15::PUE_R
• sw_pad_ctl_pad_gpio_ad_b0_15::PUS_R
• sw_pad_ctl_pad_gpio_ad_b0_15::R
• sw_pad_ctl_pad_gpio_ad_b0_15::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b0_15::SRE_R
• sw_pad_ctl_pad_gpio_ad_b0_15::W
• sw_pad_ctl_pad_gpio_ad_b1_00::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_00::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_00::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_00::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_00::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_00::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_00::R
• sw_pad_ctl_pad_gpio_ad_b1_00::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_00::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_00::W
• sw_pad_ctl_pad_gpio_ad_b1_01::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_01::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_01::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_01::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_01::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_01::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_01::R
• sw_pad_ctl_pad_gpio_ad_b1_01::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_01::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_01::W
• sw_pad_ctl_pad_gpio_ad_b1_02::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_02::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_02::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_02::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_02::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_02::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_02::R
• sw_pad_ctl_pad_gpio_ad_b1_02::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_02::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_02::W
• sw_pad_ctl_pad_gpio_ad_b1_03::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_03::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_03::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_03::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_03::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_03::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_03::R
• sw_pad_ctl_pad_gpio_ad_b1_03::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_03::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_03::W
• sw_pad_ctl_pad_gpio_ad_b1_04::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_04::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_04::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_04::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_04::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_04::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_04::R
• sw_pad_ctl_pad_gpio_ad_b1_04::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_04::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_04::W
• sw_pad_ctl_pad_gpio_ad_b1_05::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_05::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_05::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_05::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_05::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_05::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_05::R
• sw_pad_ctl_pad_gpio_ad_b1_05::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_05::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_05::W
• sw_pad_ctl_pad_gpio_ad_b1_06::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_06::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_06::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_06::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_06::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_06::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_06::R
• sw_pad_ctl_pad_gpio_ad_b1_06::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_06::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_06::W
• sw_pad_ctl_pad_gpio_ad_b1_07::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_07::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_07::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_07::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_07::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_07::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_07::R
• sw_pad_ctl_pad_gpio_ad_b1_07::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_07::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_07::W
• sw_pad_ctl_pad_gpio_ad_b1_08::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_08::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_08::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_08::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_08::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_08::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_08::R
• sw_pad_ctl_pad_gpio_ad_b1_08::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_08::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_08::W
• sw_pad_ctl_pad_gpio_ad_b1_09::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_09::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_09::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_09::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_09::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_09::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_09::R
• sw_pad_ctl_pad_gpio_ad_b1_09::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_09::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_09::W
• sw_pad_ctl_pad_gpio_ad_b1_10::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_10::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_10::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_10::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_10::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_10::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_10::R
• sw_pad_ctl_pad_gpio_ad_b1_10::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_10::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_10::W
• sw_pad_ctl_pad_gpio_ad_b1_11::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_11::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_11::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_11::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_11::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_11::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_11::R
• sw_pad_ctl_pad_gpio_ad_b1_11::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_11::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_11::W
• sw_pad_ctl_pad_gpio_ad_b1_12::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_12::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_12::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_12::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_12::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_12::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_12::R
• sw_pad_ctl_pad_gpio_ad_b1_12::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_12::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_12::W
• sw_pad_ctl_pad_gpio_ad_b1_13::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_13::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_13::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_13::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_13::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_13::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_13::R
• sw_pad_ctl_pad_gpio_ad_b1_13::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_13::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_13::W
• sw_pad_ctl_pad_gpio_ad_b1_14::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_14::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_14::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_14::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_14::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_14::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_14::R
• sw_pad_ctl_pad_gpio_ad_b1_14::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_14::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_14::W
• sw_pad_ctl_pad_gpio_ad_b1_15::DSE_R
• sw_pad_ctl_pad_gpio_ad_b1_15::HYS_R
• sw_pad_ctl_pad_gpio_ad_b1_15::ODE_R
• sw_pad_ctl_pad_gpio_ad_b1_15::PKE_R
• sw_pad_ctl_pad_gpio_ad_b1_15::PUE_R
• sw_pad_ctl_pad_gpio_ad_b1_15::PUS_R
• sw_pad_ctl_pad_gpio_ad_b1_15::R
• sw_pad_ctl_pad_gpio_ad_b1_15::SPEED_R
• sw_pad_ctl_pad_gpio_ad_b1_15::SRE_R
• sw_pad_ctl_pad_gpio_ad_b1_15::W
• sw_pad_ctl_pad_gpio_b0_00::DSE_R
• sw_pad_ctl_pad_gpio_b0_00::HYS_R
• sw_pad_ctl_pad_gpio_b0_00::ODE_R
• sw_pad_ctl_pad_gpio_b0_00::PKE_R
• sw_pad_ctl_pad_gpio_b0_00::PUE_R
• sw_pad_ctl_pad_gpio_b0_00::PUS_R
• sw_pad_ctl_pad_gpio_b0_00::R
• sw_pad_ctl_pad_gpio_b0_00::SPEED_R
• sw_pad_ctl_pad_gpio_b0_00::SRE_R
• sw_pad_ctl_pad_gpio_b0_00::W
• sw_pad_ctl_pad_gpio_b0_01::DSE_R
• sw_pad_ctl_pad_gpio_b0_01::HYS_R
• sw_pad_ctl_pad_gpio_b0_01::ODE_R
• sw_pad_ctl_pad_gpio_b0_01::PKE_R
• sw_pad_ctl_pad_gpio_b0_01::PUE_R
• sw_pad_ctl_pad_gpio_b0_01::PUS_R
• sw_pad_ctl_pad_gpio_b0_01::R
• sw_pad_ctl_pad_gpio_b0_01::SPEED_R
• sw_pad_ctl_pad_gpio_b0_01::SRE_R
• sw_pad_ctl_pad_gpio_b0_01::W
• sw_pad_ctl_pad_gpio_b0_02::DSE_R
• sw_pad_ctl_pad_gpio_b0_02::HYS_R
• sw_pad_ctl_pad_gpio_b0_02::ODE_R
• sw_pad_ctl_pad_gpio_b0_02::PKE_R
• sw_pad_ctl_pad_gpio_b0_02::PUE_R
• sw_pad_ctl_pad_gpio_b0_02::PUS_R
• sw_pad_ctl_pad_gpio_b0_02::R
• sw_pad_ctl_pad_gpio_b0_02::SPEED_R
• sw_pad_ctl_pad_gpio_b0_02::SRE_R
• sw_pad_ctl_pad_gpio_b0_02::W
• sw_pad_ctl_pad_gpio_b0_03::DSE_R
• sw_pad_ctl_pad_gpio_b0_03::HYS_R
• sw_pad_ctl_pad_gpio_b0_03::ODE_R
• sw_pad_ctl_pad_gpio_b0_03::PKE_R
• sw_pad_ctl_pad_gpio_b0_03::PUE_R
• sw_pad_ctl_pad_gpio_b0_03::PUS_R
• sw_pad_ctl_pad_gpio_b0_03::R
• sw_pad_ctl_pad_gpio_b0_03::SPEED_R
• sw_pad_ctl_pad_gpio_b0_03::SRE_R
• sw_pad_ctl_pad_gpio_b0_03::W
• sw_pad_ctl_pad_gpio_b0_04::DSE_R
• sw_pad_ctl_pad_gpio_b0_04::HYS_R
• sw_pad_ctl_pad_gpio_b0_04::ODE_R
• sw_pad_ctl_pad_gpio_b0_04::PKE_R
• sw_pad_ctl_pad_gpio_b0_04::PUE_R
• sw_pad_ctl_pad_gpio_b0_04::PUS_R
• sw_pad_ctl_pad_gpio_b0_04::R
• sw_pad_ctl_pad_gpio_b0_04::SPEED_R
• sw_pad_ctl_pad_gpio_b0_04::SRE_R
• sw_pad_ctl_pad_gpio_b0_04::W
• sw_pad_ctl_pad_gpio_b0_05::DSE_R
• sw_pad_ctl_pad_gpio_b0_05::HYS_R
• sw_pad_ctl_pad_gpio_b0_05::ODE_R
• sw_pad_ctl_pad_gpio_b0_05::PKE_R
• sw_pad_ctl_pad_gpio_b0_05::PUE_R
• sw_pad_ctl_pad_gpio_b0_05::PUS_R
• sw_pad_ctl_pad_gpio_b0_05::R
• sw_pad_ctl_pad_gpio_b0_05::SPEED_R
• sw_pad_ctl_pad_gpio_b0_05::SRE_R
• sw_pad_ctl_pad_gpio_b0_05::W
• sw_pad_ctl_pad_gpio_b0_06::DSE_R
• sw_pad_ctl_pad_gpio_b0_06::HYS_R
• sw_pad_ctl_pad_gpio_b0_06::ODE_R
• sw_pad_ctl_pad_gpio_b0_06::PKE_R
• sw_pad_ctl_pad_gpio_b0_06::PUE_R
• sw_pad_ctl_pad_gpio_b0_06::PUS_R
• sw_pad_ctl_pad_gpio_b0_06::R
• sw_pad_ctl_pad_gpio_b0_06::SPEED_R
• sw_pad_ctl_pad_gpio_b0_06::SRE_R
• sw_pad_ctl_pad_gpio_b0_06::W
• sw_pad_ctl_pad_gpio_b0_07::DSE_R
• sw_pad_ctl_pad_gpio_b0_07::HYS_R
• sw_pad_ctl_pad_gpio_b0_07::ODE_R
• sw_pad_ctl_pad_gpio_b0_07::PKE_R
• sw_pad_ctl_pad_gpio_b0_07::PUE_R
• sw_pad_ctl_pad_gpio_b0_07::PUS_R
• sw_pad_ctl_pad_gpio_b0_07::R
• sw_pad_ctl_pad_gpio_b0_07::SPEED_R
• sw_pad_ctl_pad_gpio_b0_07::SRE_R
• sw_pad_ctl_pad_gpio_b0_07::W
• sw_pad_ctl_pad_gpio_b0_08::DSE_R
• sw_pad_ctl_pad_gpio_b0_08::HYS_R
• sw_pad_ctl_pad_gpio_b0_08::ODE_R
• sw_pad_ctl_pad_gpio_b0_08::PKE_R
• sw_pad_ctl_pad_gpio_b0_08::PUE_R
• sw_pad_ctl_pad_gpio_b0_08::PUS_R
• sw_pad_ctl_pad_gpio_b0_08::R
• sw_pad_ctl_pad_gpio_b0_08::SPEED_R
• sw_pad_ctl_pad_gpio_b0_08::SRE_R
• sw_pad_ctl_pad_gpio_b0_08::W
• sw_pad_ctl_pad_gpio_b0_09::DSE_R
• sw_pad_ctl_pad_gpio_b0_09::HYS_R
• sw_pad_ctl_pad_gpio_b0_09::ODE_R
• sw_pad_ctl_pad_gpio_b0_09::PKE_R
• sw_pad_ctl_pad_gpio_b0_09::PUE_R
• sw_pad_ctl_pad_gpio_b0_09::PUS_R
• sw_pad_ctl_pad_gpio_b0_09::R
• sw_pad_ctl_pad_gpio_b0_09::SPEED_R
• sw_pad_ctl_pad_gpio_b0_09::SRE_R
• sw_pad_ctl_pad_gpio_b0_09::W
• sw_pad_ctl_pad_gpio_b0_10::DSE_R
• sw_pad_ctl_pad_gpio_b0_10::HYS_R
• sw_pad_ctl_pad_gpio_b0_10::ODE_R
• sw_pad_ctl_pad_gpio_b0_10::PKE_R
• sw_pad_ctl_pad_gpio_b0_10::PUE_R
• sw_pad_ctl_pad_gpio_b0_10::PUS_R
• sw_pad_ctl_pad_gpio_b0_10::R
• sw_pad_ctl_pad_gpio_b0_10::SPEED_R
• sw_pad_ctl_pad_gpio_b0_10::SRE_R
• sw_pad_ctl_pad_gpio_b0_10::W
• sw_pad_ctl_pad_gpio_b0_11::DSE_R
• sw_pad_ctl_pad_gpio_b0_11::HYS_R
• sw_pad_ctl_pad_gpio_b0_11::ODE_R
• sw_pad_ctl_pad_gpio_b0_11::PKE_R
• sw_pad_ctl_pad_gpio_b0_11::PUE_R
• sw_pad_ctl_pad_gpio_b0_11::PUS_R
• sw_pad_ctl_pad_gpio_b0_11::R
• sw_pad_ctl_pad_gpio_b0_11::SPEED_R
• sw_pad_ctl_pad_gpio_b0_11::SRE_R
• sw_pad_ctl_pad_gpio_b0_11::W
• sw_pad_ctl_pad_gpio_b0_12::DSE_R
• sw_pad_ctl_pad_gpio_b0_12::HYS_R
• sw_pad_ctl_pad_gpio_b0_12::ODE_R
• sw_pad_ctl_pad_gpio_b0_12::PKE_R
• sw_pad_ctl_pad_gpio_b0_12::PUE_R
• sw_pad_ctl_pad_gpio_b0_12::PUS_R
• sw_pad_ctl_pad_gpio_b0_12::R
• sw_pad_ctl_pad_gpio_b0_12::SPEED_R
• sw_pad_ctl_pad_gpio_b0_12::SRE_R
• sw_pad_ctl_pad_gpio_b0_12::W
• sw_pad_ctl_pad_gpio_b0_13::DSE_R
• sw_pad_ctl_pad_gpio_b0_13::HYS_R
• sw_pad_ctl_pad_gpio_b0_13::ODE_R
• sw_pad_ctl_pad_gpio_b0_13::PKE_R
• sw_pad_ctl_pad_gpio_b0_13::PUE_R
• sw_pad_ctl_pad_gpio_b0_13::PUS_R
• sw_pad_ctl_pad_gpio_b0_13::R
• sw_pad_ctl_pad_gpio_b0_13::SPEED_R
• sw_pad_ctl_pad_gpio_b0_13::SRE_R
• sw_pad_ctl_pad_gpio_b0_13::W
• sw_pad_ctl_pad_gpio_b0_14::DSE_R
• sw_pad_ctl_pad_gpio_b0_14::HYS_R
• sw_pad_ctl_pad_gpio_b0_14::ODE_R
• sw_pad_ctl_pad_gpio_b0_14::PKE_R
• sw_pad_ctl_pad_gpio_b0_14::PUE_R
• sw_pad_ctl_pad_gpio_b0_14::PUS_R
• sw_pad_ctl_pad_gpio_b0_14::R
• sw_pad_ctl_pad_gpio_b0_14::SPEED_R
• sw_pad_ctl_pad_gpio_b0_14::SRE_R
• sw_pad_ctl_pad_gpio_b0_14::W
• sw_pad_ctl_pad_gpio_b0_15::DSE_R
• sw_pad_ctl_pad_gpio_b0_15::HYS_R
• sw_pad_ctl_pad_gpio_b0_15::ODE_R
• sw_pad_ctl_pad_gpio_b0_15::PKE_R
• sw_pad_ctl_pad_gpio_b0_15::PUE_R
• sw_pad_ctl_pad_gpio_b0_15::PUS_R
• sw_pad_ctl_pad_gpio_b0_15::R
• sw_pad_ctl_pad_gpio_b0_15::SPEED_R
• sw_pad_ctl_pad_gpio_b0_15::SRE_R
• sw_pad_ctl_pad_gpio_b0_15::W
• sw_pad_ctl_pad_gpio_b1_00::DSE_R
• sw_pad_ctl_pad_gpio_b1_00::HYS_R
• sw_pad_ctl_pad_gpio_b1_00::ODE_R
• sw_pad_ctl_pad_gpio_b1_00::PKE_R
• sw_pad_ctl_pad_gpio_b1_00::PUE_R
• sw_pad_ctl_pad_gpio_b1_00::PUS_R
• sw_pad_ctl_pad_gpio_b1_00::R
• sw_pad_ctl_pad_gpio_b1_00::SPEED_R
• sw_pad_ctl_pad_gpio_b1_00::SRE_R
• sw_pad_ctl_pad_gpio_b1_00::W
• sw_pad_ctl_pad_gpio_b1_01::DSE_R
• sw_pad_ctl_pad_gpio_b1_01::HYS_R
• sw_pad_ctl_pad_gpio_b1_01::ODE_R
• sw_pad_ctl_pad_gpio_b1_01::PKE_R
• sw_pad_ctl_pad_gpio_b1_01::PUE_R
• sw_pad_ctl_pad_gpio_b1_01::PUS_R
• sw_pad_ctl_pad_gpio_b1_01::R
• sw_pad_ctl_pad_gpio_b1_01::SPEED_R
• sw_pad_ctl_pad_gpio_b1_01::SRE_R
• sw_pad_ctl_pad_gpio_b1_01::W
• sw_pad_ctl_pad_gpio_b1_02::DSE_R
• sw_pad_ctl_pad_gpio_b1_02::HYS_R
• sw_pad_ctl_pad_gpio_b1_02::ODE_R
• sw_pad_ctl_pad_gpio_b1_02::PKE_R
• sw_pad_ctl_pad_gpio_b1_02::PUE_R
• sw_pad_ctl_pad_gpio_b1_02::PUS_R
• sw_pad_ctl_pad_gpio_b1_02::R
• sw_pad_ctl_pad_gpio_b1_02::SPEED_R
• sw_pad_ctl_pad_gpio_b1_02::SRE_R
• sw_pad_ctl_pad_gpio_b1_02::W
• sw_pad_ctl_pad_gpio_b1_03::DSE_R
• sw_pad_ctl_pad_gpio_b1_03::HYS_R
• sw_pad_ctl_pad_gpio_b1_03::ODE_R
• sw_pad_ctl_pad_gpio_b1_03::PKE_R
• sw_pad_ctl_pad_gpio_b1_03::PUE_R
• sw_pad_ctl_pad_gpio_b1_03::PUS_R
• sw_pad_ctl_pad_gpio_b1_03::R
• sw_pad_ctl_pad_gpio_b1_03::SPEED_R
• sw_pad_ctl_pad_gpio_b1_03::SRE_R
• sw_pad_ctl_pad_gpio_b1_03::W
• sw_pad_ctl_pad_gpio_b1_04::DSE_R
• sw_pad_ctl_pad_gpio_b1_04::HYS_R
• sw_pad_ctl_pad_gpio_b1_04::ODE_R
• sw_pad_ctl_pad_gpio_b1_04::PKE_R
• sw_pad_ctl_pad_gpio_b1_04::PUE_R
• sw_pad_ctl_pad_gpio_b1_04::PUS_R
• sw_pad_ctl_pad_gpio_b1_04::R
• sw_pad_ctl_pad_gpio_b1_04::SPEED_R
• sw_pad_ctl_pad_gpio_b1_04::SRE_R
• sw_pad_ctl_pad_gpio_b1_04::W
• sw_pad_ctl_pad_gpio_b1_05::DSE_R
• sw_pad_ctl_pad_gpio_b1_05::HYS_R
• sw_pad_ctl_pad_gpio_b1_05::ODE_R
• sw_pad_ctl_pad_gpio_b1_05::PKE_R
• sw_pad_ctl_pad_gpio_b1_05::PUE_R
• sw_pad_ctl_pad_gpio_b1_05::PUS_R
• sw_pad_ctl_pad_gpio_b1_05::R
• sw_pad_ctl_pad_gpio_b1_05::SPEED_R
• sw_pad_ctl_pad_gpio_b1_05::SRE_R
• sw_pad_ctl_pad_gpio_b1_05::W
• sw_pad_ctl_pad_gpio_b1_06::DSE_R
• sw_pad_ctl_pad_gpio_b1_06::HYS_R
• sw_pad_ctl_pad_gpio_b1_06::ODE_R
• sw_pad_ctl_pad_gpio_b1_06::PKE_R
• sw_pad_ctl_pad_gpio_b1_06::PUE_R
• sw_pad_ctl_pad_gpio_b1_06::PUS_R
• sw_pad_ctl_pad_gpio_b1_06::R
• sw_pad_ctl_pad_gpio_b1_06::SPEED_R
• sw_pad_ctl_pad_gpio_b1_06::SRE_R
• sw_pad_ctl_pad_gpio_b1_06::W
• sw_pad_ctl_pad_gpio_b1_07::DSE_R
• sw_pad_ctl_pad_gpio_b1_07::HYS_R
• sw_pad_ctl_pad_gpio_b1_07::ODE_R
• sw_pad_ctl_pad_gpio_b1_07::PKE_R
• sw_pad_ctl_pad_gpio_b1_07::PUE_R
• sw_pad_ctl_pad_gpio_b1_07::PUS_R
• sw_pad_ctl_pad_gpio_b1_07::R
• sw_pad_ctl_pad_gpio_b1_07::SPEED_R
• sw_pad_ctl_pad_gpio_b1_07::SRE_R
• sw_pad_ctl_pad_gpio_b1_07::W
• sw_pad_ctl_pad_gpio_b1_08::DSE_R
• sw_pad_ctl_pad_gpio_b1_08::HYS_R
• sw_pad_ctl_pad_gpio_b1_08::ODE_R
• sw_pad_ctl_pad_gpio_b1_08::PKE_R
• sw_pad_ctl_pad_gpio_b1_08::PUE_R
• sw_pad_ctl_pad_gpio_b1_08::PUS_R
• sw_pad_ctl_pad_gpio_b1_08::R
• sw_pad_ctl_pad_gpio_b1_08::SPEED_R
• sw_pad_ctl_pad_gpio_b1_08::SRE_R
• sw_pad_ctl_pad_gpio_b1_08::W
• sw_pad_ctl_pad_gpio_b1_09::DSE_R
• sw_pad_ctl_pad_gpio_b1_09::HYS_R
• sw_pad_ctl_pad_gpio_b1_09::ODE_R
• sw_pad_ctl_pad_gpio_b1_09::PKE_R
• sw_pad_ctl_pad_gpio_b1_09::PUE_R
• sw_pad_ctl_pad_gpio_b1_09::PUS_R
• sw_pad_ctl_pad_gpio_b1_09::R
• sw_pad_ctl_pad_gpio_b1_09::SPEED_R
• sw_pad_ctl_pad_gpio_b1_09::SRE_R
• sw_pad_ctl_pad_gpio_b1_09::W
• sw_pad_ctl_pad_gpio_b1_10::DSE_R
• sw_pad_ctl_pad_gpio_b1_10::HYS_R
• sw_pad_ctl_pad_gpio_b1_10::ODE_R
• sw_pad_ctl_pad_gpio_b1_10::PKE_R
• sw_pad_ctl_pad_gpio_b1_10::PUE_R
• sw_pad_ctl_pad_gpio_b1_10::PUS_R
• sw_pad_ctl_pad_gpio_b1_10::R
• sw_pad_ctl_pad_gpio_b1_10::SPEED_R
• sw_pad_ctl_pad_gpio_b1_10::SRE_R
• sw_pad_ctl_pad_gpio_b1_10::W
• sw_pad_ctl_pad_gpio_b1_11::DSE_R
• sw_pad_ctl_pad_gpio_b1_11::HYS_R
• sw_pad_ctl_pad_gpio_b1_11::ODE_R
• sw_pad_ctl_pad_gpio_b1_11::PKE_R
• sw_pad_ctl_pad_gpio_b1_11::PUE_R
• sw_pad_ctl_pad_gpio_b1_11::PUS_R
• sw_pad_ctl_pad_gpio_b1_11::R
• sw_pad_ctl_pad_gpio_b1_11::SPEED_R
• sw_pad_ctl_pad_gpio_b1_11::SRE_R
• sw_pad_ctl_pad_gpio_b1_11::W
• sw_pad_ctl_pad_gpio_b1_12::DSE_R
• sw_pad_ctl_pad_gpio_b1_12::HYS_R
• sw_pad_ctl_pad_gpio_b1_12::ODE_R
• sw_pad_ctl_pad_gpio_b1_12::PKE_R
• sw_pad_ctl_pad_gpio_b1_12::PUE_R
• sw_pad_ctl_pad_gpio_b1_12::PUS_R
• sw_pad_ctl_pad_gpio_b1_12::R
• sw_pad_ctl_pad_gpio_b1_12::SPEED_R
• sw_pad_ctl_pad_gpio_b1_12::SRE_R
• sw_pad_ctl_pad_gpio_b1_12::W
• sw_pad_ctl_pad_gpio_b1_13::DSE_R
• sw_pad_ctl_pad_gpio_b1_13::HYS_R
• sw_pad_ctl_pad_gpio_b1_13::ODE_R
• sw_pad_ctl_pad_gpio_b1_13::PKE_R
• sw_pad_ctl_pad_gpio_b1_13::PUE_R
• sw_pad_ctl_pad_gpio_b1_13::PUS_R
• sw_pad_ctl_pad_gpio_b1_13::R
• sw_pad_ctl_pad_gpio_b1_13::SPEED_R
• sw_pad_ctl_pad_gpio_b1_13::SRE_R
• sw_pad_ctl_pad_gpio_b1_13::W
• sw_pad_ctl_pad_gpio_b1_14::DSE_R
• sw_pad_ctl_pad_gpio_b1_14::HYS_R
• sw_pad_ctl_pad_gpio_b1_14::ODE_R
• sw_pad_ctl_pad_gpio_b1_14::PKE_R
• sw_pad_ctl_pad_gpio_b1_14::PUE_R
• sw_pad_ctl_pad_gpio_b1_14::PUS_R
• sw_pad_ctl_pad_gpio_b1_14::R
• sw_pad_ctl_pad_gpio_b1_14::SPEED_R
• sw_pad_ctl_pad_gpio_b1_14::SRE_R
• sw_pad_ctl_pad_gpio_b1_14::W
• sw_pad_ctl_pad_gpio_b1_15::DSE_R
• sw_pad_ctl_pad_gpio_b1_15::HYS_R
• sw_pad_ctl_pad_gpio_b1_15::ODE_R
• sw_pad_ctl_pad_gpio_b1_15::PKE_R
• sw_pad_ctl_pad_gpio_b1_15::PUE_R
• sw_pad_ctl_pad_gpio_b1_15::PUS_R
• sw_pad_ctl_pad_gpio_b1_15::R
• sw_pad_ctl_pad_gpio_b1_15::SPEED_R
• sw_pad_ctl_pad_gpio_b1_15::SRE_R
• sw_pad_ctl_pad_gpio_b1_15::W
• sw_pad_ctl_pad_gpio_emc_00::DSE_R
• sw_pad_ctl_pad_gpio_emc_00::HYS_R
• sw_pad_ctl_pad_gpio_emc_00::ODE_R
• sw_pad_ctl_pad_gpio_emc_00::PKE_R
• sw_pad_ctl_pad_gpio_emc_00::PUE_R
• sw_pad_ctl_pad_gpio_emc_00::PUS_R
• sw_pad_ctl_pad_gpio_emc_00::R
• sw_pad_ctl_pad_gpio_emc_00::SPEED_R
• sw_pad_ctl_pad_gpio_emc_00::SRE_R
• sw_pad_ctl_pad_gpio_emc_00::W
• sw_pad_ctl_pad_gpio_emc_01::DSE_R
• sw_pad_ctl_pad_gpio_emc_01::HYS_R
• sw_pad_ctl_pad_gpio_emc_01::ODE_R
• sw_pad_ctl_pad_gpio_emc_01::PKE_R
• sw_pad_ctl_pad_gpio_emc_01::PUE_R
• sw_pad_ctl_pad_gpio_emc_01::PUS_R
• sw_pad_ctl_pad_gpio_emc_01::R
• sw_pad_ctl_pad_gpio_emc_01::SPEED_R
• sw_pad_ctl_pad_gpio_emc_01::SRE_R
• sw_pad_ctl_pad_gpio_emc_01::W
• sw_pad_ctl_pad_gpio_emc_02::DSE_R
• sw_pad_ctl_pad_gpio_emc_02::HYS_R
• sw_pad_ctl_pad_gpio_emc_02::ODE_R
• sw_pad_ctl_pad_gpio_emc_02::PKE_R
• sw_pad_ctl_pad_gpio_emc_02::PUE_R
• sw_pad_ctl_pad_gpio_emc_02::PUS_R
• sw_pad_ctl_pad_gpio_emc_02::R
• sw_pad_ctl_pad_gpio_emc_02::SPEED_R
• sw_pad_ctl_pad_gpio_emc_02::SRE_R
• sw_pad_ctl_pad_gpio_emc_02::W
• sw_pad_ctl_pad_gpio_emc_03::DSE_R
• sw_pad_ctl_pad_gpio_emc_03::HYS_R
• sw_pad_ctl_pad_gpio_emc_03::ODE_R
• sw_pad_ctl_pad_gpio_emc_03::PKE_R
• sw_pad_ctl_pad_gpio_emc_03::PUE_R
• sw_pad_ctl_pad_gpio_emc_03::PUS_R
• sw_pad_ctl_pad_gpio_emc_03::R
• sw_pad_ctl_pad_gpio_emc_03::SPEED_R
• sw_pad_ctl_pad_gpio_emc_03::SRE_R
• sw_pad_ctl_pad_gpio_emc_03::W
• sw_pad_ctl_pad_gpio_emc_04::DSE_R
• sw_pad_ctl_pad_gpio_emc_04::HYS_R
• sw_pad_ctl_pad_gpio_emc_04::ODE_R
• sw_pad_ctl_pad_gpio_emc_04::PKE_R
• sw_pad_ctl_pad_gpio_emc_04::PUE_R
• sw_pad_ctl_pad_gpio_emc_04::PUS_R
• sw_pad_ctl_pad_gpio_emc_04::R
• sw_pad_ctl_pad_gpio_emc_04::SPEED_R
• sw_pad_ctl_pad_gpio_emc_04::SRE_R
• sw_pad_ctl_pad_gpio_emc_04::W
• sw_pad_ctl_pad_gpio_emc_05::DSE_R
• sw_pad_ctl_pad_gpio_emc_05::HYS_R
• sw_pad_ctl_pad_gpio_emc_05::ODE_R
• sw_pad_ctl_pad_gpio_emc_05::PKE_R
• sw_pad_ctl_pad_gpio_emc_05::PUE_R
• sw_pad_ctl_pad_gpio_emc_05::PUS_R
• sw_pad_ctl_pad_gpio_emc_05::R
• sw_pad_ctl_pad_gpio_emc_05::SPEED_R
• sw_pad_ctl_pad_gpio_emc_05::SRE_R
• sw_pad_ctl_pad_gpio_emc_05::W
• sw_pad_ctl_pad_gpio_emc_06::DSE_R
• sw_pad_ctl_pad_gpio_emc_06::HYS_R
• sw_pad_ctl_pad_gpio_emc_06::ODE_R
• sw_pad_ctl_pad_gpio_emc_06::PKE_R
• sw_pad_ctl_pad_gpio_emc_06::PUE_R
• sw_pad_ctl_pad_gpio_emc_06::PUS_R
• sw_pad_ctl_pad_gpio_emc_06::R
• sw_pad_ctl_pad_gpio_emc_06::SPEED_R
• sw_pad_ctl_pad_gpio_emc_06::SRE_R
• sw_pad_ctl_pad_gpio_emc_06::W
• sw_pad_ctl_pad_gpio_emc_07::DSE_R
• sw_pad_ctl_pad_gpio_emc_07::HYS_R
• sw_pad_ctl_pad_gpio_emc_07::ODE_R
• sw_pad_ctl_pad_gpio_emc_07::PKE_R
• sw_pad_ctl_pad_gpio_emc_07::PUE_R
• sw_pad_ctl_pad_gpio_emc_07::PUS_R
• sw_pad_ctl_pad_gpio_emc_07::R
• sw_pad_ctl_pad_gpio_emc_07::SPEED_R
• sw_pad_ctl_pad_gpio_emc_07::SRE_R
• sw_pad_ctl_pad_gpio_emc_07::W
• sw_pad_ctl_pad_gpio_emc_08::DSE_R
• sw_pad_ctl_pad_gpio_emc_08::HYS_R
• sw_pad_ctl_pad_gpio_emc_08::ODE_R
• sw_pad_ctl_pad_gpio_emc_08::PKE_R
• sw_pad_ctl_pad_gpio_emc_08::PUE_R
• sw_pad_ctl_pad_gpio_emc_08::PUS_R
• sw_pad_ctl_pad_gpio_emc_08::R
• sw_pad_ctl_pad_gpio_emc_08::SPEED_R
• sw_pad_ctl_pad_gpio_emc_08::SRE_R
• sw_pad_ctl_pad_gpio_emc_08::W
• sw_pad_ctl_pad_gpio_emc_09::DSE_R
• sw_pad_ctl_pad_gpio_emc_09::HYS_R
• sw_pad_ctl_pad_gpio_emc_09::ODE_R
• sw_pad_ctl_pad_gpio_emc_09::PKE_R
• sw_pad_ctl_pad_gpio_emc_09::PUE_R
• sw_pad_ctl_pad_gpio_emc_09::PUS_R
• sw_pad_ctl_pad_gpio_emc_09::R
• sw_pad_ctl_pad_gpio_emc_09::SPEED_R
• sw_pad_ctl_pad_gpio_emc_09::SRE_R
• sw_pad_ctl_pad_gpio_emc_09::W
• sw_pad_ctl_pad_gpio_emc_10::DSE_R
• sw_pad_ctl_pad_gpio_emc_10::HYS_R
• sw_pad_ctl_pad_gpio_emc_10::ODE_R
• sw_pad_ctl_pad_gpio_emc_10::PKE_R
• sw_pad_ctl_pad_gpio_emc_10::PUE_R
• sw_pad_ctl_pad_gpio_emc_10::PUS_R
• sw_pad_ctl_pad_gpio_emc_10::R
• sw_pad_ctl_pad_gpio_emc_10::SPEED_R
• sw_pad_ctl_pad_gpio_emc_10::SRE_R
• sw_pad_ctl_pad_gpio_emc_10::W
• sw_pad_ctl_pad_gpio_emc_11::DSE_R
• sw_pad_ctl_pad_gpio_emc_11::HYS_R
• sw_pad_ctl_pad_gpio_emc_11::ODE_R
• sw_pad_ctl_pad_gpio_emc_11::PKE_R
• sw_pad_ctl_pad_gpio_emc_11::PUE_R
• sw_pad_ctl_pad_gpio_emc_11::PUS_R
• sw_pad_ctl_pad_gpio_emc_11::R
• sw_pad_ctl_pad_gpio_emc_11::SPEED_R
• sw_pad_ctl_pad_gpio_emc_11::SRE_R
• sw_pad_ctl_pad_gpio_emc_11::W
• sw_pad_ctl_pad_gpio_emc_12::DSE_R
• sw_pad_ctl_pad_gpio_emc_12::HYS_R
• sw_pad_ctl_pad_gpio_emc_12::ODE_R
• sw_pad_ctl_pad_gpio_emc_12::PKE_R
• sw_pad_ctl_pad_gpio_emc_12::PUE_R
• sw_pad_ctl_pad_gpio_emc_12::PUS_R
• sw_pad_ctl_pad_gpio_emc_12::R
• sw_pad_ctl_pad_gpio_emc_12::SPEED_R
• sw_pad_ctl_pad_gpio_emc_12::SRE_R
• sw_pad_ctl_pad_gpio_emc_12::W
• sw_pad_ctl_pad_gpio_emc_13::DSE_R
• sw_pad_ctl_pad_gpio_emc_13::HYS_R
• sw_pad_ctl_pad_gpio_emc_13::ODE_R
• sw_pad_ctl_pad_gpio_emc_13::PKE_R
• sw_pad_ctl_pad_gpio_emc_13::PUE_R
• sw_pad_ctl_pad_gpio_emc_13::PUS_R
• sw_pad_ctl_pad_gpio_emc_13::R
• sw_pad_ctl_pad_gpio_emc_13::SPEED_R
• sw_pad_ctl_pad_gpio_emc_13::SRE_R
• sw_pad_ctl_pad_gpio_emc_13::W
• sw_pad_ctl_pad_gpio_emc_14::DSE_R
• sw_pad_ctl_pad_gpio_emc_14::HYS_R
• sw_pad_ctl_pad_gpio_emc_14::ODE_R
• sw_pad_ctl_pad_gpio_emc_14::PKE_R
• sw_pad_ctl_pad_gpio_emc_14::PUE_R
• sw_pad_ctl_pad_gpio_emc_14::PUS_R
• sw_pad_ctl_pad_gpio_emc_14::R
• sw_pad_ctl_pad_gpio_emc_14::SPEED_R
• sw_pad_ctl_pad_gpio_emc_14::SRE_R
• sw_pad_ctl_pad_gpio_emc_14::W
• sw_pad_ctl_pad_gpio_emc_15::DSE_R
• sw_pad_ctl_pad_gpio_emc_15::HYS_R
• sw_pad_ctl_pad_gpio_emc_15::ODE_R
• sw_pad_ctl_pad_gpio_emc_15::PKE_R
• sw_pad_ctl_pad_gpio_emc_15::PUE_R
• sw_pad_ctl_pad_gpio_emc_15::PUS_R
• sw_pad_ctl_pad_gpio_emc_15::R
• sw_pad_ctl_pad_gpio_emc_15::SPEED_R
• sw_pad_ctl_pad_gpio_emc_15::SRE_R
• sw_pad_ctl_pad_gpio_emc_15::W
• sw_pad_ctl_pad_gpio_emc_16::DSE_R
• sw_pad_ctl_pad_gpio_emc_16::HYS_R
• sw_pad_ctl_pad_gpio_emc_16::ODE_R
• sw_pad_ctl_pad_gpio_emc_16::PKE_R
• sw_pad_ctl_pad_gpio_emc_16::PUE_R
• sw_pad_ctl_pad_gpio_emc_16::PUS_R
• sw_pad_ctl_pad_gpio_emc_16::R
• sw_pad_ctl_pad_gpio_emc_16::SPEED_R
• sw_pad_ctl_pad_gpio_emc_16::SRE_R
• sw_pad_ctl_pad_gpio_emc_16::W
• sw_pad_ctl_pad_gpio_emc_17::DSE_R
• sw_pad_ctl_pad_gpio_emc_17::HYS_R
• sw_pad_ctl_pad_gpio_emc_17::ODE_R
• sw_pad_ctl_pad_gpio_emc_17::PKE_R
• sw_pad_ctl_pad_gpio_emc_17::PUE_R
• sw_pad_ctl_pad_gpio_emc_17::PUS_R
• sw_pad_ctl_pad_gpio_emc_17::R
• sw_pad_ctl_pad_gpio_emc_17::SPEED_R
• sw_pad_ctl_pad_gpio_emc_17::SRE_R
• sw_pad_ctl_pad_gpio_emc_17::W
• sw_pad_ctl_pad_gpio_emc_18::DSE_R
• sw_pad_ctl_pad_gpio_emc_18::HYS_R
• sw_pad_ctl_pad_gpio_emc_18::ODE_R
• sw_pad_ctl_pad_gpio_emc_18::PKE_R
• sw_pad_ctl_pad_gpio_emc_18::PUE_R
• sw_pad_ctl_pad_gpio_emc_18::PUS_R
• sw_pad_ctl_pad_gpio_emc_18::R
• sw_pad_ctl_pad_gpio_emc_18::SPEED_R
• sw_pad_ctl_pad_gpio_emc_18::SRE_R
• sw_pad_ctl_pad_gpio_emc_18::W
• sw_pad_ctl_pad_gpio_emc_19::DSE_R
• sw_pad_ctl_pad_gpio_emc_19::HYS_R
• sw_pad_ctl_pad_gpio_emc_19::ODE_R
• sw_pad_ctl_pad_gpio_emc_19::PKE_R
• sw_pad_ctl_pad_gpio_emc_19::PUE_R
• sw_pad_ctl_pad_gpio_emc_19::PUS_R
• sw_pad_ctl_pad_gpio_emc_19::R
• sw_pad_ctl_pad_gpio_emc_19::SPEED_R
• sw_pad_ctl_pad_gpio_emc_19::SRE_R
• sw_pad_ctl_pad_gpio_emc_19::W
• sw_pad_ctl_pad_gpio_emc_20::DSE_R
• sw_pad_ctl_pad_gpio_emc_20::HYS_R
• sw_pad_ctl_pad_gpio_emc_20::ODE_R
• sw_pad_ctl_pad_gpio_emc_20::PKE_R
• sw_pad_ctl_pad_gpio_emc_20::PUE_R
• sw_pad_ctl_pad_gpio_emc_20::PUS_R
• sw_pad_ctl_pad_gpio_emc_20::R
• sw_pad_ctl_pad_gpio_emc_20::SPEED_R
• sw_pad_ctl_pad_gpio_emc_20::SRE_R
• sw_pad_ctl_pad_gpio_emc_20::W
• sw_pad_ctl_pad_gpio_emc_21::DSE_R
• sw_pad_ctl_pad_gpio_emc_21::HYS_R
• sw_pad_ctl_pad_gpio_emc_21::ODE_R
• sw_pad_ctl_pad_gpio_emc_21::PKE_R
• sw_pad_ctl_pad_gpio_emc_21::PUE_R
• sw_pad_ctl_pad_gpio_emc_21::PUS_R
• sw_pad_ctl_pad_gpio_emc_21::R
• sw_pad_ctl_pad_gpio_emc_21::SPEED_R
• sw_pad_ctl_pad_gpio_emc_21::SRE_R
• sw_pad_ctl_pad_gpio_emc_21::W
• sw_pad_ctl_pad_gpio_emc_22::DSE_R
• sw_pad_ctl_pad_gpio_emc_22::HYS_R
• sw_pad_ctl_pad_gpio_emc_22::ODE_R
• sw_pad_ctl_pad_gpio_emc_22::PKE_R
• sw_pad_ctl_pad_gpio_emc_22::PUE_R
• sw_pad_ctl_pad_gpio_emc_22::PUS_R
• sw_pad_ctl_pad_gpio_emc_22::R
• sw_pad_ctl_pad_gpio_emc_22::SPEED_R
• sw_pad_ctl_pad_gpio_emc_22::SRE_R
• sw_pad_ctl_pad_gpio_emc_22::W
• sw_pad_ctl_pad_gpio_emc_23::DSE_R
• sw_pad_ctl_pad_gpio_emc_23::HYS_R
• sw_pad_ctl_pad_gpio_emc_23::ODE_R
• sw_pad_ctl_pad_gpio_emc_23::PKE_R
• sw_pad_ctl_pad_gpio_emc_23::PUE_R
• sw_pad_ctl_pad_gpio_emc_23::PUS_R
• sw_pad_ctl_pad_gpio_emc_23::R
• sw_pad_ctl_pad_gpio_emc_23::SPEED_R
• sw_pad_ctl_pad_gpio_emc_23::SRE_R
• sw_pad_ctl_pad_gpio_emc_23::W
• sw_pad_ctl_pad_gpio_emc_24::DSE_R
• sw_pad_ctl_pad_gpio_emc_24::HYS_R
• sw_pad_ctl_pad_gpio_emc_24::ODE_R
• sw_pad_ctl_pad_gpio_emc_24::PKE_R
• sw_pad_ctl_pad_gpio_emc_24::PUE_R
• sw_pad_ctl_pad_gpio_emc_24::PUS_R
• sw_pad_ctl_pad_gpio_emc_24::R
• sw_pad_ctl_pad_gpio_emc_24::SPEED_R
• sw_pad_ctl_pad_gpio_emc_24::SRE_R
• sw_pad_ctl_pad_gpio_emc_24::W
• sw_pad_ctl_pad_gpio_emc_25::DSE_R
• sw_pad_ctl_pad_gpio_emc_25::HYS_R
• sw_pad_ctl_pad_gpio_emc_25::ODE_R
• sw_pad_ctl_pad_gpio_emc_25::PKE_R
• sw_pad_ctl_pad_gpio_emc_25::PUE_R
• sw_pad_ctl_pad_gpio_emc_25::PUS_R
• sw_pad_ctl_pad_gpio_emc_25::R
• sw_pad_ctl_pad_gpio_emc_25::SPEED_R
• sw_pad_ctl_pad_gpio_emc_25::SRE_R
• sw_pad_ctl_pad_gpio_emc_25::W
• sw_pad_ctl_pad_gpio_emc_26::DSE_R
• sw_pad_ctl_pad_gpio_emc_26::HYS_R
• sw_pad_ctl_pad_gpio_emc_26::ODE_R
• sw_pad_ctl_pad_gpio_emc_26::PKE_R
• sw_pad_ctl_pad_gpio_emc_26::PUE_R
• sw_pad_ctl_pad_gpio_emc_26::PUS_R
• sw_pad_ctl_pad_gpio_emc_26::R
• sw_pad_ctl_pad_gpio_emc_26::SPEED_R
• sw_pad_ctl_pad_gpio_emc_26::SRE_R
• sw_pad_ctl_pad_gpio_emc_26::W
• sw_pad_ctl_pad_gpio_emc_27::DSE_R
• sw_pad_ctl_pad_gpio_emc_27::HYS_R
• sw_pad_ctl_pad_gpio_emc_27::ODE_R
• sw_pad_ctl_pad_gpio_emc_27::PKE_R
• sw_pad_ctl_pad_gpio_emc_27::PUE_R
• sw_pad_ctl_pad_gpio_emc_27::PUS_R
• sw_pad_ctl_pad_gpio_emc_27::R
• sw_pad_ctl_pad_gpio_emc_27::SPEED_R
• sw_pad_ctl_pad_gpio_emc_27::SRE_R
• sw_pad_ctl_pad_gpio_emc_27::W
• sw_pad_ctl_pad_gpio_emc_28::DSE_R
• sw_pad_ctl_pad_gpio_emc_28::HYS_R
• sw_pad_ctl_pad_gpio_emc_28::ODE_R
• sw_pad_ctl_pad_gpio_emc_28::PKE_R
• sw_pad_ctl_pad_gpio_emc_28::PUE_R
• sw_pad_ctl_pad_gpio_emc_28::PUS_R
• sw_pad_ctl_pad_gpio_emc_28::R
• sw_pad_ctl_pad_gpio_emc_28::SPEED_R
• sw_pad_ctl_pad_gpio_emc_28::SRE_R
• sw_pad_ctl_pad_gpio_emc_28::W
• sw_pad_ctl_pad_gpio_emc_29::DSE_R
• sw_pad_ctl_pad_gpio_emc_29::HYS_R
• sw_pad_ctl_pad_gpio_emc_29::ODE_R
• sw_pad_ctl_pad_gpio_emc_29::PKE_R
• sw_pad_ctl_pad_gpio_emc_29::PUE_R
• sw_pad_ctl_pad_gpio_emc_29::PUS_R
• sw_pad_ctl_pad_gpio_emc_29::R
• sw_pad_ctl_pad_gpio_emc_29::SPEED_R
• sw_pad_ctl_pad_gpio_emc_29::SRE_R
• sw_pad_ctl_pad_gpio_emc_29::W
• sw_pad_ctl_pad_gpio_emc_30::DSE_R
• sw_pad_ctl_pad_gpio_emc_30::HYS_R
• sw_pad_ctl_pad_gpio_emc_30::ODE_R
• sw_pad_ctl_pad_gpio_emc_30::PKE_R
• sw_pad_ctl_pad_gpio_emc_30::PUE_R
• sw_pad_ctl_pad_gpio_emc_30::PUS_R
• sw_pad_ctl_pad_gpio_emc_30::R
• sw_pad_ctl_pad_gpio_emc_30::SPEED_R
• sw_pad_ctl_pad_gpio_emc_30::SRE_R
• sw_pad_ctl_pad_gpio_emc_30::W
• sw_pad_ctl_pad_gpio_emc_31::DSE_R
• sw_pad_ctl_pad_gpio_emc_31::HYS_R
• sw_pad_ctl_pad_gpio_emc_31::ODE_R
• sw_pad_ctl_pad_gpio_emc_31::PKE_R
• sw_pad_ctl_pad_gpio_emc_31::PUE_R
• sw_pad_ctl_pad_gpio_emc_31::PUS_R
• sw_pad_ctl_pad_gpio_emc_31::R
• sw_pad_ctl_pad_gpio_emc_31::SPEED_R
• sw_pad_ctl_pad_gpio_emc_31::SRE_R
• sw_pad_ctl_pad_gpio_emc_31::W
• sw_pad_ctl_pad_gpio_emc_32::DSE_R
• sw_pad_ctl_pad_gpio_emc_32::HYS_R
• sw_pad_ctl_pad_gpio_emc_32::ODE_R
• sw_pad_ctl_pad_gpio_emc_32::PKE_R
• sw_pad_ctl_pad_gpio_emc_32::PUE_R
• sw_pad_ctl_pad_gpio_emc_32::PUS_R
• sw_pad_ctl_pad_gpio_emc_32::R
• sw_pad_ctl_pad_gpio_emc_32::SPEED_R
• sw_pad_ctl_pad_gpio_emc_32::SRE_R
• sw_pad_ctl_pad_gpio_emc_32::W
• sw_pad_ctl_pad_gpio_emc_33::DSE_R
• sw_pad_ctl_pad_gpio_emc_33::HYS_R
• sw_pad_ctl_pad_gpio_emc_33::ODE_R
• sw_pad_ctl_pad_gpio_emc_33::PKE_R
• sw_pad_ctl_pad_gpio_emc_33::PUE_R
• sw_pad_ctl_pad_gpio_emc_33::PUS_R
• sw_pad_ctl_pad_gpio_emc_33::R
• sw_pad_ctl_pad_gpio_emc_33::SPEED_R
• sw_pad_ctl_pad_gpio_emc_33::SRE_R
• sw_pad_ctl_pad_gpio_emc_33::W
• sw_pad_ctl_pad_gpio_emc_34::DSE_R
• sw_pad_ctl_pad_gpio_emc_34::HYS_R
• sw_pad_ctl_pad_gpio_emc_34::ODE_R
• sw_pad_ctl_pad_gpio_emc_34::PKE_R
• sw_pad_ctl_pad_gpio_emc_34::PUE_R
• sw_pad_ctl_pad_gpio_emc_34::PUS_R
• sw_pad_ctl_pad_gpio_emc_34::R
• sw_pad_ctl_pad_gpio_emc_34::SPEED_R
• sw_pad_ctl_pad_gpio_emc_34::SRE_R
• sw_pad_ctl_pad_gpio_emc_34::W
• sw_pad_ctl_pad_gpio_emc_35::DSE_R
• sw_pad_ctl_pad_gpio_emc_35::HYS_R
• sw_pad_ctl_pad_gpio_emc_35::ODE_R
• sw_pad_ctl_pad_gpio_emc_35::PKE_R
• sw_pad_ctl_pad_gpio_emc_35::PUE_R
• sw_pad_ctl_pad_gpio_emc_35::PUS_R
• sw_pad_ctl_pad_gpio_emc_35::R
• sw_pad_ctl_pad_gpio_emc_35::SPEED_R
• sw_pad_ctl_pad_gpio_emc_35::SRE_R
• sw_pad_ctl_pad_gpio_emc_35::W
• sw_pad_ctl_pad_gpio_emc_36::DSE_R
• sw_pad_ctl_pad_gpio_emc_36::HYS_R
• sw_pad_ctl_pad_gpio_emc_36::ODE_R
• sw_pad_ctl_pad_gpio_emc_36::PKE_R
• sw_pad_ctl_pad_gpio_emc_36::PUE_R
• sw_pad_ctl_pad_gpio_emc_36::PUS_R
• sw_pad_ctl_pad_gpio_emc_36::R
• sw_pad_ctl_pad_gpio_emc_36::SPEED_R
• sw_pad_ctl_pad_gpio_emc_36::SRE_R
• sw_pad_ctl_pad_gpio_emc_36::W
• sw_pad_ctl_pad_gpio_emc_37::DSE_R
• sw_pad_ctl_pad_gpio_emc_37::HYS_R
• sw_pad_ctl_pad_gpio_emc_37::ODE_R
• sw_pad_ctl_pad_gpio_emc_37::PKE_R
• sw_pad_ctl_pad_gpio_emc_37::PUE_R
• sw_pad_ctl_pad_gpio_emc_37::PUS_R
• sw_pad_ctl_pad_gpio_emc_37::R
• sw_pad_ctl_pad_gpio_emc_37::SPEED_R
• sw_pad_ctl_pad_gpio_emc_37::SRE_R
• sw_pad_ctl_pad_gpio_emc_37::W
• sw_pad_ctl_pad_gpio_emc_38::DSE_R
• sw_pad_ctl_pad_gpio_emc_38::HYS_R
• sw_pad_ctl_pad_gpio_emc_38::ODE_R
• sw_pad_ctl_pad_gpio_emc_38::PKE_R
• sw_pad_ctl_pad_gpio_emc_38::PUE_R
• sw_pad_ctl_pad_gpio_emc_38::PUS_R
• sw_pad_ctl_pad_gpio_emc_38::R
• sw_pad_ctl_pad_gpio_emc_38::SPEED_R
• sw_pad_ctl_pad_gpio_emc_38::SRE_R
• sw_pad_ctl_pad_gpio_emc_38::W
• sw_pad_ctl_pad_gpio_emc_39::DSE_R
• sw_pad_ctl_pad_gpio_emc_39::HYS_R
• sw_pad_ctl_pad_gpio_emc_39::ODE_R
• sw_pad_ctl_pad_gpio_emc_39::PKE_R
• sw_pad_ctl_pad_gpio_emc_39::PUE_R
• sw_pad_ctl_pad_gpio_emc_39::PUS_R
• sw_pad_ctl_pad_gpio_emc_39::R
• sw_pad_ctl_pad_gpio_emc_39::SPEED_R
• sw_pad_ctl_pad_gpio_emc_39::SRE_R
• sw_pad_ctl_pad_gpio_emc_39::W
• sw_pad_ctl_pad_gpio_emc_40::DSE_R
• sw_pad_ctl_pad_gpio_emc_40::HYS_R
• sw_pad_ctl_pad_gpio_emc_40::ODE_R
• sw_pad_ctl_pad_gpio_emc_40::PKE_R
• sw_pad_ctl_pad_gpio_emc_40::PUE_R
• sw_pad_ctl_pad_gpio_emc_40::PUS_R
• sw_pad_ctl_pad_gpio_emc_40::R
• sw_pad_ctl_pad_gpio_emc_40::SPEED_R
• sw_pad_ctl_pad_gpio_emc_40::SRE_R
• sw_pad_ctl_pad_gpio_emc_40::W
• sw_pad_ctl_pad_gpio_emc_41::DSE_R
• sw_pad_ctl_pad_gpio_emc_41::HYS_R
• sw_pad_ctl_pad_gpio_emc_41::ODE_R
• sw_pad_ctl_pad_gpio_emc_41::PKE_R
• sw_pad_ctl_pad_gpio_emc_41::PUE_R
• sw_pad_ctl_pad_gpio_emc_41::PUS_R
• sw_pad_ctl_pad_gpio_emc_41::R
• sw_pad_ctl_pad_gpio_emc_41::SPEED_R
• sw_pad_ctl_pad_gpio_emc_41::SRE_R
• sw_pad_ctl_pad_gpio_emc_41::W
• sw_pad_ctl_pad_gpio_sd_b0_00::DSE_R
• sw_pad_ctl_pad_gpio_sd_b0_00::HYS_R
• sw_pad_ctl_pad_gpio_sd_b0_00::ODE_R
• sw_pad_ctl_pad_gpio_sd_b0_00::PKE_R
• sw_pad_ctl_pad_gpio_sd_b0_00::PUE_R
• sw_pad_ctl_pad_gpio_sd_b0_00::PUS_R
• sw_pad_ctl_pad_gpio_sd_b0_00::R
• sw_pad_ctl_pad_gpio_sd_b0_00::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b0_00::SRE_R
• sw_pad_ctl_pad_gpio_sd_b0_00::W
• sw_pad_ctl_pad_gpio_sd_b0_01::DSE_R
• sw_pad_ctl_pad_gpio_sd_b0_01::HYS_R
• sw_pad_ctl_pad_gpio_sd_b0_01::ODE_R
• sw_pad_ctl_pad_gpio_sd_b0_01::PKE_R
• sw_pad_ctl_pad_gpio_sd_b0_01::PUE_R
• sw_pad_ctl_pad_gpio_sd_b0_01::PUS_R
• sw_pad_ctl_pad_gpio_sd_b0_01::R
• sw_pad_ctl_pad_gpio_sd_b0_01::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b0_01::SRE_R
• sw_pad_ctl_pad_gpio_sd_b0_01::W
• sw_pad_ctl_pad_gpio_sd_b0_02::DSE_R
• sw_pad_ctl_pad_gpio_sd_b0_02::HYS_R
• sw_pad_ctl_pad_gpio_sd_b0_02::ODE_R
• sw_pad_ctl_pad_gpio_sd_b0_02::PKE_R
• sw_pad_ctl_pad_gpio_sd_b0_02::PUE_R
• sw_pad_ctl_pad_gpio_sd_b0_02::PUS_R
• sw_pad_ctl_pad_gpio_sd_b0_02::R
• sw_pad_ctl_pad_gpio_sd_b0_02::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b0_02::SRE_R
• sw_pad_ctl_pad_gpio_sd_b0_02::W
• sw_pad_ctl_pad_gpio_sd_b0_03::DSE_R
• sw_pad_ctl_pad_gpio_sd_b0_03::HYS_R
• sw_pad_ctl_pad_gpio_sd_b0_03::ODE_R
• sw_pad_ctl_pad_gpio_sd_b0_03::PKE_R
• sw_pad_ctl_pad_gpio_sd_b0_03::PUE_R
• sw_pad_ctl_pad_gpio_sd_b0_03::PUS_R
• sw_pad_ctl_pad_gpio_sd_b0_03::R
• sw_pad_ctl_pad_gpio_sd_b0_03::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b0_03::SRE_R
• sw_pad_ctl_pad_gpio_sd_b0_03::W
• sw_pad_ctl_pad_gpio_sd_b0_04::DSE_R
• sw_pad_ctl_pad_gpio_sd_b0_04::HYS_R
• sw_pad_ctl_pad_gpio_sd_b0_04::ODE_R
• sw_pad_ctl_pad_gpio_sd_b0_04::PKE_R
• sw_pad_ctl_pad_gpio_sd_b0_04::PUE_R
• sw_pad_ctl_pad_gpio_sd_b0_04::PUS_R
• sw_pad_ctl_pad_gpio_sd_b0_04::R
• sw_pad_ctl_pad_gpio_sd_b0_04::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b0_04::SRE_R
• sw_pad_ctl_pad_gpio_sd_b0_04::W
• sw_pad_ctl_pad_gpio_sd_b0_05::DSE_R
• sw_pad_ctl_pad_gpio_sd_b0_05::HYS_R
• sw_pad_ctl_pad_gpio_sd_b0_05::ODE_R
• sw_pad_ctl_pad_gpio_sd_b0_05::PKE_R
• sw_pad_ctl_pad_gpio_sd_b0_05::PUE_R
• sw_pad_ctl_pad_gpio_sd_b0_05::PUS_R
• sw_pad_ctl_pad_gpio_sd_b0_05::R
• sw_pad_ctl_pad_gpio_sd_b0_05::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b0_05::SRE_R
• sw_pad_ctl_pad_gpio_sd_b0_05::W
• sw_pad_ctl_pad_gpio_sd_b1_00::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_00::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_00::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_00::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_00::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_00::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_00::R
• sw_pad_ctl_pad_gpio_sd_b1_00::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_00::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_00::W
• sw_pad_ctl_pad_gpio_sd_b1_01::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_01::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_01::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_01::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_01::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_01::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_01::R
• sw_pad_ctl_pad_gpio_sd_b1_01::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_01::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_01::W
• sw_pad_ctl_pad_gpio_sd_b1_02::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_02::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_02::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_02::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_02::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_02::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_02::R
• sw_pad_ctl_pad_gpio_sd_b1_02::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_02::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_02::W
• sw_pad_ctl_pad_gpio_sd_b1_03::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_03::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_03::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_03::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_03::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_03::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_03::R
• sw_pad_ctl_pad_gpio_sd_b1_03::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_03::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_03::W
• sw_pad_ctl_pad_gpio_sd_b1_04::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_04::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_04::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_04::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_04::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_04::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_04::R
• sw_pad_ctl_pad_gpio_sd_b1_04::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_04::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_04::W
• sw_pad_ctl_pad_gpio_sd_b1_05::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_05::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_05::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_05::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_05::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_05::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_05::R
• sw_pad_ctl_pad_gpio_sd_b1_05::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_05::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_05::W
• sw_pad_ctl_pad_gpio_sd_b1_06::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_06::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_06::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_06::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_06::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_06::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_06::R
• sw_pad_ctl_pad_gpio_sd_b1_06::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_06::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_06::W
• sw_pad_ctl_pad_gpio_sd_b1_07::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_07::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_07::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_07::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_07::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_07::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_07::R
• sw_pad_ctl_pad_gpio_sd_b1_07::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_07::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_07::W
• sw_pad_ctl_pad_gpio_sd_b1_08::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_08::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_08::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_08::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_08::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_08::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_08::R
• sw_pad_ctl_pad_gpio_sd_b1_08::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_08::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_08::W
• sw_pad_ctl_pad_gpio_sd_b1_09::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_09::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_09::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_09::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_09::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_09::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_09::R
• sw_pad_ctl_pad_gpio_sd_b1_09::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_09::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_09::W
• sw_pad_ctl_pad_gpio_sd_b1_10::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_10::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_10::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_10::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_10::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_10::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_10::R
• sw_pad_ctl_pad_gpio_sd_b1_10::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_10::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_10::W
• sw_pad_ctl_pad_gpio_sd_b1_11::DSE_R
• sw_pad_ctl_pad_gpio_sd_b1_11::HYS_R
• sw_pad_ctl_pad_gpio_sd_b1_11::ODE_R
• sw_pad_ctl_pad_gpio_sd_b1_11::PKE_R
• sw_pad_ctl_pad_gpio_sd_b1_11::PUE_R
• sw_pad_ctl_pad_gpio_sd_b1_11::PUS_R
• sw_pad_ctl_pad_gpio_sd_b1_11::R
• sw_pad_ctl_pad_gpio_sd_b1_11::SPEED_R
• sw_pad_ctl_pad_gpio_sd_b1_11::SRE_R
• sw_pad_ctl_pad_gpio_sd_b1_11::W
• sw_pad_ctl_pad_gpio_spi_b0_00::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_00::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_00::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_00::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_00::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_00::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_00::R
• sw_pad_ctl_pad_gpio_spi_b0_00::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_00::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_00::W
• sw_pad_ctl_pad_gpio_spi_b0_01::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_01::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_01::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_01::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_01::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_01::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_01::R
• sw_pad_ctl_pad_gpio_spi_b0_01::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_01::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_01::W
• sw_pad_ctl_pad_gpio_spi_b0_02::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_02::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_02::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_02::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_02::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_02::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_02::R
• sw_pad_ctl_pad_gpio_spi_b0_02::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_02::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_02::W
• sw_pad_ctl_pad_gpio_spi_b0_03::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_03::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_03::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_03::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_03::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_03::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_03::R
• sw_pad_ctl_pad_gpio_spi_b0_03::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_03::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_03::W
• sw_pad_ctl_pad_gpio_spi_b0_04::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_04::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_04::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_04::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_04::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_04::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_04::R
• sw_pad_ctl_pad_gpio_spi_b0_04::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_04::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_04::W
• sw_pad_ctl_pad_gpio_spi_b0_05::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_05::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_05::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_05::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_05::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_05::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_05::R
• sw_pad_ctl_pad_gpio_spi_b0_05::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_05::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_05::W
• sw_pad_ctl_pad_gpio_spi_b0_06::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_06::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_06::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_06::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_06::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_06::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_06::R
• sw_pad_ctl_pad_gpio_spi_b0_06::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_06::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_06::W
• sw_pad_ctl_pad_gpio_spi_b0_07::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_07::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_07::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_07::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_07::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_07::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_07::R
• sw_pad_ctl_pad_gpio_spi_b0_07::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_07::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_07::W
• sw_pad_ctl_pad_gpio_spi_b0_08::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_08::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_08::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_08::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_08::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_08::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_08::R
• sw_pad_ctl_pad_gpio_spi_b0_08::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_08::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_08::W
• sw_pad_ctl_pad_gpio_spi_b0_09::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_09::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_09::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_09::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_09::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_09::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_09::R
• sw_pad_ctl_pad_gpio_spi_b0_09::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_09::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_09::W
• sw_pad_ctl_pad_gpio_spi_b0_10::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_10::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_10::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_10::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_10::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_10::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_10::R
• sw_pad_ctl_pad_gpio_spi_b0_10::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_10::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_10::W
• sw_pad_ctl_pad_gpio_spi_b0_11::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_11::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_11::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_11::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_11::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_11::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_11::R
• sw_pad_ctl_pad_gpio_spi_b0_11::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_11::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_11::W
• sw_pad_ctl_pad_gpio_spi_b0_12::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_12::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_12::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_12::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_12::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_12::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_12::R
• sw_pad_ctl_pad_gpio_spi_b0_12::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_12::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_12::W
• sw_pad_ctl_pad_gpio_spi_b0_13::DSE_R
• sw_pad_ctl_pad_gpio_spi_b0_13::HYS_R
• sw_pad_ctl_pad_gpio_spi_b0_13::ODE_R
• sw_pad_ctl_pad_gpio_spi_b0_13::PKE_R
• sw_pad_ctl_pad_gpio_spi_b0_13::PUE_R
• sw_pad_ctl_pad_gpio_spi_b0_13::PUS_R
• sw_pad_ctl_pad_gpio_spi_b0_13::R
• sw_pad_ctl_pad_gpio_spi_b0_13::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b0_13::SRE_R
• sw_pad_ctl_pad_gpio_spi_b0_13::W
• sw_pad_ctl_pad_gpio_spi_b1_00::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_00::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_00::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_00::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_00::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_00::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_00::R
• sw_pad_ctl_pad_gpio_spi_b1_00::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_00::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_00::W
• sw_pad_ctl_pad_gpio_spi_b1_01::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_01::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_01::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_01::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_01::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_01::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_01::R
• sw_pad_ctl_pad_gpio_spi_b1_01::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_01::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_01::W
• sw_pad_ctl_pad_gpio_spi_b1_02::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_02::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_02::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_02::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_02::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_02::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_02::R
• sw_pad_ctl_pad_gpio_spi_b1_02::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_02::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_02::W
• sw_pad_ctl_pad_gpio_spi_b1_03::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_03::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_03::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_03::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_03::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_03::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_03::R
• sw_pad_ctl_pad_gpio_spi_b1_03::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_03::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_03::W
• sw_pad_ctl_pad_gpio_spi_b1_04::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_04::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_04::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_04::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_04::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_04::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_04::R
• sw_pad_ctl_pad_gpio_spi_b1_04::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_04::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_04::W
• sw_pad_ctl_pad_gpio_spi_b1_05::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_05::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_05::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_05::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_05::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_05::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_05::R
• sw_pad_ctl_pad_gpio_spi_b1_05::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_05::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_05::W
• sw_pad_ctl_pad_gpio_spi_b1_06::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_06::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_06::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_06::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_06::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_06::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_06::R
• sw_pad_ctl_pad_gpio_spi_b1_06::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_06::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_06::W
• sw_pad_ctl_pad_gpio_spi_b1_07::DSE_R
• sw_pad_ctl_pad_gpio_spi_b1_07::HYS_R
• sw_pad_ctl_pad_gpio_spi_b1_07::ODE_R
• sw_pad_ctl_pad_gpio_spi_b1_07::PKE_R
• sw_pad_ctl_pad_gpio_spi_b1_07::PUE_R
• sw_pad_ctl_pad_gpio_spi_b1_07::PUS_R
• sw_pad_ctl_pad_gpio_spi_b1_07::R
• sw_pad_ctl_pad_gpio_spi_b1_07::SPEED_R
• sw_pad_ctl_pad_gpio_spi_b1_07::SRE_R
• sw_pad_ctl_pad_gpio_spi_b1_07::W
• usb_otg1_oc_select_input::DAISY_R
• usb_otg1_oc_select_input::R
• usb_otg1_oc_select_input::W
• usb_otg2_oc_select_input::DAISY_R
• usb_otg2_oc_select_input::R
• usb_otg2_oc_select_input::W
• usdhc1_cd_b_select_input::DAISY_R
• usdhc1_cd_b_select_input::R
• usdhc1_cd_b_select_input::W
• usdhc1_wp_select_input::DAISY_R
• usdhc1_wp_select_input::R
• usdhc1_wp_select_input::W
• usdhc2_cd_b_select_input::DAISY_R
• usdhc2_cd_b_select_input::R
• usdhc2_cd_b_select_input::W
• usdhc2_clk_select_input::DAISY_R
• usdhc2_clk_select_input::R
• usdhc2_clk_select_input::W
• usdhc2_cmd_select_input::DAISY_R
• usdhc2_cmd_select_input::R
• usdhc2_cmd_select_input::W
• usdhc2_data0_select_input::DAISY_R
• usdhc2_data0_select_input::R
• usdhc2_data0_select_input::W
• usdhc2_data1_select_input::DAISY_R
• usdhc2_data1_select_input::R
• usdhc2_data1_select_input::W
• usdhc2_data2_select_input::DAISY_R
• usdhc2_data2_select_input::R
• usdhc2_data2_select_input::W
• usdhc2_data3_select_input::DAISY_R
• usdhc2_data3_select_input::R
• usdhc2_data3_select_input::W
• usdhc2_data4_select_input::DAISY_R
• usdhc2_data4_select_input::R
• usdhc2_data4_select_input::W
• usdhc2_data5_select_input::DAISY_R
• usdhc2_data5_select_input::R
• usdhc2_data5_select_input::W
• usdhc2_data6_select_input::DAISY_R
• usdhc2_data6_select_input::R
• usdhc2_data6_select_input::W
• usdhc2_data7_select_input::DAISY_R
• usdhc2_data7_select_input::R
• usdhc2_data7_select_input::W
• usdhc2_wp_select_input::DAISY_R
• usdhc2_wp_select_input::R
• usdhc2_wp_select_input::W
• xbar1_in02_select_input::DAISY_R
• xbar1_in02_select_input::R
• xbar1_in02_select_input::W
• xbar1_in03_select_input::DAISY_R
• xbar1_in03_select_input::R
• xbar1_in03_select_input::W
• xbar1_in04_select_input::DAISY_R
• xbar1_in04_select_input::R
• xbar1_in04_select_input::W
• xbar1_in05_select_input::DAISY_R
• xbar1_in05_select_input::R
• xbar1_in05_select_input::W
• xbar1_in06_select_input::DAISY_R
• xbar1_in06_select_input::R
• xbar1_in06_select_input::W
• xbar1_in07_select_input::DAISY_R
• xbar1_in07_select_input::R
• xbar1_in07_select_input::W
• xbar1_in08_select_input::DAISY_R
• xbar1_in08_select_input::R
• xbar1_in08_select_input::W
• xbar1_in09_select_input::DAISY_R
• xbar1_in09_select_input::R
• xbar1_in09_select_input::W
• xbar1_in14_select_input::DAISY_R
• xbar1_in14_select_input::R
• xbar1_in14_select_input::W
• xbar1_in15_select_input::DAISY_R
• xbar1_in15_select_input::R
• xbar1_in15_select_input::W
• xbar1_in16_select_input::DAISY_R
• xbar1_in16_select_input::R
• xbar1_in16_select_input::W
• xbar1_in17_select_input::DAISY_R
• xbar1_in17_select_input::R
• xbar1_in17_select_input::W
• xbar1_in18_select_input::DAISY_R
• xbar1_in18_select_input::R
• xbar1_in18_select_input::W
• xbar1_in19_select_input::DAISY_R
• xbar1_in19_select_input::R
• xbar1_in19_select_input::W
• xbar1_in20_select_input::DAISY_R
• xbar1_in20_select_input::R
• xbar1_in20_select_input::W
• xbar1_in21_select_input::DAISY_R
• xbar1_in21_select_input::R
• xbar1_in21_select_input::W
• xbar1_in22_select_input::DAISY_R
• xbar1_in22_select_input::R
• xbar1_in22_select_input::W
• xbar1_in23_select_input::DAISY_R
• xbar1_in23_select_input::R
• xbar1_in23_select_input::W
• xbar1_in24_select_input::DAISY_R
• xbar1_in24_select_input::R
• xbar1_in24_select_input::W
• xbar1_in25_select_input::DAISY_R
• xbar1_in25_select_input::R
• xbar1_in25_select_input::W