Type Definition imxrt1062_flexspi::mcr2::W

type W = W<u32, MCR2>;

Writer for register MCR2

Methods

impl W

pub fn clrahbbufopt(&mut self) -> CLRAHBBUFOPT_W

Bit 11 - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.

pub fn clrlearnphase(&mut self) -> CLRLEARNPHASE_W

Bit 14 - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.

pub fn samedeviceen(&mut self) -> SAMEDEVICEEN_W

Bit 15 - All external devices are same devices (both in types and size) for A1/A2/B1/B2.

pub fn sckbdiffopt(&mut self) -> SCKBDIFFOPT_W

Bit 19 - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set.

pub fn resumewait(&mut self) -> RESUMEWAIT_W

Bits 24:31 - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.