[−][src]Struct imxrt1062_dma0::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

Writes raw bits to the register

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn edbg(&mut self) -> EDBG_W`[src]

Bit 1 - Enable Debug

`pub fn erca(&mut self) -> ERCA_W`[src]

Bit 2 - Enable Round Robin Channel Arbitration

`pub fn erga(&mut self) -> ERGA_W`[src]

Bit 3 - Enable Round Robin Group Arbitration

`pub fn hoe(&mut self) -> HOE_W`[src]

Bit 4 - Halt On Error

`pub fn halt(&mut self) -> HALT_W`[src]

Bit 5 - Halt DMA Operations

`pub fn clm(&mut self) -> CLM_W`[src]

Bit 6 - Continuous Link Mode

`pub fn emlm(&mut self) -> EMLM_W`[src]

Bit 7 - Enable Minor Loop Mapping

`pub fn grp0pri(&mut self) -> GRP0PRI_W`[src]

Bit 8 - Channel Group 0 Priority

`pub fn grp1pri(&mut self) -> GRP1PRI_W`[src]

Bit 10 - Channel Group 1 Priority

`pub fn ecx(&mut self) -> ECX_W`[src]

Bit 16 - Error Cancel Transfer

`pub fn cx(&mut self) -> CX_W`[src]

Bit 17 - Cancel Transfer

`impl W<u32, Reg<u32, _ERQ>>`[src]

`pub fn erq0(&mut self) -> ERQ0_W`[src]

Bit 0 - Enable DMA Request 0

`pub fn erq1(&mut self) -> ERQ1_W`[src]

Bit 1 - Enable DMA Request 1

`pub fn erq2(&mut self) -> ERQ2_W`[src]

Bit 2 - Enable DMA Request 2

`pub fn erq3(&mut self) -> ERQ3_W`[src]

Bit 3 - Enable DMA Request 3

`pub fn erq4(&mut self) -> ERQ4_W`[src]

Bit 4 - Enable DMA Request 4

`pub fn erq5(&mut self) -> ERQ5_W`[src]

Bit 5 - Enable DMA Request 5

`pub fn erq6(&mut self) -> ERQ6_W`[src]

Bit 6 - Enable DMA Request 6

`pub fn erq7(&mut self) -> ERQ7_W`[src]

Bit 7 - Enable DMA Request 7

`pub fn erq8(&mut self) -> ERQ8_W`[src]

Bit 8 - Enable DMA Request 8

`pub fn erq9(&mut self) -> ERQ9_W`[src]

Bit 9 - Enable DMA Request 9

`pub fn erq10(&mut self) -> ERQ10_W`[src]

Bit 10 - Enable DMA Request 10

`pub fn erq11(&mut self) -> ERQ11_W`[src]

Bit 11 - Enable DMA Request 11

`pub fn erq12(&mut self) -> ERQ12_W`[src]

Bit 12 - Enable DMA Request 12

`pub fn erq13(&mut self) -> ERQ13_W`[src]

Bit 13 - Enable DMA Request 13

`pub fn erq14(&mut self) -> ERQ14_W`[src]

Bit 14 - Enable DMA Request 14

`pub fn erq15(&mut self) -> ERQ15_W`[src]

Bit 15 - Enable DMA Request 15

`pub fn erq16(&mut self) -> ERQ16_W`[src]

Bit 16 - Enable DMA Request 16

`pub fn erq17(&mut self) -> ERQ17_W`[src]

Bit 17 - Enable DMA Request 17

`pub fn erq18(&mut self) -> ERQ18_W`[src]

Bit 18 - Enable DMA Request 18

`pub fn erq19(&mut self) -> ERQ19_W`[src]

Bit 19 - Enable DMA Request 19

`pub fn erq20(&mut self) -> ERQ20_W`[src]

Bit 20 - Enable DMA Request 20

`pub fn erq21(&mut self) -> ERQ21_W`[src]

Bit 21 - Enable DMA Request 21

`pub fn erq22(&mut self) -> ERQ22_W`[src]

Bit 22 - Enable DMA Request 22

`pub fn erq23(&mut self) -> ERQ23_W`[src]

Bit 23 - Enable DMA Request 23

`pub fn erq24(&mut self) -> ERQ24_W`[src]

Bit 24 - Enable DMA Request 24

`pub fn erq25(&mut self) -> ERQ25_W`[src]

Bit 25 - Enable DMA Request 25

`pub fn erq26(&mut self) -> ERQ26_W`[src]

Bit 26 - Enable DMA Request 26

`pub fn erq27(&mut self) -> ERQ27_W`[src]

Bit 27 - Enable DMA Request 27

`pub fn erq28(&mut self) -> ERQ28_W`[src]

Bit 28 - Enable DMA Request 28

`pub fn erq29(&mut self) -> ERQ29_W`[src]

Bit 29 - Enable DMA Request 29

`pub fn erq30(&mut self) -> ERQ30_W`[src]

Bit 30 - Enable DMA Request 30

`pub fn erq31(&mut self) -> ERQ31_W`[src]

Bit 31 - Enable DMA Request 31

`impl W<u32, Reg<u32, _EEI>>`[src]

`pub fn eei0(&mut self) -> EEI0_W`[src]

Bit 0 - Enable Error Interrupt 0

`pub fn eei1(&mut self) -> EEI1_W`[src]

Bit 1 - Enable Error Interrupt 1

`pub fn eei2(&mut self) -> EEI2_W`[src]

Bit 2 - Enable Error Interrupt 2

`pub fn eei3(&mut self) -> EEI3_W`[src]

Bit 3 - Enable Error Interrupt 3

`pub fn eei4(&mut self) -> EEI4_W`[src]

Bit 4 - Enable Error Interrupt 4

`pub fn eei5(&mut self) -> EEI5_W`[src]

Bit 5 - Enable Error Interrupt 5

`pub fn eei6(&mut self) -> EEI6_W`[src]

Bit 6 - Enable Error Interrupt 6

`pub fn eei7(&mut self) -> EEI7_W`[src]

Bit 7 - Enable Error Interrupt 7

`pub fn eei8(&mut self) -> EEI8_W`[src]

Bit 8 - Enable Error Interrupt 8

`pub fn eei9(&mut self) -> EEI9_W`[src]

Bit 9 - Enable Error Interrupt 9

`pub fn eei10(&mut self) -> EEI10_W`[src]

Bit 10 - Enable Error Interrupt 10

`pub fn eei11(&mut self) -> EEI11_W`[src]

Bit 11 - Enable Error Interrupt 11

`pub fn eei12(&mut self) -> EEI12_W`[src]

Bit 12 - Enable Error Interrupt 12

`pub fn eei13(&mut self) -> EEI13_W`[src]

Bit 13 - Enable Error Interrupt 13

`pub fn eei14(&mut self) -> EEI14_W`[src]

Bit 14 - Enable Error Interrupt 14

`pub fn eei15(&mut self) -> EEI15_W`[src]

Bit 15 - Enable Error Interrupt 15

`pub fn eei16(&mut self) -> EEI16_W`[src]

Bit 16 - Enable Error Interrupt 16

`pub fn eei17(&mut self) -> EEI17_W`[src]

Bit 17 - Enable Error Interrupt 17

`pub fn eei18(&mut self) -> EEI18_W`[src]

Bit 18 - Enable Error Interrupt 18

`pub fn eei19(&mut self) -> EEI19_W`[src]

Bit 19 - Enable Error Interrupt 19

`pub fn eei20(&mut self) -> EEI20_W`[src]

Bit 20 - Enable Error Interrupt 20

`pub fn eei21(&mut self) -> EEI21_W`[src]

Bit 21 - Enable Error Interrupt 21

`pub fn eei22(&mut self) -> EEI22_W`[src]

Bit 22 - Enable Error Interrupt 22

`pub fn eei23(&mut self) -> EEI23_W`[src]

Bit 23 - Enable Error Interrupt 23

`pub fn eei24(&mut self) -> EEI24_W`[src]

Bit 24 - Enable Error Interrupt 24

`pub fn eei25(&mut self) -> EEI25_W`[src]

Bit 25 - Enable Error Interrupt 25

`pub fn eei26(&mut self) -> EEI26_W`[src]

Bit 26 - Enable Error Interrupt 26

`pub fn eei27(&mut self) -> EEI27_W`[src]

Bit 27 - Enable Error Interrupt 27

`pub fn eei28(&mut self) -> EEI28_W`[src]

Bit 28 - Enable Error Interrupt 28

`pub fn eei29(&mut self) -> EEI29_W`[src]

Bit 29 - Enable Error Interrupt 29

`pub fn eei30(&mut self) -> EEI30_W`[src]

Bit 30 - Enable Error Interrupt 30

`pub fn eei31(&mut self) -> EEI31_W`[src]

Bit 31 - Enable Error Interrupt 31

`impl W<u8, Reg<u8, _CEEI>>`[src]

`pub fn ceei(&mut self) -> CEEI_W`[src]

Bits 0:4 - Clear Enable Error Interrupt

`pub fn caee(&mut self) -> CAEE_W`[src]

Bit 6 - Clear All Enable Error Interrupts

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _SEEI>>`[src]

`pub fn seei(&mut self) -> SEEI_W`[src]

Bits 0:4 - Set Enable Error Interrupt

`pub fn saee(&mut self) -> SAEE_W`[src]

Bit 6 - Sets All Enable Error Interrupts

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _CERQ>>`[src]

`pub fn cerq(&mut self) -> CERQ_W`[src]

Bits 0:4 - Clear Enable Request

`pub fn caer(&mut self) -> CAER_W`[src]

Bit 6 - Clear All Enable Requests

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _SERQ>>`[src]

`pub fn serq(&mut self) -> SERQ_W`[src]

Bits 0:4 - Set Enable Request

`pub fn saer(&mut self) -> SAER_W`[src]

Bit 6 - Set All Enable Requests

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _CDNE>>`[src]

`pub fn cdne(&mut self) -> CDNE_W`[src]

Bits 0:4 - Clear DONE Bit

`pub fn cadn(&mut self) -> CADN_W`[src]

Bit 6 - Clears All DONE Bits

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _SSRT>>`[src]

`pub fn ssrt(&mut self) -> SSRT_W`[src]

Bits 0:4 - Set START Bit

`pub fn sast(&mut self) -> SAST_W`[src]

Bit 6 - Set All START Bits (activates all channels)

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _CERR>>`[src]

`pub fn cerr(&mut self) -> CERR_W`[src]

Bits 0:4 - Clear Error Indicator

`pub fn caei(&mut self) -> CAEI_W`[src]

Bit 6 - Clear All Error Indicators

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u8, Reg<u8, _CINT>>`[src]

`pub fn cint(&mut self) -> CINT_W`[src]

Bits 0:4 - Clear Interrupt Request

`pub fn cair(&mut self) -> CAIR_W`[src]

Bit 6 - Clear All Interrupt Requests

`pub fn nop(&mut self) -> NOP_W`[src]

Bit 7 - No Op enable

`impl W<u32, Reg<u32, _INT>>`[src]

`pub fn int0(&mut self) -> INT0_W`[src]

Bit 0 - Interrupt Request 0

`pub fn int1(&mut self) -> INT1_W`[src]

Bit 1 - Interrupt Request 1

`pub fn int2(&mut self) -> INT2_W`[src]

Bit 2 - Interrupt Request 2

`pub fn int3(&mut self) -> INT3_W`[src]

Bit 3 - Interrupt Request 3

`pub fn int4(&mut self) -> INT4_W`[src]

Bit 4 - Interrupt Request 4

`pub fn int5(&mut self) -> INT5_W`[src]

Bit 5 - Interrupt Request 5

`pub fn int6(&mut self) -> INT6_W`[src]

Bit 6 - Interrupt Request 6

`pub fn int7(&mut self) -> INT7_W`[src]

Bit 7 - Interrupt Request 7

`pub fn int8(&mut self) -> INT8_W`[src]

Bit 8 - Interrupt Request 8

`pub fn int9(&mut self) -> INT9_W`[src]

Bit 9 - Interrupt Request 9

`pub fn int10(&mut self) -> INT10_W`[src]

Bit 10 - Interrupt Request 10

`pub fn int11(&mut self) -> INT11_W`[src]

Bit 11 - Interrupt Request 11

`pub fn int12(&mut self) -> INT12_W`[src]

Bit 12 - Interrupt Request 12

`pub fn int13(&mut self) -> INT13_W`[src]

Bit 13 - Interrupt Request 13

`pub fn int14(&mut self) -> INT14_W`[src]

Bit 14 - Interrupt Request 14

`pub fn int15(&mut self) -> INT15_W`[src]

Bit 15 - Interrupt Request 15

`pub fn int16(&mut self) -> INT16_W`[src]

Bit 16 - Interrupt Request 16

`pub fn int17(&mut self) -> INT17_W`[src]

Bit 17 - Interrupt Request 17

`pub fn int18(&mut self) -> INT18_W`[src]

Bit 18 - Interrupt Request 18

`pub fn int19(&mut self) -> INT19_W`[src]

Bit 19 - Interrupt Request 19

`pub fn int20(&mut self) -> INT20_W`[src]

Bit 20 - Interrupt Request 20

`pub fn int21(&mut self) -> INT21_W`[src]

Bit 21 - Interrupt Request 21

`pub fn int22(&mut self) -> INT22_W`[src]

Bit 22 - Interrupt Request 22

`pub fn int23(&mut self) -> INT23_W`[src]

Bit 23 - Interrupt Request 23

`pub fn int24(&mut self) -> INT24_W`[src]

Bit 24 - Interrupt Request 24

`pub fn int25(&mut self) -> INT25_W`[src]

Bit 25 - Interrupt Request 25

`pub fn int26(&mut self) -> INT26_W`[src]

Bit 26 - Interrupt Request 26

`pub fn int27(&mut self) -> INT27_W`[src]

Bit 27 - Interrupt Request 27

`pub fn int28(&mut self) -> INT28_W`[src]

Bit 28 - Interrupt Request 28

`pub fn int29(&mut self) -> INT29_W`[src]

Bit 29 - Interrupt Request 29

`pub fn int30(&mut self) -> INT30_W`[src]

Bit 30 - Interrupt Request 30

`pub fn int31(&mut self) -> INT31_W`[src]

Bit 31 - Interrupt Request 31

`impl W<u32, Reg<u32, _ERR>>`[src]

`pub fn err0(&mut self) -> ERR0_W`[src]

Bit 0 - Error In Channel 0

`pub fn err1(&mut self) -> ERR1_W`[src]

Bit 1 - Error In Channel 1

`pub fn err2(&mut self) -> ERR2_W`[src]

Bit 2 - Error In Channel 2

`pub fn err3(&mut self) -> ERR3_W`[src]

Bit 3 - Error In Channel 3

`pub fn err4(&mut self) -> ERR4_W`[src]

Bit 4 - Error In Channel 4

`pub fn err5(&mut self) -> ERR5_W`[src]

Bit 5 - Error In Channel 5

`pub fn err6(&mut self) -> ERR6_W`[src]

Bit 6 - Error In Channel 6

`pub fn err7(&mut self) -> ERR7_W`[src]

Bit 7 - Error In Channel 7

`pub fn err8(&mut self) -> ERR8_W`[src]

Bit 8 - Error In Channel 8

`pub fn err9(&mut self) -> ERR9_W`[src]

Bit 9 - Error In Channel 9

`pub fn err10(&mut self) -> ERR10_W`[src]

Bit 10 - Error In Channel 10

`pub fn err11(&mut self) -> ERR11_W`[src]

Bit 11 - Error In Channel 11

`pub fn err12(&mut self) -> ERR12_W`[src]

Bit 12 - Error In Channel 12

`pub fn err13(&mut self) -> ERR13_W`[src]

Bit 13 - Error In Channel 13

`pub fn err14(&mut self) -> ERR14_W`[src]

Bit 14 - Error In Channel 14

`pub fn err15(&mut self) -> ERR15_W`[src]

Bit 15 - Error In Channel 15

`pub fn err16(&mut self) -> ERR16_W`[src]

Bit 16 - Error In Channel 16

`pub fn err17(&mut self) -> ERR17_W`[src]

Bit 17 - Error In Channel 17

`pub fn err18(&mut self) -> ERR18_W`[src]

Bit 18 - Error In Channel 18

`pub fn err19(&mut self) -> ERR19_W`[src]

Bit 19 - Error In Channel 19

`pub fn err20(&mut self) -> ERR20_W`[src]

Bit 20 - Error In Channel 20

`pub fn err21(&mut self) -> ERR21_W`[src]

Bit 21 - Error In Channel 21

`pub fn err22(&mut self) -> ERR22_W`[src]

Bit 22 - Error In Channel 22

`pub fn err23(&mut self) -> ERR23_W`[src]

Bit 23 - Error In Channel 23

`pub fn err24(&mut self) -> ERR24_W`[src]

Bit 24 - Error In Channel 24

`pub fn err25(&mut self) -> ERR25_W`[src]

Bit 25 - Error In Channel 25

`pub fn err26(&mut self) -> ERR26_W`[src]

Bit 26 - Error In Channel 26

`pub fn err27(&mut self) -> ERR27_W`[src]

Bit 27 - Error In Channel 27

`pub fn err28(&mut self) -> ERR28_W`[src]

Bit 28 - Error In Channel 28

`pub fn err29(&mut self) -> ERR29_W`[src]

Bit 29 - Error In Channel 29

`pub fn err30(&mut self) -> ERR30_W`[src]

Bit 30 - Error In Channel 30

`pub fn err31(&mut self) -> ERR31_W`[src]

Bit 31 - Error In Channel 31

`impl W<u32, Reg<u32, _EARS>>`[src]

`pub fn edreq_0(&mut self) -> EDREQ_0_W`[src]

Bit 0 - Enable asynchronous DMA request in stop mode for channel 0.

`pub fn edreq_1(&mut self) -> EDREQ_1_W`[src]

Bit 1 - Enable asynchronous DMA request in stop mode for channel 1.

`pub fn edreq_2(&mut self) -> EDREQ_2_W`[src]

Bit 2 - Enable asynchronous DMA request in stop mode for channel 2.

`pub fn edreq_3(&mut self) -> EDREQ_3_W`[src]

Bit 3 - Enable asynchronous DMA request in stop mode for channel 3.

`pub fn edreq_4(&mut self) -> EDREQ_4_W`[src]

Bit 4 - Enable asynchronous DMA request in stop mode for channel 4

`pub fn edreq_5(&mut self) -> EDREQ_5_W`[src]

Bit 5 - Enable asynchronous DMA request in stop mode for channel 5

`pub fn edreq_6(&mut self) -> EDREQ_6_W`[src]

Bit 6 - Enable asynchronous DMA request in stop mode for channel 6

`pub fn edreq_7(&mut self) -> EDREQ_7_W`[src]

Bit 7 - Enable asynchronous DMA request in stop mode for channel 7

`pub fn edreq_8(&mut self) -> EDREQ_8_W`[src]

Bit 8 - Enable asynchronous DMA request in stop mode for channel 8

`pub fn edreq_9(&mut self) -> EDREQ_9_W`[src]

Bit 9 - Enable asynchronous DMA request in stop mode for channel 9

`pub fn edreq_10(&mut self) -> EDREQ_10_W`[src]

Bit 10 - Enable asynchronous DMA request in stop mode for channel 10

`pub fn edreq_11(&mut self) -> EDREQ_11_W`[src]

Bit 11 - Enable asynchronous DMA request in stop mode for channel 11

`pub fn edreq_12(&mut self) -> EDREQ_12_W`[src]

Bit 12 - Enable asynchronous DMA request in stop mode for channel 12

`pub fn edreq_13(&mut self) -> EDREQ_13_W`[src]

Bit 13 - Enable asynchronous DMA request in stop mode for channel 13

`pub fn edreq_14(&mut self) -> EDREQ_14_W`[src]

Bit 14 - Enable asynchronous DMA request in stop mode for channel 14

`pub fn edreq_15(&mut self) -> EDREQ_15_W`[src]

Bit 15 - Enable asynchronous DMA request in stop mode for channel 15

`pub fn edreq_16(&mut self) -> EDREQ_16_W`[src]

Bit 16 - Enable asynchronous DMA request in stop mode for channel 16

`pub fn edreq_17(&mut self) -> EDREQ_17_W`[src]

Bit 17 - Enable asynchronous DMA request in stop mode for channel 17

`pub fn edreq_18(&mut self) -> EDREQ_18_W`[src]

Bit 18 - Enable asynchronous DMA request in stop mode for channel 18

`pub fn edreq_19(&mut self) -> EDREQ_19_W`[src]

Bit 19 - Enable asynchronous DMA request in stop mode for channel 19

`pub fn edreq_20(&mut self) -> EDREQ_20_W`[src]

Bit 20 - Enable asynchronous DMA request in stop mode for channel 20

`pub fn edreq_21(&mut self) -> EDREQ_21_W`[src]

Bit 21 - Enable asynchronous DMA request in stop mode for channel 21

`pub fn edreq_22(&mut self) -> EDREQ_22_W`[src]

Bit 22 - Enable asynchronous DMA request in stop mode for channel 22

`pub fn edreq_23(&mut self) -> EDREQ_23_W`[src]

Bit 23 - Enable asynchronous DMA request in stop mode for channel 23

`pub fn edreq_24(&mut self) -> EDREQ_24_W`[src]

Bit 24 - Enable asynchronous DMA request in stop mode for channel 24

`pub fn edreq_25(&mut self) -> EDREQ_25_W`[src]

Bit 25 - Enable asynchronous DMA request in stop mode for channel 25

`pub fn edreq_26(&mut self) -> EDREQ_26_W`[src]

Bit 26 - Enable asynchronous DMA request in stop mode for channel 26

`pub fn edreq_27(&mut self) -> EDREQ_27_W`[src]

Bit 27 - Enable asynchronous DMA request in stop mode for channel 27

`pub fn edreq_28(&mut self) -> EDREQ_28_W`[src]

Bit 28 - Enable asynchronous DMA request in stop mode for channel 28

`pub fn edreq_29(&mut self) -> EDREQ_29_W`[src]

Bit 29 - Enable asynchronous DMA request in stop mode for channel 29

`pub fn edreq_30(&mut self) -> EDREQ_30_W`[src]

Bit 30 - Enable asynchronous DMA request in stop mode for channel 30

`pub fn edreq_31(&mut self) -> EDREQ_31_W`[src]

Bit 31 - Enable asynchronous DMA request in stop mode for channel 31

`impl W<u8, Reg<u8, _DCHPRI3>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI2>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI1>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI0>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI7>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI6>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI5>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI4>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI11>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI10>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI9>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI8>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI15>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI14>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI13>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI12>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI19>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI18>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI17>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI16>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI23>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI22>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI21>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI20>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI27>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI26>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI25>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI24>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI31>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI30>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI29>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u8, Reg<u8, _DCHPRI28>>`[src]

`pub fn chpri(&mut self) -> CHPRI_W`[src]

Bits 0:3 - Channel n Arbitration Priority

`pub fn dpa(&mut self) -> DPA_W`[src]

Bit 6 - Disable Preempt Ability. This field resets to 0.

`pub fn ecp(&mut self) -> ECP_W`[src]

Bit 7 - Enable Channel Preemption. This field resets to 0.

`impl W<u32, Reg<u32, _TCD0_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD0_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD0_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD0_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD0_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD0_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD0_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD0_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD0_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD0_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD0_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD0_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD0_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD0_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD0_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD1_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD1_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD1_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD1_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD1_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD1_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD1_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD1_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD1_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD1_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD1_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD1_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD1_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD1_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD1_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD2_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD2_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD2_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD2_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD2_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD2_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD2_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD2_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD2_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD2_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD2_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD2_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD2_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD2_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD2_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD3_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD3_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD3_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD3_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD3_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD3_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD3_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD3_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD3_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD3_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD3_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD3_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD3_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD3_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD3_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD4_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD4_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD4_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD4_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD4_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD4_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD4_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD4_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD4_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD4_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD4_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD4_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD4_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD4_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD4_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD5_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD5_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD5_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD5_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD5_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD5_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD5_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD5_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD5_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD5_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD5_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD5_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD5_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD5_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD5_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD6_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD6_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD6_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD6_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD6_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD6_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD6_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD6_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD6_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD6_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD6_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD6_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD6_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD6_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD6_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD7_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD7_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD7_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD7_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD7_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD7_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD7_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD7_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD7_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD7_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD7_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD7_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD7_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD7_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD7_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD8_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD8_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD8_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD8_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD8_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD8_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD8_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD8_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD8_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD8_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD8_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD8_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD8_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD8_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD8_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD9_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD9_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD9_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD9_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD9_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD9_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD9_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD9_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD9_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD9_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD9_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD9_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD9_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD9_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD9_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD10_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD10_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD10_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD10_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD10_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD10_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD10_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD10_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD10_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD10_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD10_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD10_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD10_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD10_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD10_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD11_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD11_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD11_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD11_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD11_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD11_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD11_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD11_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD11_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD11_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD11_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD11_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD11_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD11_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD11_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD12_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD12_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD12_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD12_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD12_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD12_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD12_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD12_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD12_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD12_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD12_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD12_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD12_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD12_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD12_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD13_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD13_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD13_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD13_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD13_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD13_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD13_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD13_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD13_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD13_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD13_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD13_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD13_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD13_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD13_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD14_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD14_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD14_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD14_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD14_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD14_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD14_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD14_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD14_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD14_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD14_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD14_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD14_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD14_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD14_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD15_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD15_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD15_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD15_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD15_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD15_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD15_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD15_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD15_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD15_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD15_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD15_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD15_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD15_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD15_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD16_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD16_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD16_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD16_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD16_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD16_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD16_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD16_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD16_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD16_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD16_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD16_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD16_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD16_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD16_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD17_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD17_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD17_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD17_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD17_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD17_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD17_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD17_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD17_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD17_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD17_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD17_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD17_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD17_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD17_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD18_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD18_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD18_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD18_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD18_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD18_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD18_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD18_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD18_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD18_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD18_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD18_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD18_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD18_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD18_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD19_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD19_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD19_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD19_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD19_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD19_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD19_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD19_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD19_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD19_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD19_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD19_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD19_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD19_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD19_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD20_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD20_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD20_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD20_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD20_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD20_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD20_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD20_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD20_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD20_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD20_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD20_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD20_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD20_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD20_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD21_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD21_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD21_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD21_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD21_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD21_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD21_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD21_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD21_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD21_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD21_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD21_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD21_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD21_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD21_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD22_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD22_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD22_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD22_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD22_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD22_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD22_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD22_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD22_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD22_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD22_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD22_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD22_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD22_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD22_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD23_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD23_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD23_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD23_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD23_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD23_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD23_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD23_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD23_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD23_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD23_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD23_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD23_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD23_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD23_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD24_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD24_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD24_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD24_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD24_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD24_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD24_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD24_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD24_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD24_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD24_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD24_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD24_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD24_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD24_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD25_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD25_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD25_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD25_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD25_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD25_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD25_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD25_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD25_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD25_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD25_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD25_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD25_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD25_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD25_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD26_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD26_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD26_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD26_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD26_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD26_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD26_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD26_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD26_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD26_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD26_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD26_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD26_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD26_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD26_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD27_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD27_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD27_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD27_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD27_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD27_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD27_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD27_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD27_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD27_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD27_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD27_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD27_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD27_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD27_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD28_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD28_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD28_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD28_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD28_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD28_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD28_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD28_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD28_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD28_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD28_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD28_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD28_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD28_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD28_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD29_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD29_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD29_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD29_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD29_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD29_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD29_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD29_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD29_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD29_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD29_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD29_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD29_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD29_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD29_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD30_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD30_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD30_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD30_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD30_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD30_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD30_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD30_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD30_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD30_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD30_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD30_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD30_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD30_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD30_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u32, Reg<u32, _TCD31_SADDR>>`[src]

`pub fn saddr(&mut self) -> SADDR_W`[src]

Bits 0:31 - Source Address

`impl W<u16, Reg<u16, _TCD31_SOFF>>`[src]

`pub fn soff(&mut self) -> SOFF_W`[src]

Bits 0:15 - Source address signed offset

`impl W<u16, Reg<u16, _TCD31_ATTR>>`[src]

`pub fn dsize(&mut self) -> DSIZE_W`[src]

Bits 0:2 - Destination data transfer size

`pub fn dmod(&mut self) -> DMOD_W`[src]

Bits 3:7 - Destination Address Modulo

`pub fn ssize(&mut self) -> SSIZE_W`[src]

Bits 8:10 - Source data transfer size

`pub fn smod(&mut self) -> SMOD_W`[src]

Bits 11:15 - Source Address Modulo

`impl W<u32, Reg<u32, _TCD31_NBYTES_MLNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:31 - Minor Byte Transfer Count

`impl W<u32, Reg<u32, _TCD31_NBYTES_MLOFFNO>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:29 - Minor Byte Transfer Count

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD31_NBYTES_MLOFFYES>>`[src]

`pub fn nbytes(&mut self) -> NBYTES_W`[src]

Bits 0:9 - Minor Byte Transfer Count

`pub fn mloff(&mut self) -> MLOFF_W`[src]

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

`pub fn dmloe(&mut self) -> DMLOE_W`[src]

Bit 30 - Destination Minor Loop Offset enable

`pub fn smloe(&mut self) -> SMLOE_W`[src]

Bit 31 - Source Minor Loop Offset Enable

`impl W<u32, Reg<u32, _TCD31_SLAST>>`[src]

`pub fn slast(&mut self) -> SLAST_W`[src]

Bits 0:31 - Last Source Address Adjustment

`impl W<u32, Reg<u32, _TCD31_DADDR>>`[src]

`pub fn daddr(&mut self) -> DADDR_W`[src]

Bits 0:31 - Destination Address

`impl W<u16, Reg<u16, _TCD31_DOFF>>`[src]

`pub fn doff(&mut self) -> DOFF_W`[src]

Bits 0:15 - Destination Address Signed Offset

`impl W<u16, Reg<u16, _TCD31_CITER_ELINKNO>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:14 - Current Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u16, Reg<u16, _TCD31_CITER_ELINKYES>>`[src]

`pub fn citer(&mut self) -> CITER_W`[src]

Bits 0:8 - Current Major Iteration Count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Minor Loop Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enable channel-to-channel linking on minor-loop complete

`impl W<u32, Reg<u32, _TCD31_DLASTSGA>>`[src]

`pub fn dlastsga(&mut self) -> DLASTSGA_W`[src]

Bits 0:31 - DLASTSGA

`impl W<u16, Reg<u16, _TCD31_CSR>>`[src]

`pub fn start(&mut self) -> START_W`[src]

Bit 0 - Channel Start

`pub fn intmajor(&mut self) -> INTMAJOR_W`[src]

Bit 1 - Enable an interrupt when major iteration count completes.

`pub fn inthalf(&mut self) -> INTHALF_W`[src]

Bit 2 - Enable an interrupt when major counter is half complete.

`pub fn dreq(&mut self) -> DREQ_W`[src]

Bit 3 - Disable Request

`pub fn esg(&mut self) -> ESG_W`[src]

Bit 4 - Enable Scatter/Gather Processing

`pub fn majorelink(&mut self) -> MAJORELINK_W`[src]

Bit 5 - Enable channel-to-channel linking on major loop complete

`pub fn done(&mut self) -> DONE_W`[src]

Bit 7 - Channel Done

`pub fn majorlinkch(&mut self) -> MAJORLINKCH_W`[src]

Bits 8:12 - Major Loop Link Channel Number

`pub fn bwc(&mut self) -> BWC_W`[src]

Bits 14:15 - Bandwidth Control

`impl W<u16, Reg<u16, _TCD31_BITER_ELINKNO>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:14 - Starting Major Iteration Count

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

`impl W<u16, Reg<u16, _TCD31_BITER_ELINKYES>>`[src]

`pub fn biter(&mut self) -> BITER_W`[src]

Bits 0:8 - Starting major iteration count

`pub fn linkch(&mut self) -> LINKCH_W`[src]

Bits 9:13 - Link Channel Number

`pub fn elink(&mut self) -> ELINK_W`[src]

Bit 15 - Enables channel-to-channel linking on minor loop complete

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,`

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,`

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct imxrt1062_dma0::W

Methods

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

impl W<u32, Reg<u32, _CR>>[src]

pub fn edbg(&mut self) -> EDBG_W[src]

pub fn erca(&mut self) -> ERCA_W[src]

pub fn erga(&mut self) -> ERGA_W[src]

pub fn hoe(&mut self) -> HOE_W[src]

pub fn halt(&mut self) -> HALT_W[src]

pub fn clm(&mut self) -> CLM_W[src]

pub fn emlm(&mut self) -> EMLM_W[src]

pub fn grp0pri(&mut self) -> GRP0PRI_W[src]

pub fn grp1pri(&mut self) -> GRP1PRI_W[src]

pub fn ecx(&mut self) -> ECX_W[src]

pub fn cx(&mut self) -> CX_W[src]

impl W<u32, Reg<u32, _ERQ>>[src]

pub fn erq0(&mut self) -> ERQ0_W[src]

pub fn erq1(&mut self) -> ERQ1_W[src]

pub fn erq2(&mut self) -> ERQ2_W[src]

pub fn erq3(&mut self) -> ERQ3_W[src]

pub fn erq4(&mut self) -> ERQ4_W[src]

pub fn erq5(&mut self) -> ERQ5_W[src]

pub fn erq6(&mut self) -> ERQ6_W[src]

pub fn erq7(&mut self) -> ERQ7_W[src]

pub fn erq8(&mut self) -> ERQ8_W[src]

pub fn erq9(&mut self) -> ERQ9_W[src]

pub fn erq10(&mut self) -> ERQ10_W[src]

pub fn erq11(&mut self) -> ERQ11_W[src]

pub fn erq12(&mut self) -> ERQ12_W[src]

pub fn erq13(&mut self) -> ERQ13_W[src]

pub fn erq14(&mut self) -> ERQ14_W[src]

pub fn erq15(&mut self) -> ERQ15_W[src]

pub fn erq16(&mut self) -> ERQ16_W[src]

pub fn erq17(&mut self) -> ERQ17_W[src]

pub fn erq18(&mut self) -> ERQ18_W[src]

pub fn erq19(&mut self) -> ERQ19_W[src]

pub fn erq20(&mut self) -> ERQ20_W[src]

pub fn erq21(&mut self) -> ERQ21_W[src]

pub fn erq22(&mut self) -> ERQ22_W[src]

pub fn erq23(&mut self) -> ERQ23_W[src]

pub fn erq24(&mut self) -> ERQ24_W[src]

pub fn erq25(&mut self) -> ERQ25_W[src]

pub fn erq26(&mut self) -> ERQ26_W[src]

pub fn erq27(&mut self) -> ERQ27_W[src]

pub fn erq28(&mut self) -> ERQ28_W[src]

pub fn erq29(&mut self) -> ERQ29_W[src]

pub fn erq30(&mut self) -> ERQ30_W[src]

pub fn erq31(&mut self) -> ERQ31_W[src]

impl W<u32, Reg<u32, _EEI>>[src]

pub fn eei0(&mut self) -> EEI0_W[src]

pub fn eei1(&mut self) -> EEI1_W[src]

pub fn eei2(&mut self) -> EEI2_W[src]

pub fn eei3(&mut self) -> EEI3_W[src]

pub fn eei4(&mut self) -> EEI4_W[src]

pub fn eei5(&mut self) -> EEI5_W[src]

pub fn eei6(&mut self) -> EEI6_W[src]

pub fn eei7(&mut self) -> EEI7_W[src]

pub fn eei8(&mut self) -> EEI8_W[src]

pub fn eei9(&mut self) -> EEI9_W[src]

pub fn eei10(&mut self) -> EEI10_W[src]

pub fn eei11(&mut self) -> EEI11_W[src]

pub fn eei12(&mut self) -> EEI12_W[src]

pub fn eei13(&mut self) -> EEI13_W[src]

pub fn eei14(&mut self) -> EEI14_W[src]

pub fn eei15(&mut self) -> EEI15_W[src]

pub fn eei16(&mut self) -> EEI16_W[src]

pub fn eei17(&mut self) -> EEI17_W[src]

pub fn eei18(&mut self) -> EEI18_W[src]

pub fn eei19(&mut self) -> EEI19_W[src]

pub fn eei20(&mut self) -> EEI20_W[src]

pub fn eei21(&mut self) -> EEI21_W[src]

pub fn eei22(&mut self) -> EEI22_W[src]

pub fn eei23(&mut self) -> EEI23_W[src]

pub fn eei24(&mut self) -> EEI24_W[src]

pub fn eei25(&mut self) -> EEI25_W[src]

pub fn eei26(&mut self) -> EEI26_W[src]

pub fn eei27(&mut self) -> EEI27_W[src]

pub fn eei28(&mut self) -> EEI28_W[src]

pub fn eei29(&mut self) -> EEI29_W[src]

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

`impl W<u32, Reg<u32, _CR>>`[src]

`pub fn edbg(&mut self) -> EDBG_W`[src]

`pub fn erca(&mut self) -> ERCA_W`[src]

`pub fn erga(&mut self) -> ERGA_W`[src]

`pub fn hoe(&mut self) -> HOE_W`[src]

`pub fn halt(&mut self) -> HALT_W`[src]

`pub fn clm(&mut self) -> CLM_W`[src]

`pub fn emlm(&mut self) -> EMLM_W`[src]

`pub fn grp0pri(&mut self) -> GRP0PRI_W`[src]

`pub fn grp1pri(&mut self) -> GRP1PRI_W`[src]

`pub fn ecx(&mut self) -> ECX_W`[src]

`pub fn cx(&mut self) -> CX_W`[src]

`impl W<u32, Reg<u32, _ERQ>>`[src]

`pub fn erq0(&mut self) -> ERQ0_W`[src]

`pub fn erq1(&mut self) -> ERQ1_W`[src]

`pub fn erq2(&mut self) -> ERQ2_W`[src]

`pub fn erq3(&mut self) -> ERQ3_W`[src]

`pub fn erq4(&mut self) -> ERQ4_W`[src]

`pub fn erq5(&mut self) -> ERQ5_W`[src]

`pub fn erq6(&mut self) -> ERQ6_W`[src]

`pub fn erq7(&mut self) -> ERQ7_W`[src]

`pub fn erq8(&mut self) -> ERQ8_W`[src]

`pub fn erq9(&mut self) -> ERQ9_W`[src]

`pub fn erq10(&mut self) -> ERQ10_W`[src]

`pub fn erq11(&mut self) -> ERQ11_W`[src]

`pub fn erq12(&mut self) -> ERQ12_W`[src]

`pub fn erq13(&mut self) -> ERQ13_W`[src]

`pub fn erq14(&mut self) -> ERQ14_W`[src]

`pub fn erq15(&mut self) -> ERQ15_W`[src]

`pub fn erq16(&mut self) -> ERQ16_W`[src]

`pub fn erq17(&mut self) -> ERQ17_W`[src]

`pub fn erq18(&mut self) -> ERQ18_W`[src]

`pub fn erq19(&mut self) -> ERQ19_W`[src]

`pub fn erq20(&mut self) -> ERQ20_W`[src]

`pub fn erq21(&mut self) -> ERQ21_W`[src]

`pub fn erq22(&mut self) -> ERQ22_W`[src]

`pub fn erq23(&mut self) -> ERQ23_W`[src]

`pub fn erq24(&mut self) -> ERQ24_W`[src]

`pub fn erq25(&mut self) -> ERQ25_W`[src]

`pub fn erq26(&mut self) -> ERQ26_W`[src]

`pub fn erq27(&mut self) -> ERQ27_W`[src]

`pub fn erq28(&mut self) -> ERQ28_W`[src]

`pub fn erq29(&mut self) -> ERQ29_W`[src]

`pub fn erq30(&mut self) -> ERQ30_W`[src]

`pub fn erq31(&mut self) -> ERQ31_W`[src]

`impl W<u32, Reg<u32, _EEI>>`[src]

`pub fn eei0(&mut self) -> EEI0_W`[src]

`pub fn eei1(&mut self) -> EEI1_W`[src]

`pub fn eei2(&mut self) -> EEI2_W`[src]

`pub fn eei3(&mut self) -> EEI3_W`[src]

`pub fn eei4(&mut self) -> EEI4_W`[src]

`pub fn eei5(&mut self) -> EEI5_W`[src]

`pub fn eei6(&mut self) -> EEI6_W`[src]

`pub fn eei7(&mut self) -> EEI7_W`[src]

`pub fn eei8(&mut self) -> EEI8_W`[src]

`pub fn eei9(&mut self) -> EEI9_W`[src]

`pub fn eei10(&mut self) -> EEI10_W`[src]

`pub fn eei11(&mut self) -> EEI11_W`[src]

`pub fn eei12(&mut self) -> EEI12_W`[src]

`pub fn eei13(&mut self) -> EEI13_W`[src]

`pub fn eei14(&mut self) -> EEI14_W`[src]

`pub fn eei15(&mut self) -> EEI15_W`[src]

`pub fn eei16(&mut self) -> EEI16_W`[src]

`pub fn eei17(&mut self) -> EEI17_W`[src]

`pub fn eei18(&mut self) -> EEI18_W`[src]

`pub fn eei19(&mut self) -> EEI19_W`[src]

`pub fn eei20(&mut self) -> EEI20_W`[src]

`pub fn eei21(&mut self) -> EEI21_W`[src]

`pub fn eei22(&mut self) -> EEI22_W`[src]

`pub fn eei23(&mut self) -> EEI23_W`[src]

`pub fn eei24(&mut self) -> EEI24_W`[src]

`pub fn eei25(&mut self) -> EEI25_W`[src]

`pub fn eei26(&mut self) -> EEI26_W`[src]

`pub fn eei27(&mut self) -> EEI27_W`[src]

`pub fn eei28(&mut self) -> EEI28_W`[src]

`pub fn eei29(&mut self) -> EEI29_W`[src]

`pub fn eei30(&mut self) -> EEI30_W`[src]

`pub fn eei31(&mut self) -> EEI31_W`[src]