Struct imxrt1062_dcp::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTRL>>

pub fn channel_interrupt_enable(&mut self) -> CHANNEL_INTERRUPT_ENABLE_W

Bits 0:7 - Per-channel interrupt enable bit

pub fn enable_context_switching(&mut self) -> ENABLE_CONTEXT_SWITCHING_W

Bit 21 - Enable automatic context switching for the channels

pub fn enable_context_caching(&mut self) -> ENABLE_CONTEXT_CACHING_W

Bit 22 - The software must set this bit to enable the caching of contexts between the operations

pub fn gather_residual_writes(&mut self) -> GATHER_RESIDUAL_WRITES_W

Bit 23 - The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for a normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Set this bit to zero to enable a normal DCP operation

impl W<u32, Reg<u32, _CTRL_SET>>

pub fn channel_interrupt_enable(&mut self) -> CHANNEL_INTERRUPT_ENABLE_W

Bits 0:7 - Per-channel interrupt enable bit

pub fn enable_context_switching(&mut self) -> ENABLE_CONTEXT_SWITCHING_W

Bit 21 - Enable automatic context switching for the channels

pub fn enable_context_caching(&mut self) -> ENABLE_CONTEXT_CACHING_W

Bit 22 - The software must set this bit to enable the caching of contexts between the operations

pub fn gather_residual_writes(&mut self) -> GATHER_RESIDUAL_WRITES_W

Bit 23 - The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for a normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Set this bit to zero to enable a normal DCP operation

impl W<u32, Reg<u32, _CTRL_CLR>>

pub fn channel_interrupt_enable(&mut self) -> CHANNEL_INTERRUPT_ENABLE_W

Bits 0:7 - Per-channel interrupt enable bit

pub fn enable_context_switching(&mut self) -> ENABLE_CONTEXT_SWITCHING_W

Bit 21 - Enable automatic context switching for the channels

pub fn enable_context_caching(&mut self) -> ENABLE_CONTEXT_CACHING_W

Bit 22 - The software must set this bit to enable the caching of contexts between the operations

pub fn gather_residual_writes(&mut self) -> GATHER_RESIDUAL_WRITES_W

Bit 23 - The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for a normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Set this bit to zero to enable a normal DCP operation

impl W<u32, Reg<u32, _CTRL_TOG>>

pub fn channel_interrupt_enable(&mut self) -> CHANNEL_INTERRUPT_ENABLE_W

Bits 0:7 - Per-channel interrupt enable bit

pub fn enable_context_switching(&mut self) -> ENABLE_CONTEXT_SWITCHING_W

Bit 21 - Enable automatic context switching for the channels

pub fn enable_context_caching(&mut self) -> ENABLE_CONTEXT_CACHING_W

Bit 22 - The software must set this bit to enable the caching of contexts between the operations

pub fn gather_residual_writes(&mut self) -> GATHER_RESIDUAL_WRITES_W

Bit 23 - The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations

pub fn clkgate(&mut self) -> CLKGATE_W

Bit 30 - This bit must be set to zero for a normal operation

pub fn sftrst(&mut self) -> SFTRST_W

Bit 31 - Set this bit to zero to enable a normal DCP operation

impl W<u32, Reg<u32, _STAT>>

pub fn irq(&mut self) -> IRQ_W

Bits 0:3 - Indicates which channels have pending interrupt requests

impl W<u32, Reg<u32, _STAT_SET>>

pub fn irq(&mut self) -> IRQ_W

Bits 0:3 - Indicates which channels have pending interrupt requests

impl W<u32, Reg<u32, _STAT_CLR>>

pub fn irq(&mut self) -> IRQ_W

Bits 0:3 - Indicates which channels have pending interrupt requests

impl W<u32, Reg<u32, _STAT_TOG>>

pub fn irq(&mut self) -> IRQ_W

Bits 0:3 - Indicates which channels have pending interrupt requests

impl W<u32, Reg<u32, _CHANNELCTRL>>

pub fn enable_channel(&mut self) -> ENABLE_CHANNEL_W

Bits 0:7 - Setting a bit in this field enables the DMA channel associated with it

pub fn high_priority_channel(&mut self) -> HIGH_PRIORITY_CHANNEL_W

Bits 8:15 - Setting a bit in this field causes the corresponding channel to have high-priority arbitration

pub fn ch0_irq_merged(&mut self) -> CH0_IRQ_MERGED_W

Bit 16 - Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt

impl W<u32, Reg<u32, _CHANNELCTRL_SET>>

pub fn enable_channel(&mut self) -> ENABLE_CHANNEL_W

Bits 0:7 - Setting a bit in this field enables the DMA channel associated with it

pub fn high_priority_channel(&mut self) -> HIGH_PRIORITY_CHANNEL_W

Bits 8:15 - Setting a bit in this field causes the corresponding channel to have high-priority arbitration

pub fn ch0_irq_merged(&mut self) -> CH0_IRQ_MERGED_W

Bit 16 - Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt

impl W<u32, Reg<u32, _CHANNELCTRL_CLR>>

pub fn enable_channel(&mut self) -> ENABLE_CHANNEL_W

Bits 0:7 - Setting a bit in this field enables the DMA channel associated with it

pub fn high_priority_channel(&mut self) -> HIGH_PRIORITY_CHANNEL_W

Bits 8:15 - Setting a bit in this field causes the corresponding channel to have high-priority arbitration

pub fn ch0_irq_merged(&mut self) -> CH0_IRQ_MERGED_W

Bit 16 - Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt

impl W<u32, Reg<u32, _CHANNELCTRL_TOG>>

pub fn enable_channel(&mut self) -> ENABLE_CHANNEL_W

Bits 0:7 - Setting a bit in this field enables the DMA channel associated with it

pub fn high_priority_channel(&mut self) -> HIGH_PRIORITY_CHANNEL_W

Bits 8:15 - Setting a bit in this field causes the corresponding channel to have high-priority arbitration

pub fn ch0_irq_merged(&mut self) -> CH0_IRQ_MERGED_W

Bit 16 - Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt

impl W<u32, Reg<u32, _CAPABILITY0>>

pub fn disable_unique_key(&mut self) -> DISABLE_UNIQUE_KEY_W

Bit 29 - Write to a 1 to disable the per-device unique key

pub fn disable_decrypt(&mut self) -> DISABLE_DECRYPT_W

Bit 31 - Write to 1 to disable the decryption

impl W<u32, Reg<u32, _CONTEXT>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Context pointer address

impl W<u32, Reg<u32, _KEY>>

pub fn subword(&mut self) -> SUBWORD_W

Bits 0:1 - Key subword pointer

pub fn index(&mut self) -> INDEX_W

Bits 4:5 - Key index pointer. The valid indices are 0-[number_keys].

impl W<u32, Reg<u32, _KEYDATA>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Word 0 data for the key. This is the least-significant word.

impl W<u32, Reg<u32, _CH0CMDPTR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Pointer to the descriptor structure to be processed for channel 0.

impl W<u32, Reg<u32, _CH0SEMA>>

pub fn increment(&mut self) -> INCREMENT_W

Bits 0:7 - The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected

impl W<u32, Reg<u32, _CH0STAT>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions

impl W<u32, Reg<u32, _CH0STAT_SET>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions

impl W<u32, Reg<u32, _CH0STAT_CLR>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions

impl W<u32, Reg<u32, _CH0STAT_TOG>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions

impl W<u32, Reg<u32, _CH0OPTS>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH0OPTS_SET>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH0OPTS_CLR>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH0OPTS_TOG>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH1CMDPTR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Pointer to the descriptor structure to be processed for channel 1.

impl W<u32, Reg<u32, _CH1SEMA>>

pub fn increment(&mut self) -> INCREMENT_W

Bits 0:7 - The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected

impl W<u32, Reg<u32, _CH1STAT>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH1STAT_SET>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH1STAT_CLR>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH1STAT_TOG>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates the additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH1OPTS>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH1OPTS_SET>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH1OPTS_CLR>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH1OPTS_TOG>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH2CMDPTR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Pointer to the descriptor structure to be processed for channel 2.

impl W<u32, Reg<u32, _CH2SEMA>>

pub fn increment(&mut self) -> INCREMENT_W

Bits 0:7 - The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected

impl W<u32, Reg<u32, _CH2STAT>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH2STAT_SET>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH2STAT_CLR>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH2STAT_TOG>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH2OPTS>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH2OPTS_SET>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH2OPTS_CLR>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH2OPTS_TOG>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH3CMDPTR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:31 - Pointer to the descriptor structure to be processed for channel 3.

impl W<u32, Reg<u32, _CH3SEMA>>

pub fn increment(&mut self) -> INCREMENT_W

Bits 0:7 - The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected

impl W<u32, Reg<u32, _CH3STAT>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH3STAT_SET>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH3STAT_CLR>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH3STAT_TOG>>

pub fn hash_mismatch(&mut self) -> HASH_MISMATCH_W

Bit 1 - This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit

pub fn error_setup(&mut self) -> ERROR_SETUP_W

Bit 2 - This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation)

pub fn error_packet(&mut self) -> ERROR_PACKET_W

Bit 3 - This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod

pub fn error_src(&mut self) -> ERROR_SRC_W

Bit 4 - This bit indicates that a bus error occurred when reading from the source buffer

pub fn error_dst(&mut self) -> ERROR_DST_W

Bit 5 - This bit indicates that a bus error occurred when storing to the destination buffer

pub fn error_pagefault(&mut self) -> ERROR_PAGEFAULT_W

Bit 6 - This bit indicates that a page fault occurred while converting a virtual address to a physical address

pub fn error_code(&mut self) -> ERROR_CODE_W

Bits 16:23 - Indicates additional error codes for some of the error conditions.

impl W<u32, Reg<u32, _CH3OPTS>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH3OPTS_SET>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH3OPTS_CLR>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _CH3OPTS_TOG>>

pub fn recovery_timer(&mut self) -> RECOVERY_TIMER_W

Bits 0:15 - This field indicates the recovery time for the channel

impl W<u32, Reg<u32, _DBGSELECT>>

pub fn index(&mut self) -> INDEX_W

Bits 0:7 - Selects a value to read via the debug data register.

impl W<u32, Reg<u32, _PAGETABLE>>

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - Page table enable control

pub fn flush(&mut self) -> FLUSH_W

Bit 1 - Page table flush control. To flush the TLB, write this bit to 1 and then back to 0.

pub fn base(&mut self) -> BASE_W

Bits 2:31 - Page table base address