Type Definition imxrt1062_can1::mcr::R

type R = R<u32, MCR>;

Reader of register MCR

Methods

impl R

pub fn maxmb(&self) -> MAXMB_R

Bits 0:6 - This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes

pub fn idam(&self) -> IDAM_R

Bits 8:9 - This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below

pub fn aen(&self) -> AEN_R

Bit 12 - This bit is supplied for backwards compatibility reasons

pub fn lprioen(&self) -> LPRIOEN_R

Bit 13 - This bit is provided for backwards compatibility reasons

pub fn irmq(&self) -> IRMQ_R

Bit 16 - This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK

pub fn srxdis(&self) -> SRXDIS_R

Bit 17 - This bit defines whether FlexCAN is allowed to receive frames transmitted by itself

pub fn waksrc(&self) -> WAKSRC_R

Bit 19 - This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up

pub fn lpmack(&self) -> LPMACK_R

Bit 20 - This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode

pub fn wrnen(&self) -> WRNEN_R

Bit 21 - When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register

pub fn slfwak(&self) -> SLFWAK_R

Bit 22 - This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode

pub fn supv(&self) -> SUPV_R

Bit 23 - This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode

pub fn frzack(&self) -> FRZACK_R

Bit 24 - This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped

pub fn softrst(&self) -> SOFTRST_R

Bit 25 - When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers

pub fn wakmsk(&self) -> WAKMSK_R

Bit 26 - This bit enables the Wake Up Interrupt generation.

pub fn notrdy(&self) -> NOTRDY_R

Bit 27 - This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode

pub fn halt(&self) -> HALT_R

Bit 28 - Assertion of this bit puts the FLEXCAN module into Freeze Mode

pub fn rfen(&self) -> RFEN_R

Bit 29 - This bit controls whether the Rx FIFO feature is enabled or not

pub fn frz(&self) -> FRZ_R

Bit 30 - The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level

pub fn mdis(&self) -> MDIS_R

Bit 31 - This bit controls whether FLEXCAN is enabled or not