Struct imxrt1062_adc_etc::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTRL>>

pub fn trig_enable(&mut self) -> TRIG_ENABLE_W

Bits 0:7 - TRIG enable register

pub fn ext0_trig_enable(&mut self) -> EXT0_TRIG_ENABLE_W

Bit 8 - TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger.

pub fn ext0_trig_priority(&mut self) -> EXT0_TRIG_PRIORITY_W

Bits 9:11 - External TSC0 trigger priority, 7 is Highest, 0 is lowest .

pub fn ext1_trig_enable(&mut self) -> EXT1_TRIG_ENABLE_W

Bit 12 - TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger.

pub fn ext1_trig_priority(&mut self) -> EXT1_TRIG_PRIORITY_W

Bits 13:15 - External TSC1 trigger priority, 7 is Highest, 0 is lowest .

pub fn pre_divider(&mut self) -> PRE_DIVIDER_W

Bits 16:23 - Pre-divider for trig delay and interval .

pub fn dma_mode_sel(&mut self) -> DMA_MODE_SEL_W

Bit 29 - 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared

pub fn tsc_bypass(&mut self) -> TSC_BYPASS_W

Bit 30 - 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared.

pub fn softrst(&mut self) -> SOFTRST_W

Bit 31 - Software reset, high active. When write 1 ,all logical will be reset.

impl W<u32, Reg<u32, _DONE0_1_IRQ>>

pub fn trig0_done0(&mut self) -> TRIG0_DONE0_W

Bit 0 - TRIG0 done0 interrupt detection

pub fn trig1_done0(&mut self) -> TRIG1_DONE0_W

Bit 1 - TRIG1 done0 interrupt detection

pub fn trig2_done0(&mut self) -> TRIG2_DONE0_W

Bit 2 - TRIG2 done0 interrupt detection

pub fn trig3_done0(&mut self) -> TRIG3_DONE0_W

Bit 3 - TRIG3 done0 interrupt detection

pub fn trig4_done0(&mut self) -> TRIG4_DONE0_W

Bit 4 - TRIG4 done0 interrupt detection

pub fn trig5_done0(&mut self) -> TRIG5_DONE0_W

Bit 5 - TRIG5 done0 interrupt detection

pub fn trig6_done0(&mut self) -> TRIG6_DONE0_W

Bit 6 - TRIG6 done0 interrupt detection

pub fn trig7_done0(&mut self) -> TRIG7_DONE0_W

Bit 7 - TRIG7 done0 interrupt detection

pub fn trig0_done1(&mut self) -> TRIG0_DONE1_W

Bit 16 - TRIG0 done1 interrupt detection

pub fn trig1_done1(&mut self) -> TRIG1_DONE1_W

Bit 17 - TRIG1 done1 interrupt detection

pub fn trig2_done1(&mut self) -> TRIG2_DONE1_W

Bit 18 - TRIG2 done1 interrupt detection

pub fn trig3_done1(&mut self) -> TRIG3_DONE1_W

Bit 19 - TRIG3 done1 interrupt detection

pub fn trig4_done1(&mut self) -> TRIG4_DONE1_W

Bit 20 - TRIG4 done1 interrupt detection

pub fn trig5_done1(&mut self) -> TRIG5_DONE1_W

Bit 21 - TRIG5 done1 interrupt detection

pub fn trig6_done1(&mut self) -> TRIG6_DONE1_W

Bit 22 - TRIG6 done1 interrupt detection

pub fn trig7_done1(&mut self) -> TRIG7_DONE1_W

Bit 23 - TRIG7 done1 interrupt detection

impl W<u32, Reg<u32, _DONE2_ERR_IRQ>>

pub fn trig0_done2(&mut self) -> TRIG0_DONE2_W

Bit 0 - TRIG0 done2 interrupt detection

pub fn trig1_done2(&mut self) -> TRIG1_DONE2_W

Bit 1 - TRIG1 done2 interrupt detection

pub fn trig2_done2(&mut self) -> TRIG2_DONE2_W

Bit 2 - TRIG2 done2 interrupt detection

pub fn trig3_done2(&mut self) -> TRIG3_DONE2_W

Bit 3 - TRIG3 done2 interrupt detection

pub fn trig4_done2(&mut self) -> TRIG4_DONE2_W

Bit 4 - TRIG4 done2 interrupt detection

pub fn trig5_done2(&mut self) -> TRIG5_DONE2_W

Bit 5 - TRIG5 done2 interrupt detection

pub fn trig6_done2(&mut self) -> TRIG6_DONE2_W

Bit 6 - TRIG6 done2 interrupt detection

pub fn trig7_done2(&mut self) -> TRIG7_DONE2_W

Bit 7 - TRIG7 done2 interrupt detection

pub fn trig0_err(&mut self) -> TRIG0_ERR_W

Bit 16 - TRIG0 error interrupt detection

pub fn trig1_err(&mut self) -> TRIG1_ERR_W

Bit 17 - TRIG1 error interrupt detection

pub fn trig2_err(&mut self) -> TRIG2_ERR_W

Bit 18 - TRIG2 error interrupt detection

pub fn trig3_err(&mut self) -> TRIG3_ERR_W

Bit 19 - TRIG3 error interrupt detection

pub fn trig4_err(&mut self) -> TRIG4_ERR_W

Bit 20 - TRIG4 error interrupt detection

pub fn trig5_err(&mut self) -> TRIG5_ERR_W

Bit 21 - TRIG5 error interrupt detection

pub fn trig6_err(&mut self) -> TRIG6_ERR_W

Bit 22 - TRIG6 error interrupt detection

pub fn trig7_err(&mut self) -> TRIG7_ERR_W

Bit 23 - TRIG7 error interrupt detection

impl W<u32, Reg<u32, _DMA_CTRL>>

pub fn trig0_enable(&mut self) -> TRIG0_ENABLE_W

Bit 0 - When TRIG0 done enable DMA request

pub fn trig1_enable(&mut self) -> TRIG1_ENABLE_W

Bit 1 - When TRIG1 done enable DMA request

pub fn trig2_enable(&mut self) -> TRIG2_ENABLE_W

Bit 2 - When TRIG2 done enable DMA request

pub fn trig3_enable(&mut self) -> TRIG3_ENABLE_W

Bit 3 - When TRIG3 done enable DMA request

pub fn trig4_enable(&mut self) -> TRIG4_ENABLE_W

Bit 4 - When TRIG4 done enable DMA request

pub fn trig5_enable(&mut self) -> TRIG5_ENABLE_W

Bit 5 - When TRIG5 done enable DMA request

pub fn trig6_enable(&mut self) -> TRIG6_ENABLE_W

Bit 6 - When TRIG6 done enable DMA request

pub fn trig7_enable(&mut self) -> TRIG7_ENABLE_W

Bit 7 - When TRIG7 done enable DMA request

pub fn trig0_req(&mut self) -> TRIG0_REQ_W

Bit 16 - When TRIG0 done DMA request detection

pub fn trig1_req(&mut self) -> TRIG1_REQ_W

Bit 17 - When TRIG1 done DMA request detection

pub fn trig2_req(&mut self) -> TRIG2_REQ_W

Bit 18 - When TRIG2 done DMA request detection

pub fn trig3_req(&mut self) -> TRIG3_REQ_W

Bit 19 - When TRIG3 done DMA request detection

pub fn trig4_req(&mut self) -> TRIG4_REQ_W

Bit 20 - When TRIG4 done DMA request detection

pub fn trig5_req(&mut self) -> TRIG5_REQ_W

Bit 21 - When TRIG5 done DMA request detection

pub fn trig6_req(&mut self) -> TRIG6_REQ_W

Bit 22 - When TRIG6 done DMA request detection

pub fn trig7_req(&mut self) -> TRIG7_REQ_W

Bit 23 - When TRIG7 done DMA request detection

impl W<u32, Reg<u32, _TRIG0_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG0_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG0_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG0_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG0_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG0_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG1_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG1_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG1_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG1_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG1_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG1_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG2_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG2_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG2_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG2_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG2_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG2_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG3_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG3_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG3_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG3_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG3_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG3_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG4_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG4_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG4_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG4_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG4_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG4_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG5_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG5_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG5_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG5_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG5_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG5_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG6_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG6_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG6_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG6_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG6_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG6_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE

impl W<u32, Reg<u32, _TRIG7_CTRL>>

pub fn sw_trig(&mut self) -> SW_TRIG_W

Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.

pub fn trig_mode(&mut self) -> TRIG_MODE_W

Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.

pub fn trig_chain(&mut self) -> TRIG_CHAIN_W

Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;

pub fn trig_priority(&mut self) -> TRIG_PRIORITY_W

Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .

pub fn sync_mode(&mut self) -> SYNC_MODE_W

Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode

impl W<u32, Reg<u32, _TRIG7_COUNTER>>

pub fn init_delay(&mut self) -> INIT_DELAY_W

Bits 0:15 - TRIGGER initial delay counter

pub fn sample_interval(&mut self) -> SAMPLE_INTERVAL_W

Bits 16:31 - TRIGGER sampling interval counter

impl W<u32, Reg<u32, _TRIG7_CHAIN_1_0>>

pub fn csel0(&mut self) -> CSEL0_W

Bits 0:3 - CHAIN0 CSEL ADC channel selection

pub fn hwts0(&mut self) -> HWTS0_W

Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection

pub fn b2b0(&mut self) -> B2B0_W

Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie0(&mut self) -> IE0_W

Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

pub fn csel1(&mut self) -> CSEL1_W

Bits 16:19 - CHAIN1 CSEL ADC channel selection

pub fn hwts1(&mut self) -> HWTS1_W

Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection

pub fn b2b1(&mut self) -> B2B1_W

Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger

pub fn ie1(&mut self) -> IE1_W

Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2

impl W<u32, Reg<u32, _TRIG7_CHAIN_3_2>>

pub fn csel2(&mut self) -> CSEL2_W

Bits 0:3 - CHAIN2 CSEL

pub fn hwts2(&mut self) -> HWTS2_W

Bits 4:11 - CHAIN2 HWTS

pub fn b2b2(&mut self) -> B2B2_W

Bit 12 - CHAIN2 B2B

pub fn ie2(&mut self) -> IE2_W

Bits 13:14 - CHAIN2 IE

pub fn csel3(&mut self) -> CSEL3_W

Bits 16:19 - CHAIN3 CSEL

pub fn hwts3(&mut self) -> HWTS3_W

Bits 20:27 - CHAIN3 HWTS

pub fn b2b3(&mut self) -> B2B3_W

Bit 28 - CHAIN3 B2B

pub fn ie3(&mut self) -> IE3_W

Bits 29:30 - CHAIN3 IE

impl W<u32, Reg<u32, _TRIG7_CHAIN_5_4>>

pub fn csel4(&mut self) -> CSEL4_W

Bits 0:3 - CHAIN4 CSEL

pub fn hwts4(&mut self) -> HWTS4_W

Bits 4:11 - CHAIN4 HWTS

pub fn b2b4(&mut self) -> B2B4_W

Bit 12 - CHAIN4 B2B

pub fn ie4(&mut self) -> IE4_W

Bits 13:14 - CHAIN4 IE

pub fn csel5(&mut self) -> CSEL5_W

Bits 16:19 - CHAIN5 CSEL

pub fn hwts5(&mut self) -> HWTS5_W

Bits 20:27 - CHAIN5 HWTS

pub fn b2b5(&mut self) -> B2B5_W

Bit 28 - CHAIN5 B2B

pub fn ie5(&mut self) -> IE5_W

Bits 29:30 - CHAIN5 IE

impl W<u32, Reg<u32, _TRIG7_CHAIN_7_6>>

pub fn csel6(&mut self) -> CSEL6_W

Bits 0:3 - CHAIN6 CSEL

pub fn hwts6(&mut self) -> HWTS6_W

Bits 4:11 - CHAIN6 HWTS

pub fn b2b6(&mut self) -> B2B6_W

Bit 12 - CHAIN6 B2B

pub fn ie6(&mut self) -> IE6_W

Bits 13:14 - CHAIN6 IE

pub fn csel7(&mut self) -> CSEL7_W

Bits 16:19 - CHAIN7 CSEL

pub fn hwts7(&mut self) -> HWTS7_W

Bits 20:27 - CHAIN7 HWTS

pub fn b2b7(&mut self) -> B2B7_W

Bit 28 - CHAIN7 B2B

pub fn ie7(&mut self) -> IE7_W

Bits 29:30 - CHAIN7 IE