imxrt_ral/blocks/imxrt1052/
pxp.rs1#[doc = "PXP v2.0 Register Reference Index"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Control Register 0"]
5 pub CTRL: crate::RWRegister<u32>,
6 #[doc = "Control Register 0"]
7 pub CTRL_SET: crate::RWRegister<u32>,
8 #[doc = "Control Register 0"]
9 pub CTRL_CLR: crate::RWRegister<u32>,
10 #[doc = "Control Register 0"]
11 pub CTRL_TOG: crate::RWRegister<u32>,
12 #[doc = "Status Register"]
13 pub STAT: crate::RWRegister<u32>,
14 #[doc = "Status Register"]
15 pub STAT_SET: crate::RWRegister<u32>,
16 #[doc = "Status Register"]
17 pub STAT_CLR: crate::RWRegister<u32>,
18 #[doc = "Status Register"]
19 pub STAT_TOG: crate::RWRegister<u32>,
20 #[doc = "Output Buffer Control Register"]
21 pub OUT_CTRL: crate::RWRegister<u32>,
22 #[doc = "Output Buffer Control Register"]
23 pub OUT_CTRL_SET: crate::RWRegister<u32>,
24 #[doc = "Output Buffer Control Register"]
25 pub OUT_CTRL_CLR: crate::RWRegister<u32>,
26 #[doc = "Output Buffer Control Register"]
27 pub OUT_CTRL_TOG: crate::RWRegister<u32>,
28 #[doc = "Output Frame Buffer Pointer"]
29 pub OUT_BUF: crate::RWRegister<u32>,
30 _reserved0: [u8; 0x0c],
31 #[doc = "Output Frame Buffer Pointer #2"]
32 pub OUT_BUF2: crate::RWRegister<u32>,
33 _reserved1: [u8; 0x0c],
34 #[doc = "Output Buffer Pitch"]
35 pub OUT_PITCH: crate::RWRegister<u32>,
36 _reserved2: [u8; 0x0c],
37 #[doc = "Output Surface Lower Right Coordinate"]
38 pub OUT_LRC: crate::RWRegister<u32>,
39 _reserved3: [u8; 0x0c],
40 #[doc = "Processed Surface Upper Left Coordinate"]
41 pub OUT_PS_ULC: crate::RWRegister<u32>,
42 _reserved4: [u8; 0x0c],
43 #[doc = "Processed Surface Lower Right Coordinate"]
44 pub OUT_PS_LRC: crate::RWRegister<u32>,
45 _reserved5: [u8; 0x0c],
46 #[doc = "Alpha Surface Upper Left Coordinate"]
47 pub OUT_AS_ULC: crate::RWRegister<u32>,
48 _reserved6: [u8; 0x0c],
49 #[doc = "Alpha Surface Lower Right Coordinate"]
50 pub OUT_AS_LRC: crate::RWRegister<u32>,
51 _reserved7: [u8; 0x0c],
52 #[doc = "Processed Surface (PS) Control Register"]
53 pub PS_CTRL: crate::RWRegister<u32>,
54 #[doc = "Processed Surface (PS) Control Register"]
55 pub PS_CTRL_SET: crate::RWRegister<u32>,
56 #[doc = "Processed Surface (PS) Control Register"]
57 pub PS_CTRL_CLR: crate::RWRegister<u32>,
58 #[doc = "Processed Surface (PS) Control Register"]
59 pub PS_CTRL_TOG: crate::RWRegister<u32>,
60 #[doc = "PS Input Buffer Address"]
61 pub PS_BUF: crate::RWRegister<u32>,
62 _reserved8: [u8; 0x0c],
63 #[doc = "PS U/Cb or 2 Plane UV Input Buffer Address"]
64 pub PS_UBUF: crate::RWRegister<u32>,
65 _reserved9: [u8; 0x0c],
66 #[doc = "PS V/Cr Input Buffer Address"]
67 pub PS_VBUF: crate::RWRegister<u32>,
68 _reserved10: [u8; 0x0c],
69 #[doc = "Processed Surface Pitch"]
70 pub PS_PITCH: crate::RWRegister<u32>,
71 _reserved11: [u8; 0x0c],
72 #[doc = "PS Background Color"]
73 pub PS_BACKGROUND: crate::RWRegister<u32>,
74 _reserved12: [u8; 0x0c],
75 #[doc = "PS Scale Factor Register"]
76 pub PS_SCALE: crate::RWRegister<u32>,
77 _reserved13: [u8; 0x0c],
78 #[doc = "PS Scale Offset Register"]
79 pub PS_OFFSET: crate::RWRegister<u32>,
80 _reserved14: [u8; 0x0c],
81 #[doc = "PS Color Key Low"]
82 pub PS_CLRKEYLOW: crate::RWRegister<u32>,
83 _reserved15: [u8; 0x0c],
84 #[doc = "PS Color Key High"]
85 pub PS_CLRKEYHIGH: crate::RWRegister<u32>,
86 _reserved16: [u8; 0x0c],
87 #[doc = "Alpha Surface Control"]
88 pub AS_CTRL: crate::RWRegister<u32>,
89 _reserved17: [u8; 0x0c],
90 #[doc = "Alpha Surface Buffer Pointer"]
91 pub AS_BUF: crate::RWRegister<u32>,
92 _reserved18: [u8; 0x0c],
93 #[doc = "Alpha Surface Pitch"]
94 pub AS_PITCH: crate::RWRegister<u32>,
95 _reserved19: [u8; 0x0c],
96 #[doc = "Overlay Color Key Low"]
97 pub AS_CLRKEYLOW: crate::RWRegister<u32>,
98 _reserved20: [u8; 0x0c],
99 #[doc = "Overlay Color Key High"]
100 pub AS_CLRKEYHIGH: crate::RWRegister<u32>,
101 _reserved21: [u8; 0x0c],
102 #[doc = "Color Space Conversion Coefficient Register 0"]
103 pub CSC1_COEF0: crate::RWRegister<u32>,
104 _reserved22: [u8; 0x0c],
105 #[doc = "Color Space Conversion Coefficient Register 1"]
106 pub CSC1_COEF1: crate::RWRegister<u32>,
107 _reserved23: [u8; 0x0c],
108 #[doc = "Color Space Conversion Coefficient Register 2"]
109 pub CSC1_COEF2: crate::RWRegister<u32>,
110 _reserved24: [u8; 0x015c],
111 #[doc = "PXP Power Control Register"]
112 pub POWER: crate::RWRegister<u32>,
113 _reserved25: [u8; 0xdc],
114 #[doc = "Next Frame Pointer"]
115 pub NEXT: crate::RWRegister<u32>,
116 _reserved26: [u8; 0x3c],
117 #[doc = "PXP Alpha Engine A Control Register."]
118 pub PORTER_DUFF_CTRL: crate::RWRegister<u32>,
119}
120#[doc = "Control Register 0"]
121pub mod CTRL {
122 #[doc = "Enables PXP operation with specified parameters"]
123 pub mod ENABLE {
124 pub const offset: u32 = 0;
125 pub const mask: u32 = 0x01 << offset;
126 pub mod R {}
127 pub mod W {}
128 pub mod RW {}
129 }
130 #[doc = "Interrupt enable"]
131 pub mod IRQ_ENABLE {
132 pub const offset: u32 = 1;
133 pub const mask: u32 = 0x01 << offset;
134 pub mod R {}
135 pub mod W {}
136 pub mod RW {}
137 }
138 #[doc = "Next command interrupt enable"]
139 pub mod NEXT_IRQ_ENABLE {
140 pub const offset: u32 = 2;
141 pub const mask: u32 = 0x01 << offset;
142 pub mod R {}
143 pub mod W {}
144 pub mod RW {}
145 }
146 #[doc = "Enable handshake with LCD controller"]
147 pub mod ENABLE_LCD_HANDSHAKE {
148 pub const offset: u32 = 4;
149 pub const mask: u32 = 0x01 << offset;
150 pub mod R {}
151 pub mod W {}
152 pub mod RW {}
153 }
154 #[doc = "Indicates the clockwise rotation to be applied at the output buffer"]
155 pub mod ROTATE {
156 pub const offset: u32 = 8;
157 pub const mask: u32 = 0x03 << offset;
158 pub mod R {}
159 pub mod W {}
160 pub mod RW {
161 #[doc = "ROT_0"]
162 pub const ROT_0: u32 = 0;
163 #[doc = "ROT_90"]
164 pub const ROT_90: u32 = 0x01;
165 #[doc = "ROT_180"]
166 pub const ROT_180: u32 = 0x02;
167 #[doc = "ROT_270"]
168 pub const ROT_270: u32 = 0x03;
169 }
170 }
171 #[doc = "Indicates that the output buffer should be flipped horizontally (effect applied before rotation)."]
172 pub mod HFLIP {
173 pub const offset: u32 = 10;
174 pub const mask: u32 = 0x01 << offset;
175 pub mod R {}
176 pub mod W {}
177 pub mod RW {}
178 }
179 #[doc = "Indicates that the output buffer should be flipped vertically (effect applied before rotation)."]
180 pub mod VFLIP {
181 pub const offset: u32 = 11;
182 pub const mask: u32 = 0x01 << offset;
183 pub mod R {}
184 pub mod W {}
185 pub mod RW {}
186 }
187 #[doc = "This bit controls where rotation will occur in the PXP datapath"]
188 pub mod ROT_POS {
189 pub const offset: u32 = 22;
190 pub const mask: u32 = 0x01 << offset;
191 pub mod R {}
192 pub mod W {}
193 pub mod RW {}
194 }
195 #[doc = "Select the block size to process."]
196 pub mod BLOCK_SIZE {
197 pub const offset: u32 = 23;
198 pub const mask: u32 = 0x01 << offset;
199 pub mod R {}
200 pub mod W {}
201 pub mod RW {
202 #[doc = "Process 8x8 pixel blocks."]
203 pub const _8X8: u32 = 0;
204 #[doc = "Process 16x16 pixel blocks."]
205 pub const _16X16: u32 = 0x01;
206 }
207 }
208 #[doc = "Enable the PXP to run continuously"]
209 pub mod EN_REPEAT {
210 pub const offset: u32 = 28;
211 pub const mask: u32 = 0x01 << offset;
212 pub mod R {}
213 pub mod W {}
214 pub mod RW {}
215 }
216 #[doc = "This bit must be set to zero for normal operation"]
217 pub mod CLKGATE {
218 pub const offset: u32 = 30;
219 pub const mask: u32 = 0x01 << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {}
223 }
224 #[doc = "Set this bit to zero to enable normal PXP operation"]
225 pub mod SFTRST {
226 pub const offset: u32 = 31;
227 pub const mask: u32 = 0x01 << offset;
228 pub mod R {}
229 pub mod W {}
230 pub mod RW {}
231 }
232}
233#[doc = "Control Register 0"]
234pub mod CTRL_SET {
235 #[doc = "Enables PXP operation with specified parameters"]
236 pub mod ENABLE {
237 pub const offset: u32 = 0;
238 pub const mask: u32 = 0x01 << offset;
239 pub mod R {}
240 pub mod W {}
241 pub mod RW {}
242 }
243 #[doc = "Interrupt enable"]
244 pub mod IRQ_ENABLE {
245 pub const offset: u32 = 1;
246 pub const mask: u32 = 0x01 << offset;
247 pub mod R {}
248 pub mod W {}
249 pub mod RW {}
250 }
251 #[doc = "Next command interrupt enable"]
252 pub mod NEXT_IRQ_ENABLE {
253 pub const offset: u32 = 2;
254 pub const mask: u32 = 0x01 << offset;
255 pub mod R {}
256 pub mod W {}
257 pub mod RW {}
258 }
259 #[doc = "Enable handshake with LCD controller"]
260 pub mod ENABLE_LCD_HANDSHAKE {
261 pub const offset: u32 = 4;
262 pub const mask: u32 = 0x01 << offset;
263 pub mod R {}
264 pub mod W {}
265 pub mod RW {}
266 }
267 #[doc = "Indicates the clockwise rotation to be applied at the output buffer"]
268 pub mod ROTATE {
269 pub const offset: u32 = 8;
270 pub const mask: u32 = 0x03 << offset;
271 pub mod R {}
272 pub mod W {}
273 pub mod RW {
274 #[doc = "ROT_0"]
275 pub const ROT_0: u32 = 0;
276 #[doc = "ROT_90"]
277 pub const ROT_90: u32 = 0x01;
278 #[doc = "ROT_180"]
279 pub const ROT_180: u32 = 0x02;
280 #[doc = "ROT_270"]
281 pub const ROT_270: u32 = 0x03;
282 }
283 }
284 #[doc = "Indicates that the output buffer should be flipped horizontally (effect applied before rotation)."]
285 pub mod HFLIP {
286 pub const offset: u32 = 10;
287 pub const mask: u32 = 0x01 << offset;
288 pub mod R {}
289 pub mod W {}
290 pub mod RW {}
291 }
292 #[doc = "Indicates that the output buffer should be flipped vertically (effect applied before rotation)."]
293 pub mod VFLIP {
294 pub const offset: u32 = 11;
295 pub const mask: u32 = 0x01 << offset;
296 pub mod R {}
297 pub mod W {}
298 pub mod RW {}
299 }
300 #[doc = "This bit controls where rotation will occur in the PXP datapath"]
301 pub mod ROT_POS {
302 pub const offset: u32 = 22;
303 pub const mask: u32 = 0x01 << offset;
304 pub mod R {}
305 pub mod W {}
306 pub mod RW {}
307 }
308 #[doc = "Select the block size to process."]
309 pub mod BLOCK_SIZE {
310 pub const offset: u32 = 23;
311 pub const mask: u32 = 0x01 << offset;
312 pub mod R {}
313 pub mod W {}
314 pub mod RW {
315 #[doc = "Process 8x8 pixel blocks."]
316 pub const _8X8: u32 = 0;
317 #[doc = "Process 16x16 pixel blocks."]
318 pub const _16X16: u32 = 0x01;
319 }
320 }
321 #[doc = "Enable the PXP to run continuously"]
322 pub mod EN_REPEAT {
323 pub const offset: u32 = 28;
324 pub const mask: u32 = 0x01 << offset;
325 pub mod R {}
326 pub mod W {}
327 pub mod RW {}
328 }
329 #[doc = "This bit must be set to zero for normal operation"]
330 pub mod CLKGATE {
331 pub const offset: u32 = 30;
332 pub const mask: u32 = 0x01 << offset;
333 pub mod R {}
334 pub mod W {}
335 pub mod RW {}
336 }
337 #[doc = "Set this bit to zero to enable normal PXP operation"]
338 pub mod SFTRST {
339 pub const offset: u32 = 31;
340 pub const mask: u32 = 0x01 << offset;
341 pub mod R {}
342 pub mod W {}
343 pub mod RW {}
344 }
345}
346#[doc = "Control Register 0"]
347pub mod CTRL_CLR {
348 #[doc = "Enables PXP operation with specified parameters"]
349 pub mod ENABLE {
350 pub const offset: u32 = 0;
351 pub const mask: u32 = 0x01 << offset;
352 pub mod R {}
353 pub mod W {}
354 pub mod RW {}
355 }
356 #[doc = "Interrupt enable"]
357 pub mod IRQ_ENABLE {
358 pub const offset: u32 = 1;
359 pub const mask: u32 = 0x01 << offset;
360 pub mod R {}
361 pub mod W {}
362 pub mod RW {}
363 }
364 #[doc = "Next command interrupt enable"]
365 pub mod NEXT_IRQ_ENABLE {
366 pub const offset: u32 = 2;
367 pub const mask: u32 = 0x01 << offset;
368 pub mod R {}
369 pub mod W {}
370 pub mod RW {}
371 }
372 #[doc = "Enable handshake with LCD controller"]
373 pub mod ENABLE_LCD_HANDSHAKE {
374 pub const offset: u32 = 4;
375 pub const mask: u32 = 0x01 << offset;
376 pub mod R {}
377 pub mod W {}
378 pub mod RW {}
379 }
380 #[doc = "Indicates the clockwise rotation to be applied at the output buffer"]
381 pub mod ROTATE {
382 pub const offset: u32 = 8;
383 pub const mask: u32 = 0x03 << offset;
384 pub mod R {}
385 pub mod W {}
386 pub mod RW {
387 #[doc = "ROT_0"]
388 pub const ROT_0: u32 = 0;
389 #[doc = "ROT_90"]
390 pub const ROT_90: u32 = 0x01;
391 #[doc = "ROT_180"]
392 pub const ROT_180: u32 = 0x02;
393 #[doc = "ROT_270"]
394 pub const ROT_270: u32 = 0x03;
395 }
396 }
397 #[doc = "Indicates that the output buffer should be flipped horizontally (effect applied before rotation)."]
398 pub mod HFLIP {
399 pub const offset: u32 = 10;
400 pub const mask: u32 = 0x01 << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {}
404 }
405 #[doc = "Indicates that the output buffer should be flipped vertically (effect applied before rotation)."]
406 pub mod VFLIP {
407 pub const offset: u32 = 11;
408 pub const mask: u32 = 0x01 << offset;
409 pub mod R {}
410 pub mod W {}
411 pub mod RW {}
412 }
413 #[doc = "This bit controls where rotation will occur in the PXP datapath"]
414 pub mod ROT_POS {
415 pub const offset: u32 = 22;
416 pub const mask: u32 = 0x01 << offset;
417 pub mod R {}
418 pub mod W {}
419 pub mod RW {}
420 }
421 #[doc = "Select the block size to process."]
422 pub mod BLOCK_SIZE {
423 pub const offset: u32 = 23;
424 pub const mask: u32 = 0x01 << offset;
425 pub mod R {}
426 pub mod W {}
427 pub mod RW {
428 #[doc = "Process 8x8 pixel blocks."]
429 pub const _8X8: u32 = 0;
430 #[doc = "Process 16x16 pixel blocks."]
431 pub const _16X16: u32 = 0x01;
432 }
433 }
434 #[doc = "Enable the PXP to run continuously"]
435 pub mod EN_REPEAT {
436 pub const offset: u32 = 28;
437 pub const mask: u32 = 0x01 << offset;
438 pub mod R {}
439 pub mod W {}
440 pub mod RW {}
441 }
442 #[doc = "This bit must be set to zero for normal operation"]
443 pub mod CLKGATE {
444 pub const offset: u32 = 30;
445 pub const mask: u32 = 0x01 << offset;
446 pub mod R {}
447 pub mod W {}
448 pub mod RW {}
449 }
450 #[doc = "Set this bit to zero to enable normal PXP operation"]
451 pub mod SFTRST {
452 pub const offset: u32 = 31;
453 pub const mask: u32 = 0x01 << offset;
454 pub mod R {}
455 pub mod W {}
456 pub mod RW {}
457 }
458}
459#[doc = "Control Register 0"]
460pub mod CTRL_TOG {
461 #[doc = "Enables PXP operation with specified parameters"]
462 pub mod ENABLE {
463 pub const offset: u32 = 0;
464 pub const mask: u32 = 0x01 << offset;
465 pub mod R {}
466 pub mod W {}
467 pub mod RW {}
468 }
469 #[doc = "Interrupt enable"]
470 pub mod IRQ_ENABLE {
471 pub const offset: u32 = 1;
472 pub const mask: u32 = 0x01 << offset;
473 pub mod R {}
474 pub mod W {}
475 pub mod RW {}
476 }
477 #[doc = "Next command interrupt enable"]
478 pub mod NEXT_IRQ_ENABLE {
479 pub const offset: u32 = 2;
480 pub const mask: u32 = 0x01 << offset;
481 pub mod R {}
482 pub mod W {}
483 pub mod RW {}
484 }
485 #[doc = "Enable handshake with LCD controller"]
486 pub mod ENABLE_LCD_HANDSHAKE {
487 pub const offset: u32 = 4;
488 pub const mask: u32 = 0x01 << offset;
489 pub mod R {}
490 pub mod W {}
491 pub mod RW {}
492 }
493 #[doc = "Indicates the clockwise rotation to be applied at the output buffer"]
494 pub mod ROTATE {
495 pub const offset: u32 = 8;
496 pub const mask: u32 = 0x03 << offset;
497 pub mod R {}
498 pub mod W {}
499 pub mod RW {
500 #[doc = "ROT_0"]
501 pub const ROT_0: u32 = 0;
502 #[doc = "ROT_90"]
503 pub const ROT_90: u32 = 0x01;
504 #[doc = "ROT_180"]
505 pub const ROT_180: u32 = 0x02;
506 #[doc = "ROT_270"]
507 pub const ROT_270: u32 = 0x03;
508 }
509 }
510 #[doc = "Indicates that the output buffer should be flipped horizontally (effect applied before rotation)."]
511 pub mod HFLIP {
512 pub const offset: u32 = 10;
513 pub const mask: u32 = 0x01 << offset;
514 pub mod R {}
515 pub mod W {}
516 pub mod RW {}
517 }
518 #[doc = "Indicates that the output buffer should be flipped vertically (effect applied before rotation)."]
519 pub mod VFLIP {
520 pub const offset: u32 = 11;
521 pub const mask: u32 = 0x01 << offset;
522 pub mod R {}
523 pub mod W {}
524 pub mod RW {}
525 }
526 #[doc = "This bit controls where rotation will occur in the PXP datapath"]
527 pub mod ROT_POS {
528 pub const offset: u32 = 22;
529 pub const mask: u32 = 0x01 << offset;
530 pub mod R {}
531 pub mod W {}
532 pub mod RW {}
533 }
534 #[doc = "Select the block size to process."]
535 pub mod BLOCK_SIZE {
536 pub const offset: u32 = 23;
537 pub const mask: u32 = 0x01 << offset;
538 pub mod R {}
539 pub mod W {}
540 pub mod RW {
541 #[doc = "Process 8x8 pixel blocks."]
542 pub const _8X8: u32 = 0;
543 #[doc = "Process 16x16 pixel blocks."]
544 pub const _16X16: u32 = 0x01;
545 }
546 }
547 #[doc = "Enable the PXP to run continuously"]
548 pub mod EN_REPEAT {
549 pub const offset: u32 = 28;
550 pub const mask: u32 = 0x01 << offset;
551 pub mod R {}
552 pub mod W {}
553 pub mod RW {}
554 }
555 #[doc = "This bit must be set to zero for normal operation"]
556 pub mod CLKGATE {
557 pub const offset: u32 = 30;
558 pub const mask: u32 = 0x01 << offset;
559 pub mod R {}
560 pub mod W {}
561 pub mod RW {}
562 }
563 #[doc = "Set this bit to zero to enable normal PXP operation"]
564 pub mod SFTRST {
565 pub const offset: u32 = 31;
566 pub const mask: u32 = 0x01 << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {}
570 }
571}
572#[doc = "Status Register"]
573pub mod STAT {
574 #[doc = "Indicates current PXP interrupt status"]
575 pub mod IRQ {
576 pub const offset: u32 = 0;
577 pub const mask: u32 = 0x01 << offset;
578 pub mod R {}
579 pub mod W {}
580 pub mod RW {}
581 }
582 #[doc = "Indicates PXP encountered an AXI write error and processing has been terminated."]
583 pub mod AXI_WRITE_ERROR {
584 pub const offset: u32 = 1;
585 pub const mask: u32 = 0x01 << offset;
586 pub mod R {}
587 pub mod W {}
588 pub mod RW {}
589 }
590 #[doc = "Indicates PXP encountered an AXI read error and processing has been terminated."]
591 pub mod AXI_READ_ERROR {
592 pub const offset: u32 = 2;
593 pub const mask: u32 = 0x01 << offset;
594 pub mod R {}
595 pub mod W {}
596 pub mod RW {}
597 }
598 #[doc = "Indicates that a command issued with the \"Next Command\" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register"]
599 pub mod NEXT_IRQ {
600 pub const offset: u32 = 3;
601 pub const mask: u32 = 0x01 << offset;
602 pub mod R {}
603 pub mod W {}
604 pub mod RW {}
605 }
606 #[doc = "Indicates the AXI ID of the failing bus operation."]
607 pub mod AXI_ERROR_ID {
608 pub const offset: u32 = 4;
609 pub const mask: u32 = 0x0f << offset;
610 pub mod R {}
611 pub mod W {}
612 pub mod RW {}
613 }
614 #[doc = "Indicates that the LUT DMA transfer has completed."]
615 pub mod LUT_DMA_LOAD_DONE_IRQ {
616 pub const offset: u32 = 8;
617 pub const mask: u32 = 0x01 << offset;
618 pub mod R {}
619 pub mod W {}
620 pub mod RW {}
621 }
622 #[doc = "Indicates the X coordinate of the block currently being rendered."]
623 pub mod BLOCKY {
624 pub const offset: u32 = 16;
625 pub const mask: u32 = 0xff << offset;
626 pub mod R {}
627 pub mod W {}
628 pub mod RW {}
629 }
630 #[doc = "Indicates the X coordinate of the block currently being rendered."]
631 pub mod BLOCKX {
632 pub const offset: u32 = 24;
633 pub const mask: u32 = 0xff << offset;
634 pub mod R {}
635 pub mod W {}
636 pub mod RW {}
637 }
638}
639#[doc = "Status Register"]
640pub mod STAT_SET {
641 #[doc = "Indicates current PXP interrupt status"]
642 pub mod IRQ {
643 pub const offset: u32 = 0;
644 pub const mask: u32 = 0x01 << offset;
645 pub mod R {}
646 pub mod W {}
647 pub mod RW {}
648 }
649 #[doc = "Indicates PXP encountered an AXI write error and processing has been terminated."]
650 pub mod AXI_WRITE_ERROR {
651 pub const offset: u32 = 1;
652 pub const mask: u32 = 0x01 << offset;
653 pub mod R {}
654 pub mod W {}
655 pub mod RW {}
656 }
657 #[doc = "Indicates PXP encountered an AXI read error and processing has been terminated."]
658 pub mod AXI_READ_ERROR {
659 pub const offset: u32 = 2;
660 pub const mask: u32 = 0x01 << offset;
661 pub mod R {}
662 pub mod W {}
663 pub mod RW {}
664 }
665 #[doc = "Indicates that a command issued with the \"Next Command\" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register"]
666 pub mod NEXT_IRQ {
667 pub const offset: u32 = 3;
668 pub const mask: u32 = 0x01 << offset;
669 pub mod R {}
670 pub mod W {}
671 pub mod RW {}
672 }
673 #[doc = "Indicates the AXI ID of the failing bus operation."]
674 pub mod AXI_ERROR_ID {
675 pub const offset: u32 = 4;
676 pub const mask: u32 = 0x0f << offset;
677 pub mod R {}
678 pub mod W {}
679 pub mod RW {}
680 }
681 #[doc = "Indicates that the LUT DMA transfer has completed."]
682 pub mod LUT_DMA_LOAD_DONE_IRQ {
683 pub const offset: u32 = 8;
684 pub const mask: u32 = 0x01 << offset;
685 pub mod R {}
686 pub mod W {}
687 pub mod RW {}
688 }
689 #[doc = "Indicates the X coordinate of the block currently being rendered."]
690 pub mod BLOCKY {
691 pub const offset: u32 = 16;
692 pub const mask: u32 = 0xff << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {}
696 }
697 #[doc = "Indicates the X coordinate of the block currently being rendered."]
698 pub mod BLOCKX {
699 pub const offset: u32 = 24;
700 pub const mask: u32 = 0xff << offset;
701 pub mod R {}
702 pub mod W {}
703 pub mod RW {}
704 }
705}
706#[doc = "Status Register"]
707pub mod STAT_CLR {
708 #[doc = "Indicates current PXP interrupt status"]
709 pub mod IRQ {
710 pub const offset: u32 = 0;
711 pub const mask: u32 = 0x01 << offset;
712 pub mod R {}
713 pub mod W {}
714 pub mod RW {}
715 }
716 #[doc = "Indicates PXP encountered an AXI write error and processing has been terminated."]
717 pub mod AXI_WRITE_ERROR {
718 pub const offset: u32 = 1;
719 pub const mask: u32 = 0x01 << offset;
720 pub mod R {}
721 pub mod W {}
722 pub mod RW {}
723 }
724 #[doc = "Indicates PXP encountered an AXI read error and processing has been terminated."]
725 pub mod AXI_READ_ERROR {
726 pub const offset: u32 = 2;
727 pub const mask: u32 = 0x01 << offset;
728 pub mod R {}
729 pub mod W {}
730 pub mod RW {}
731 }
732 #[doc = "Indicates that a command issued with the \"Next Command\" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register"]
733 pub mod NEXT_IRQ {
734 pub const offset: u32 = 3;
735 pub const mask: u32 = 0x01 << offset;
736 pub mod R {}
737 pub mod W {}
738 pub mod RW {}
739 }
740 #[doc = "Indicates the AXI ID of the failing bus operation."]
741 pub mod AXI_ERROR_ID {
742 pub const offset: u32 = 4;
743 pub const mask: u32 = 0x0f << offset;
744 pub mod R {}
745 pub mod W {}
746 pub mod RW {}
747 }
748 #[doc = "Indicates that the LUT DMA transfer has completed."]
749 pub mod LUT_DMA_LOAD_DONE_IRQ {
750 pub const offset: u32 = 8;
751 pub const mask: u32 = 0x01 << offset;
752 pub mod R {}
753 pub mod W {}
754 pub mod RW {}
755 }
756 #[doc = "Indicates the X coordinate of the block currently being rendered."]
757 pub mod BLOCKY {
758 pub const offset: u32 = 16;
759 pub const mask: u32 = 0xff << offset;
760 pub mod R {}
761 pub mod W {}
762 pub mod RW {}
763 }
764 #[doc = "Indicates the X coordinate of the block currently being rendered."]
765 pub mod BLOCKX {
766 pub const offset: u32 = 24;
767 pub const mask: u32 = 0xff << offset;
768 pub mod R {}
769 pub mod W {}
770 pub mod RW {}
771 }
772}
773#[doc = "Status Register"]
774pub mod STAT_TOG {
775 #[doc = "Indicates current PXP interrupt status"]
776 pub mod IRQ {
777 pub const offset: u32 = 0;
778 pub const mask: u32 = 0x01 << offset;
779 pub mod R {}
780 pub mod W {}
781 pub mod RW {}
782 }
783 #[doc = "Indicates PXP encountered an AXI write error and processing has been terminated."]
784 pub mod AXI_WRITE_ERROR {
785 pub const offset: u32 = 1;
786 pub const mask: u32 = 0x01 << offset;
787 pub mod R {}
788 pub mod W {}
789 pub mod RW {}
790 }
791 #[doc = "Indicates PXP encountered an AXI read error and processing has been terminated."]
792 pub mod AXI_READ_ERROR {
793 pub const offset: u32 = 2;
794 pub const mask: u32 = 0x01 << offset;
795 pub mod R {}
796 pub mod W {}
797 pub mod RW {}
798 }
799 #[doc = "Indicates that a command issued with the \"Next Command\" functionality has been issued and that a new command may be initiated with a write to the PXP_NEXT register"]
800 pub mod NEXT_IRQ {
801 pub const offset: u32 = 3;
802 pub const mask: u32 = 0x01 << offset;
803 pub mod R {}
804 pub mod W {}
805 pub mod RW {}
806 }
807 #[doc = "Indicates the AXI ID of the failing bus operation."]
808 pub mod AXI_ERROR_ID {
809 pub const offset: u32 = 4;
810 pub const mask: u32 = 0x0f << offset;
811 pub mod R {}
812 pub mod W {}
813 pub mod RW {}
814 }
815 #[doc = "Indicates that the LUT DMA transfer has completed."]
816 pub mod LUT_DMA_LOAD_DONE_IRQ {
817 pub const offset: u32 = 8;
818 pub const mask: u32 = 0x01 << offset;
819 pub mod R {}
820 pub mod W {}
821 pub mod RW {}
822 }
823 #[doc = "Indicates the X coordinate of the block currently being rendered."]
824 pub mod BLOCKY {
825 pub const offset: u32 = 16;
826 pub const mask: u32 = 0xff << offset;
827 pub mod R {}
828 pub mod W {}
829 pub mod RW {}
830 }
831 #[doc = "Indicates the X coordinate of the block currently being rendered."]
832 pub mod BLOCKX {
833 pub const offset: u32 = 24;
834 pub const mask: u32 = 0xff << offset;
835 pub mod R {}
836 pub mod W {}
837 pub mod RW {}
838 }
839}
840#[doc = "Output Buffer Control Register"]
841pub mod OUT_CTRL {
842 #[doc = "Output framebuffer format"]
843 pub mod FORMAT {
844 pub const offset: u32 = 0;
845 pub const mask: u32 = 0x1f << offset;
846 pub mod R {}
847 pub mod W {}
848 pub mod RW {
849 #[doc = "32-bit pixels"]
850 pub const ARGB8888: u32 = 0;
851 #[doc = "32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)"]
852 pub const RGB888: u32 = 0x04;
853 #[doc = "24-bit pixels (packed 24-bit format)"]
854 pub const RGB888P: u32 = 0x05;
855 #[doc = "16-bit pixels"]
856 pub const ARGB1555: u32 = 0x08;
857 #[doc = "16-bit pixels"]
858 pub const ARGB4444: u32 = 0x09;
859 #[doc = "16-bit pixels"]
860 pub const RGB555: u32 = 0x0c;
861 #[doc = "16-bit pixels"]
862 pub const RGB444: u32 = 0x0d;
863 #[doc = "16-bit pixels"]
864 pub const RGB565: u32 = 0x0e;
865 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
866 pub const YUV1P444: u32 = 0x10;
867 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
868 pub const UYVY1P422: u32 = 0x12;
869 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
870 pub const VYUY1P422: u32 = 0x13;
871 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
872 pub const Y8: u32 = 0x14;
873 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
874 pub const Y4: u32 = 0x15;
875 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
876 pub const YUV2P422: u32 = 0x18;
877 #[doc = "16-bit pixels (2-plane UV)"]
878 pub const YUV2P420: u32 = 0x19;
879 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
880 pub const YVU2P422: u32 = 0x1a;
881 #[doc = "16-bit pixels (2-plane VU)"]
882 pub const YVU2P420: u32 = 0x1b;
883 }
884 }
885 #[doc = "Determines how the PXP writes it's output data"]
886 pub mod INTERLACED_OUTPUT {
887 pub const offset: u32 = 8;
888 pub const mask: u32 = 0x03 << offset;
889 pub mod R {}
890 pub mod W {}
891 pub mod RW {
892 #[doc = "All data written in progressive format to the OUTBUF Pointer."]
893 pub const PROGRESSIVE: u32 = 0;
894 #[doc = "Interlaced output: only data for field 0 is written to the OUTBUF Pointer."]
895 pub const FIELD0: u32 = 0x01;
896 #[doc = "Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer."]
897 pub const FIELD1: u32 = 0x02;
898 #[doc = "Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2."]
899 pub const INTERLACED: u32 = 0x03;
900 }
901 }
902 #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"]
903 pub mod ALPHA_OUTPUT {
904 pub const offset: u32 = 23;
905 pub const mask: u32 = 0x01 << offset;
906 pub mod R {}
907 pub mod W {}
908 pub mod RW {}
909 }
910 #[doc = "When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline"]
911 pub mod ALPHA {
912 pub const offset: u32 = 24;
913 pub const mask: u32 = 0xff << offset;
914 pub mod R {}
915 pub mod W {}
916 pub mod RW {}
917 }
918}
919#[doc = "Output Buffer Control Register"]
920pub mod OUT_CTRL_SET {
921 #[doc = "Output framebuffer format"]
922 pub mod FORMAT {
923 pub const offset: u32 = 0;
924 pub const mask: u32 = 0x1f << offset;
925 pub mod R {}
926 pub mod W {}
927 pub mod RW {
928 #[doc = "32-bit pixels"]
929 pub const ARGB8888: u32 = 0;
930 #[doc = "32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)"]
931 pub const RGB888: u32 = 0x04;
932 #[doc = "24-bit pixels (packed 24-bit format)"]
933 pub const RGB888P: u32 = 0x05;
934 #[doc = "16-bit pixels"]
935 pub const ARGB1555: u32 = 0x08;
936 #[doc = "16-bit pixels"]
937 pub const ARGB4444: u32 = 0x09;
938 #[doc = "16-bit pixels"]
939 pub const RGB555: u32 = 0x0c;
940 #[doc = "16-bit pixels"]
941 pub const RGB444: u32 = 0x0d;
942 #[doc = "16-bit pixels"]
943 pub const RGB565: u32 = 0x0e;
944 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
945 pub const YUV1P444: u32 = 0x10;
946 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
947 pub const UYVY1P422: u32 = 0x12;
948 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
949 pub const VYUY1P422: u32 = 0x13;
950 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
951 pub const Y8: u32 = 0x14;
952 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
953 pub const Y4: u32 = 0x15;
954 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
955 pub const YUV2P422: u32 = 0x18;
956 #[doc = "16-bit pixels (2-plane UV)"]
957 pub const YUV2P420: u32 = 0x19;
958 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
959 pub const YVU2P422: u32 = 0x1a;
960 #[doc = "16-bit pixels (2-plane VU)"]
961 pub const YVU2P420: u32 = 0x1b;
962 }
963 }
964 #[doc = "Determines how the PXP writes it's output data"]
965 pub mod INTERLACED_OUTPUT {
966 pub const offset: u32 = 8;
967 pub const mask: u32 = 0x03 << offset;
968 pub mod R {}
969 pub mod W {}
970 pub mod RW {
971 #[doc = "All data written in progressive format to the OUTBUF Pointer."]
972 pub const PROGRESSIVE: u32 = 0;
973 #[doc = "Interlaced output: only data for field 0 is written to the OUTBUF Pointer."]
974 pub const FIELD0: u32 = 0x01;
975 #[doc = "Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer."]
976 pub const FIELD1: u32 = 0x02;
977 #[doc = "Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2."]
978 pub const INTERLACED: u32 = 0x03;
979 }
980 }
981 #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"]
982 pub mod ALPHA_OUTPUT {
983 pub const offset: u32 = 23;
984 pub const mask: u32 = 0x01 << offset;
985 pub mod R {}
986 pub mod W {}
987 pub mod RW {}
988 }
989 #[doc = "When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline"]
990 pub mod ALPHA {
991 pub const offset: u32 = 24;
992 pub const mask: u32 = 0xff << offset;
993 pub mod R {}
994 pub mod W {}
995 pub mod RW {}
996 }
997}
998#[doc = "Output Buffer Control Register"]
999pub mod OUT_CTRL_CLR {
1000 #[doc = "Output framebuffer format"]
1001 pub mod FORMAT {
1002 pub const offset: u32 = 0;
1003 pub const mask: u32 = 0x1f << offset;
1004 pub mod R {}
1005 pub mod W {}
1006 pub mod RW {
1007 #[doc = "32-bit pixels"]
1008 pub const ARGB8888: u32 = 0;
1009 #[doc = "32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)"]
1010 pub const RGB888: u32 = 0x04;
1011 #[doc = "24-bit pixels (packed 24-bit format)"]
1012 pub const RGB888P: u32 = 0x05;
1013 #[doc = "16-bit pixels"]
1014 pub const ARGB1555: u32 = 0x08;
1015 #[doc = "16-bit pixels"]
1016 pub const ARGB4444: u32 = 0x09;
1017 #[doc = "16-bit pixels"]
1018 pub const RGB555: u32 = 0x0c;
1019 #[doc = "16-bit pixels"]
1020 pub const RGB444: u32 = 0x0d;
1021 #[doc = "16-bit pixels"]
1022 pub const RGB565: u32 = 0x0e;
1023 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
1024 pub const YUV1P444: u32 = 0x10;
1025 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
1026 pub const UYVY1P422: u32 = 0x12;
1027 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
1028 pub const VYUY1P422: u32 = 0x13;
1029 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
1030 pub const Y8: u32 = 0x14;
1031 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
1032 pub const Y4: u32 = 0x15;
1033 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
1034 pub const YUV2P422: u32 = 0x18;
1035 #[doc = "16-bit pixels (2-plane UV)"]
1036 pub const YUV2P420: u32 = 0x19;
1037 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
1038 pub const YVU2P422: u32 = 0x1a;
1039 #[doc = "16-bit pixels (2-plane VU)"]
1040 pub const YVU2P420: u32 = 0x1b;
1041 }
1042 }
1043 #[doc = "Determines how the PXP writes it's output data"]
1044 pub mod INTERLACED_OUTPUT {
1045 pub const offset: u32 = 8;
1046 pub const mask: u32 = 0x03 << offset;
1047 pub mod R {}
1048 pub mod W {}
1049 pub mod RW {
1050 #[doc = "All data written in progressive format to the OUTBUF Pointer."]
1051 pub const PROGRESSIVE: u32 = 0;
1052 #[doc = "Interlaced output: only data for field 0 is written to the OUTBUF Pointer."]
1053 pub const FIELD0: u32 = 0x01;
1054 #[doc = "Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer."]
1055 pub const FIELD1: u32 = 0x02;
1056 #[doc = "Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2."]
1057 pub const INTERLACED: u32 = 0x03;
1058 }
1059 }
1060 #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"]
1061 pub mod ALPHA_OUTPUT {
1062 pub const offset: u32 = 23;
1063 pub const mask: u32 = 0x01 << offset;
1064 pub mod R {}
1065 pub mod W {}
1066 pub mod RW {}
1067 }
1068 #[doc = "When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline"]
1069 pub mod ALPHA {
1070 pub const offset: u32 = 24;
1071 pub const mask: u32 = 0xff << offset;
1072 pub mod R {}
1073 pub mod W {}
1074 pub mod RW {}
1075 }
1076}
1077#[doc = "Output Buffer Control Register"]
1078pub mod OUT_CTRL_TOG {
1079 #[doc = "Output framebuffer format"]
1080 pub mod FORMAT {
1081 pub const offset: u32 = 0;
1082 pub const mask: u32 = 0x1f << offset;
1083 pub mod R {}
1084 pub mod W {}
1085 pub mod RW {
1086 #[doc = "32-bit pixels"]
1087 pub const ARGB8888: u32 = 0;
1088 #[doc = "32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)"]
1089 pub const RGB888: u32 = 0x04;
1090 #[doc = "24-bit pixels (packed 24-bit format)"]
1091 pub const RGB888P: u32 = 0x05;
1092 #[doc = "16-bit pixels"]
1093 pub const ARGB1555: u32 = 0x08;
1094 #[doc = "16-bit pixels"]
1095 pub const ARGB4444: u32 = 0x09;
1096 #[doc = "16-bit pixels"]
1097 pub const RGB555: u32 = 0x0c;
1098 #[doc = "16-bit pixels"]
1099 pub const RGB444: u32 = 0x0d;
1100 #[doc = "16-bit pixels"]
1101 pub const RGB565: u32 = 0x0e;
1102 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
1103 pub const YUV1P444: u32 = 0x10;
1104 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
1105 pub const UYVY1P422: u32 = 0x12;
1106 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
1107 pub const VYUY1P422: u32 = 0x13;
1108 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
1109 pub const Y8: u32 = 0x14;
1110 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
1111 pub const Y4: u32 = 0x15;
1112 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
1113 pub const YUV2P422: u32 = 0x18;
1114 #[doc = "16-bit pixels (2-plane UV)"]
1115 pub const YUV2P420: u32 = 0x19;
1116 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
1117 pub const YVU2P422: u32 = 0x1a;
1118 #[doc = "16-bit pixels (2-plane VU)"]
1119 pub const YVU2P420: u32 = 0x1b;
1120 }
1121 }
1122 #[doc = "Determines how the PXP writes it's output data"]
1123 pub mod INTERLACED_OUTPUT {
1124 pub const offset: u32 = 8;
1125 pub const mask: u32 = 0x03 << offset;
1126 pub mod R {}
1127 pub mod W {}
1128 pub mod RW {
1129 #[doc = "All data written in progressive format to the OUTBUF Pointer."]
1130 pub const PROGRESSIVE: u32 = 0;
1131 #[doc = "Interlaced output: only data for field 0 is written to the OUTBUF Pointer."]
1132 pub const FIELD0: u32 = 0x01;
1133 #[doc = "Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer."]
1134 pub const FIELD1: u32 = 0x02;
1135 #[doc = "Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2."]
1136 pub const INTERLACED: u32 = 0x03;
1137 }
1138 }
1139 #[doc = "Indicates that alpha component in output buffer pixels should be overwritten by PXP_OUT_CTRL\\[ALPHA\\]"]
1140 pub mod ALPHA_OUTPUT {
1141 pub const offset: u32 = 23;
1142 pub const mask: u32 = 0x01 << offset;
1143 pub mod R {}
1144 pub mod W {}
1145 pub mod RW {}
1146 }
1147 #[doc = "When generating an output buffer with an alpha component, the value in this field will be used when enabled to override the alpha passed through the pixel data pipeline"]
1148 pub mod ALPHA {
1149 pub const offset: u32 = 24;
1150 pub const mask: u32 = 0xff << offset;
1151 pub mod R {}
1152 pub mod W {}
1153 pub mod RW {}
1154 }
1155}
1156#[doc = "Output Frame Buffer Pointer"]
1157pub mod OUT_BUF {
1158 #[doc = "Current address pointer for the output frame buffer"]
1159 pub mod ADDR {
1160 pub const offset: u32 = 0;
1161 pub const mask: u32 = 0xffff_ffff << offset;
1162 pub mod R {}
1163 pub mod W {}
1164 pub mod RW {}
1165 }
1166}
1167#[doc = "Output Frame Buffer Pointer #2"]
1168pub mod OUT_BUF2 {
1169 #[doc = "Current address pointer for the output frame buffer"]
1170 pub mod ADDR {
1171 pub const offset: u32 = 0;
1172 pub const mask: u32 = 0xffff_ffff << offset;
1173 pub mod R {}
1174 pub mod W {}
1175 pub mod RW {}
1176 }
1177}
1178#[doc = "Output Buffer Pitch"]
1179pub mod OUT_PITCH {
1180 #[doc = "Indicates the number of bytes in memory between two vertically adjacent pixels."]
1181 pub mod PITCH {
1182 pub const offset: u32 = 0;
1183 pub const mask: u32 = 0xffff << offset;
1184 pub mod R {}
1185 pub mod W {}
1186 pub mod RW {}
1187 }
1188}
1189#[doc = "Output Surface Lower Right Coordinate"]
1190pub mod OUT_LRC {
1191 #[doc = "Indicates the number of vertical PIXELS in the output surface (non-rotated)"]
1192 pub mod Y {
1193 pub const offset: u32 = 0;
1194 pub const mask: u32 = 0x3fff << offset;
1195 pub mod R {}
1196 pub mod W {}
1197 pub mod RW {}
1198 }
1199 #[doc = "Indicates number of horizontal PIXELS in the output surface (non-rotated)"]
1200 pub mod X {
1201 pub const offset: u32 = 16;
1202 pub const mask: u32 = 0x3fff << offset;
1203 pub mod R {}
1204 pub mod W {}
1205 pub mod RW {}
1206 }
1207}
1208#[doc = "Processed Surface Upper Left Coordinate"]
1209pub mod OUT_PS_ULC {
1210 #[doc = "This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output buffer"]
1211 pub mod Y {
1212 pub const offset: u32 = 0;
1213 pub const mask: u32 = 0x3fff << offset;
1214 pub mod R {}
1215 pub mod W {}
1216 pub mod RW {}
1217 }
1218 #[doc = "This field indicates the upper left X-coordinate (in pixels) of the processed surface (PS) in the output buffer"]
1219 pub mod X {
1220 pub const offset: u32 = 16;
1221 pub const mask: u32 = 0x3fff << offset;
1222 pub mod R {}
1223 pub mod W {}
1224 pub mod RW {}
1225 }
1226}
1227#[doc = "Processed Surface Lower Right Coordinate"]
1228pub mod OUT_PS_LRC {
1229 #[doc = "This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer"]
1230 pub mod Y {
1231 pub const offset: u32 = 0;
1232 pub const mask: u32 = 0x3fff << offset;
1233 pub mod R {}
1234 pub mod W {}
1235 pub mod RW {}
1236 }
1237 #[doc = "This field indicates the lower right X-coordinate (in pixels) of the processed surface (PS) in the output frame buffer"]
1238 pub mod X {
1239 pub const offset: u32 = 16;
1240 pub const mask: u32 = 0x3fff << offset;
1241 pub mod R {}
1242 pub mod W {}
1243 pub mod RW {}
1244 }
1245}
1246#[doc = "Alpha Surface Upper Left Coordinate"]
1247pub mod OUT_AS_ULC {
1248 #[doc = "This field indicates the upper left Y-coordinate (in pixels) of the alpha surface in the output frame buffer"]
1249 pub mod Y {
1250 pub const offset: u32 = 0;
1251 pub const mask: u32 = 0x3fff << offset;
1252 pub mod R {}
1253 pub mod W {}
1254 pub mod RW {}
1255 }
1256 #[doc = "This field indicates the upper left X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer"]
1257 pub mod X {
1258 pub const offset: u32 = 16;
1259 pub const mask: u32 = 0x3fff << offset;
1260 pub mod R {}
1261 pub mod W {}
1262 pub mod RW {}
1263 }
1264}
1265#[doc = "Alpha Surface Lower Right Coordinate"]
1266pub mod OUT_AS_LRC {
1267 #[doc = "This field indicates the lower right Y-coordinate (in pixels) of the alpha surface in the output frame buffer"]
1268 pub mod Y {
1269 pub const offset: u32 = 0;
1270 pub const mask: u32 = 0x3fff << offset;
1271 pub mod R {}
1272 pub mod W {}
1273 pub mod RW {}
1274 }
1275 #[doc = "This field indicates the lower right X-coordinate (in pixels) of the alpha surface (AS) in the output frame buffer"]
1276 pub mod X {
1277 pub const offset: u32 = 16;
1278 pub const mask: u32 = 0x3fff << offset;
1279 pub mod R {}
1280 pub mod W {}
1281 pub mod RW {}
1282 }
1283}
1284#[doc = "Processed Surface (PS) Control Register"]
1285pub mod PS_CTRL {
1286 #[doc = "PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register."]
1287 pub mod FORMAT {
1288 pub const offset: u32 = 0;
1289 pub const mask: u32 = 0x1f << offset;
1290 pub mod R {}
1291 pub mod W {}
1292 pub mod RW {
1293 #[doc = "32-bit pixels (unpacked 24-bit format)"]
1294 pub const RGB888: u32 = 0x04;
1295 #[doc = "16-bit pixels"]
1296 pub const RGB555: u32 = 0x0c;
1297 #[doc = "16-bit pixels"]
1298 pub const RGB444: u32 = 0x0d;
1299 #[doc = "16-bit pixels"]
1300 pub const RGB565: u32 = 0x0e;
1301 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
1302 pub const YUV1P444: u32 = 0x10;
1303 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
1304 pub const UYVY1P422: u32 = 0x12;
1305 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
1306 pub const VYUY1P422: u32 = 0x13;
1307 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
1308 pub const Y8: u32 = 0x14;
1309 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
1310 pub const Y4: u32 = 0x15;
1311 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
1312 pub const YUV2P422: u32 = 0x18;
1313 #[doc = "16-bit pixels (2-plane UV)"]
1314 pub const YUV2P420: u32 = 0x19;
1315 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
1316 pub const YVU2P422: u32 = 0x1a;
1317 #[doc = "16-bit pixels (2-plane VU)"]
1318 pub const YVU2P420: u32 = 0x1b;
1319 #[doc = "16-bit pixels (3-plane format)"]
1320 pub const YUV422: u32 = 0x1e;
1321 #[doc = "16-bit pixels (3-plane format)"]
1322 pub const YUV420: u32 = 0x1f;
1323 }
1324 }
1325 #[doc = "Swap bytes in words. For each 16 bit word, the two bytes will be swapped."]
1326 pub mod WB_SWAP {
1327 pub const offset: u32 = 5;
1328 pub const mask: u32 = 0x01 << offset;
1329 pub mod R {}
1330 pub mod W {}
1331 pub mod RW {}
1332 }
1333 #[doc = "Verticle pre decimation filter control."]
1334 pub mod DECY {
1335 pub const offset: u32 = 8;
1336 pub const mask: u32 = 0x03 << offset;
1337 pub mod R {}
1338 pub mod W {}
1339 pub mod RW {
1340 #[doc = "Disable pre-decimation filter."]
1341 pub const DISABLE: u32 = 0;
1342 #[doc = "Decimate PS by 2."]
1343 pub const DECY2: u32 = 0x01;
1344 #[doc = "Decimate PS by 4."]
1345 pub const DECY4: u32 = 0x02;
1346 #[doc = "Decimate PS by 8."]
1347 pub const DECY8: u32 = 0x03;
1348 }
1349 }
1350 #[doc = "Horizontal pre decimation filter control."]
1351 pub mod DECX {
1352 pub const offset: u32 = 10;
1353 pub const mask: u32 = 0x03 << offset;
1354 pub mod R {}
1355 pub mod W {}
1356 pub mod RW {
1357 #[doc = "Disable pre-decimation filter."]
1358 pub const DISABLE: u32 = 0;
1359 #[doc = "Decimate PS by 2."]
1360 pub const DECX2: u32 = 0x01;
1361 #[doc = "Decimate PS by 4."]
1362 pub const DECX4: u32 = 0x02;
1363 #[doc = "Decimate PS by 8."]
1364 pub const DECX8: u32 = 0x03;
1365 }
1366 }
1367}
1368#[doc = "Processed Surface (PS) Control Register"]
1369pub mod PS_CTRL_SET {
1370 #[doc = "PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register."]
1371 pub mod FORMAT {
1372 pub const offset: u32 = 0;
1373 pub const mask: u32 = 0x1f << offset;
1374 pub mod R {}
1375 pub mod W {}
1376 pub mod RW {
1377 #[doc = "32-bit pixels (unpacked 24-bit format)"]
1378 pub const RGB888: u32 = 0x04;
1379 #[doc = "16-bit pixels"]
1380 pub const RGB555: u32 = 0x0c;
1381 #[doc = "16-bit pixels"]
1382 pub const RGB444: u32 = 0x0d;
1383 #[doc = "16-bit pixels"]
1384 pub const RGB565: u32 = 0x0e;
1385 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
1386 pub const YUV1P444: u32 = 0x10;
1387 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
1388 pub const UYVY1P422: u32 = 0x12;
1389 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
1390 pub const VYUY1P422: u32 = 0x13;
1391 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
1392 pub const Y8: u32 = 0x14;
1393 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
1394 pub const Y4: u32 = 0x15;
1395 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
1396 pub const YUV2P422: u32 = 0x18;
1397 #[doc = "16-bit pixels (2-plane UV)"]
1398 pub const YUV2P420: u32 = 0x19;
1399 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
1400 pub const YVU2P422: u32 = 0x1a;
1401 #[doc = "16-bit pixels (2-plane VU)"]
1402 pub const YVU2P420: u32 = 0x1b;
1403 #[doc = "16-bit pixels (3-plane format)"]
1404 pub const YUV422: u32 = 0x1e;
1405 #[doc = "16-bit pixels (3-plane format)"]
1406 pub const YUV420: u32 = 0x1f;
1407 }
1408 }
1409 #[doc = "Swap bytes in words. For each 16 bit word, the two bytes will be swapped."]
1410 pub mod WB_SWAP {
1411 pub const offset: u32 = 5;
1412 pub const mask: u32 = 0x01 << offset;
1413 pub mod R {}
1414 pub mod W {}
1415 pub mod RW {}
1416 }
1417 #[doc = "Verticle pre decimation filter control."]
1418 pub mod DECY {
1419 pub const offset: u32 = 8;
1420 pub const mask: u32 = 0x03 << offset;
1421 pub mod R {}
1422 pub mod W {}
1423 pub mod RW {
1424 #[doc = "Disable pre-decimation filter."]
1425 pub const DISABLE: u32 = 0;
1426 #[doc = "Decimate PS by 2."]
1427 pub const DECY2: u32 = 0x01;
1428 #[doc = "Decimate PS by 4."]
1429 pub const DECY4: u32 = 0x02;
1430 #[doc = "Decimate PS by 8."]
1431 pub const DECY8: u32 = 0x03;
1432 }
1433 }
1434 #[doc = "Horizontal pre decimation filter control."]
1435 pub mod DECX {
1436 pub const offset: u32 = 10;
1437 pub const mask: u32 = 0x03 << offset;
1438 pub mod R {}
1439 pub mod W {}
1440 pub mod RW {
1441 #[doc = "Disable pre-decimation filter."]
1442 pub const DISABLE: u32 = 0;
1443 #[doc = "Decimate PS by 2."]
1444 pub const DECX2: u32 = 0x01;
1445 #[doc = "Decimate PS by 4."]
1446 pub const DECX4: u32 = 0x02;
1447 #[doc = "Decimate PS by 8."]
1448 pub const DECX8: u32 = 0x03;
1449 }
1450 }
1451}
1452#[doc = "Processed Surface (PS) Control Register"]
1453pub mod PS_CTRL_CLR {
1454 #[doc = "PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register."]
1455 pub mod FORMAT {
1456 pub const offset: u32 = 0;
1457 pub const mask: u32 = 0x1f << offset;
1458 pub mod R {}
1459 pub mod W {}
1460 pub mod RW {
1461 #[doc = "32-bit pixels (unpacked 24-bit format)"]
1462 pub const RGB888: u32 = 0x04;
1463 #[doc = "16-bit pixels"]
1464 pub const RGB555: u32 = 0x0c;
1465 #[doc = "16-bit pixels"]
1466 pub const RGB444: u32 = 0x0d;
1467 #[doc = "16-bit pixels"]
1468 pub const RGB565: u32 = 0x0e;
1469 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
1470 pub const YUV1P444: u32 = 0x10;
1471 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
1472 pub const UYVY1P422: u32 = 0x12;
1473 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
1474 pub const VYUY1P422: u32 = 0x13;
1475 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
1476 pub const Y8: u32 = 0x14;
1477 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
1478 pub const Y4: u32 = 0x15;
1479 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
1480 pub const YUV2P422: u32 = 0x18;
1481 #[doc = "16-bit pixels (2-plane UV)"]
1482 pub const YUV2P420: u32 = 0x19;
1483 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
1484 pub const YVU2P422: u32 = 0x1a;
1485 #[doc = "16-bit pixels (2-plane VU)"]
1486 pub const YVU2P420: u32 = 0x1b;
1487 #[doc = "16-bit pixels (3-plane format)"]
1488 pub const YUV422: u32 = 0x1e;
1489 #[doc = "16-bit pixels (3-plane format)"]
1490 pub const YUV420: u32 = 0x1f;
1491 }
1492 }
1493 #[doc = "Swap bytes in words. For each 16 bit word, the two bytes will be swapped."]
1494 pub mod WB_SWAP {
1495 pub const offset: u32 = 5;
1496 pub const mask: u32 = 0x01 << offset;
1497 pub mod R {}
1498 pub mod W {}
1499 pub mod RW {}
1500 }
1501 #[doc = "Verticle pre decimation filter control."]
1502 pub mod DECY {
1503 pub const offset: u32 = 8;
1504 pub const mask: u32 = 0x03 << offset;
1505 pub mod R {}
1506 pub mod W {}
1507 pub mod RW {
1508 #[doc = "Disable pre-decimation filter."]
1509 pub const DISABLE: u32 = 0;
1510 #[doc = "Decimate PS by 2."]
1511 pub const DECY2: u32 = 0x01;
1512 #[doc = "Decimate PS by 4."]
1513 pub const DECY4: u32 = 0x02;
1514 #[doc = "Decimate PS by 8."]
1515 pub const DECY8: u32 = 0x03;
1516 }
1517 }
1518 #[doc = "Horizontal pre decimation filter control."]
1519 pub mod DECX {
1520 pub const offset: u32 = 10;
1521 pub const mask: u32 = 0x03 << offset;
1522 pub mod R {}
1523 pub mod W {}
1524 pub mod RW {
1525 #[doc = "Disable pre-decimation filter."]
1526 pub const DISABLE: u32 = 0;
1527 #[doc = "Decimate PS by 2."]
1528 pub const DECX2: u32 = 0x01;
1529 #[doc = "Decimate PS by 4."]
1530 pub const DECX4: u32 = 0x02;
1531 #[doc = "Decimate PS by 8."]
1532 pub const DECX8: u32 = 0x03;
1533 }
1534 }
1535}
1536#[doc = "Processed Surface (PS) Control Register"]
1537pub mod PS_CTRL_TOG {
1538 #[doc = "PS buffer format. To select between YUV and YCbCr formats, see bit 31 of the CSC1_COEF0 register."]
1539 pub mod FORMAT {
1540 pub const offset: u32 = 0;
1541 pub const mask: u32 = 0x1f << offset;
1542 pub mod R {}
1543 pub mod W {}
1544 pub mod RW {
1545 #[doc = "32-bit pixels (unpacked 24-bit format)"]
1546 pub const RGB888: u32 = 0x04;
1547 #[doc = "16-bit pixels"]
1548 pub const RGB555: u32 = 0x0c;
1549 #[doc = "16-bit pixels"]
1550 pub const RGB444: u32 = 0x0d;
1551 #[doc = "16-bit pixels"]
1552 pub const RGB565: u32 = 0x0e;
1553 #[doc = "32-bit pixels (1-plane XYUV unpacked)"]
1554 pub const YUV1P444: u32 = 0x10;
1555 #[doc = "16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)"]
1556 pub const UYVY1P422: u32 = 0x12;
1557 #[doc = "16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)"]
1558 pub const VYUY1P422: u32 = 0x13;
1559 #[doc = "8-bit monochrome pixels (1-plane Y luma output)"]
1560 pub const Y8: u32 = 0x14;
1561 #[doc = "4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)"]
1562 pub const Y4: u32 = 0x15;
1563 #[doc = "16-bit pixels (2-plane UV interleaved bytes)"]
1564 pub const YUV2P422: u32 = 0x18;
1565 #[doc = "16-bit pixels (2-plane UV)"]
1566 pub const YUV2P420: u32 = 0x19;
1567 #[doc = "16-bit pixels (2-plane VU interleaved bytes)"]
1568 pub const YVU2P422: u32 = 0x1a;
1569 #[doc = "16-bit pixels (2-plane VU)"]
1570 pub const YVU2P420: u32 = 0x1b;
1571 #[doc = "16-bit pixels (3-plane format)"]
1572 pub const YUV422: u32 = 0x1e;
1573 #[doc = "16-bit pixels (3-plane format)"]
1574 pub const YUV420: u32 = 0x1f;
1575 }
1576 }
1577 #[doc = "Swap bytes in words. For each 16 bit word, the two bytes will be swapped."]
1578 pub mod WB_SWAP {
1579 pub const offset: u32 = 5;
1580 pub const mask: u32 = 0x01 << offset;
1581 pub mod R {}
1582 pub mod W {}
1583 pub mod RW {}
1584 }
1585 #[doc = "Verticle pre decimation filter control."]
1586 pub mod DECY {
1587 pub const offset: u32 = 8;
1588 pub const mask: u32 = 0x03 << offset;
1589 pub mod R {}
1590 pub mod W {}
1591 pub mod RW {
1592 #[doc = "Disable pre-decimation filter."]
1593 pub const DISABLE: u32 = 0;
1594 #[doc = "Decimate PS by 2."]
1595 pub const DECY2: u32 = 0x01;
1596 #[doc = "Decimate PS by 4."]
1597 pub const DECY4: u32 = 0x02;
1598 #[doc = "Decimate PS by 8."]
1599 pub const DECY8: u32 = 0x03;
1600 }
1601 }
1602 #[doc = "Horizontal pre decimation filter control."]
1603 pub mod DECX {
1604 pub const offset: u32 = 10;
1605 pub const mask: u32 = 0x03 << offset;
1606 pub mod R {}
1607 pub mod W {}
1608 pub mod RW {
1609 #[doc = "Disable pre-decimation filter."]
1610 pub const DISABLE: u32 = 0;
1611 #[doc = "Decimate PS by 2."]
1612 pub const DECX2: u32 = 0x01;
1613 #[doc = "Decimate PS by 4."]
1614 pub const DECX4: u32 = 0x02;
1615 #[doc = "Decimate PS by 8."]
1616 pub const DECX8: u32 = 0x03;
1617 }
1618 }
1619}
1620#[doc = "PS Input Buffer Address"]
1621pub mod PS_BUF {
1622 #[doc = "Address pointer for the PS RGB or Y (luma) input buffer."]
1623 pub mod ADDR {
1624 pub const offset: u32 = 0;
1625 pub const mask: u32 = 0xffff_ffff << offset;
1626 pub mod R {}
1627 pub mod W {}
1628 pub mod RW {}
1629 }
1630}
1631#[doc = "PS U/Cb or 2 Plane UV Input Buffer Address"]
1632pub mod PS_UBUF {
1633 #[doc = "Address pointer for the PS U/Cb or 2 plane UV Chroma input buffer."]
1634 pub mod ADDR {
1635 pub const offset: u32 = 0;
1636 pub const mask: u32 = 0xffff_ffff << offset;
1637 pub mod R {}
1638 pub mod W {}
1639 pub mod RW {}
1640 }
1641}
1642#[doc = "PS V/Cr Input Buffer Address"]
1643pub mod PS_VBUF {
1644 #[doc = "Address pointer for the PS V/Cr Chroma input buffer."]
1645 pub mod ADDR {
1646 pub const offset: u32 = 0;
1647 pub const mask: u32 = 0xffff_ffff << offset;
1648 pub mod R {}
1649 pub mod W {}
1650 pub mod RW {}
1651 }
1652}
1653#[doc = "Processed Surface Pitch"]
1654pub mod PS_PITCH {
1655 #[doc = "Indicates the number of bytes in memory between two vertically adjacent pixels."]
1656 pub mod PITCH {
1657 pub const offset: u32 = 0;
1658 pub const mask: u32 = 0xffff << offset;
1659 pub mod R {}
1660 pub mod W {}
1661 pub mod RW {}
1662 }
1663}
1664#[doc = "PS Background Color"]
1665pub mod PS_BACKGROUND {
1666 #[doc = "Background color (in 24bpp format) for any pixels not within the buffer range specified by the PS ULC/LRC"]
1667 pub mod COLOR {
1668 pub const offset: u32 = 0;
1669 pub const mask: u32 = 0x00ff_ffff << offset;
1670 pub mod R {}
1671 pub mod W {}
1672 pub mod RW {}
1673 }
1674}
1675#[doc = "PS Scale Factor Register"]
1676pub mod PS_SCALE {
1677 #[doc = "This is a two bit integer and 12 bit fractional representation (##"]
1678 pub mod XSCALE {
1679 pub const offset: u32 = 0;
1680 pub const mask: u32 = 0x7fff << offset;
1681 pub mod R {}
1682 pub mod W {}
1683 pub mod RW {}
1684 }
1685 #[doc = "This is a two bit integer and 12 bit fractional representation (##"]
1686 pub mod YSCALE {
1687 pub const offset: u32 = 16;
1688 pub const mask: u32 = 0x7fff << offset;
1689 pub mod R {}
1690 pub mod W {}
1691 pub mod RW {}
1692 }
1693}
1694#[doc = "PS Scale Offset Register"]
1695pub mod PS_OFFSET {
1696 #[doc = "This is a 12 bit fractional representation (0"]
1697 pub mod XOFFSET {
1698 pub const offset: u32 = 0;
1699 pub const mask: u32 = 0x0fff << offset;
1700 pub mod R {}
1701 pub mod W {}
1702 pub mod RW {}
1703 }
1704 #[doc = "This is a 12 bit fractional representation (0"]
1705 pub mod YOFFSET {
1706 pub const offset: u32 = 16;
1707 pub const mask: u32 = 0x0fff << offset;
1708 pub mod R {}
1709 pub mod W {}
1710 pub mod RW {}
1711 }
1712}
1713#[doc = "PS Color Key Low"]
1714pub mod PS_CLRKEYLOW {
1715 #[doc = "Low range of color key applied to PS buffer"]
1716 pub mod PIXEL {
1717 pub const offset: u32 = 0;
1718 pub const mask: u32 = 0x00ff_ffff << offset;
1719 pub mod R {}
1720 pub mod W {}
1721 pub mod RW {}
1722 }
1723}
1724#[doc = "PS Color Key High"]
1725pub mod PS_CLRKEYHIGH {
1726 #[doc = "High range of color key applied to PS buffer"]
1727 pub mod PIXEL {
1728 pub const offset: u32 = 0;
1729 pub const mask: u32 = 0x00ff_ffff << offset;
1730 pub mod R {}
1731 pub mod W {}
1732 pub mod RW {}
1733 }
1734}
1735#[doc = "Alpha Surface Control"]
1736pub mod AS_CTRL {
1737 #[doc = "Determines how the alpha value is constructed for this alpha surface"]
1738 pub mod ALPHA_CTRL {
1739 pub const offset: u32 = 1;
1740 pub const mask: u32 = 0x03 << offset;
1741 pub mod R {}
1742 pub mod W {}
1743 pub mod RW {
1744 #[doc = "Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored."]
1745 pub const EMBEDDED: u32 = 0;
1746 #[doc = "Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels."]
1747 pub const OVERRIDE: u32 = 0x01;
1748 #[doc = "Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field."]
1749 pub const MULTIPLY: u32 = 0x02;
1750 #[doc = "Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels."]
1751 pub const ROPS: u32 = 0x03;
1752 }
1753 }
1754 #[doc = "Indicates that colorkey functionality is enabled for this alpha surface"]
1755 pub mod ENABLE_COLORKEY {
1756 pub const offset: u32 = 3;
1757 pub const mask: u32 = 0x01 << offset;
1758 pub mod R {}
1759 pub mod W {}
1760 pub mod RW {}
1761 }
1762 #[doc = "Indicates the input buffer format for AS."]
1763 pub mod FORMAT {
1764 pub const offset: u32 = 4;
1765 pub const mask: u32 = 0x0f << offset;
1766 pub mod R {}
1767 pub mod W {}
1768 pub mod RW {
1769 #[doc = "32-bit pixels with alpha"]
1770 pub const ARGB8888: u32 = 0;
1771 #[doc = "32-bit pixels without alpha (unpacked 24-bit format)"]
1772 pub const RGB888: u32 = 0x04;
1773 #[doc = "16-bit pixels with alpha"]
1774 pub const ARGB1555: u32 = 0x08;
1775 #[doc = "16-bit pixels with alpha"]
1776 pub const ARGB4444: u32 = 0x09;
1777 #[doc = "16-bit pixels without alpha"]
1778 pub const RGB555: u32 = 0x0c;
1779 #[doc = "16-bit pixels without alpha"]
1780 pub const RGB444: u32 = 0x0d;
1781 #[doc = "16-bit pixels without alpha"]
1782 pub const RGB565: u32 = 0x0e;
1783 }
1784 }
1785 #[doc = "Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE values are programmed in PXP_AS_CTRL\\[ALPHA_CTRL\\]"]
1786 pub mod ALPHA {
1787 pub const offset: u32 = 8;
1788 pub const mask: u32 = 0xff << offset;
1789 pub mod R {}
1790 pub mod W {}
1791 pub mod RW {}
1792 }
1793 #[doc = "Indicates a raster operation to perform when enabled"]
1794 pub mod ROP {
1795 pub const offset: u32 = 16;
1796 pub const mask: u32 = 0x0f << offset;
1797 pub mod R {}
1798 pub mod W {}
1799 pub mod RW {
1800 #[doc = "AS AND PS"]
1801 pub const MASKAS: u32 = 0;
1802 #[doc = "nAS AND PS"]
1803 pub const MASKNOTAS: u32 = 0x01;
1804 #[doc = "AS AND nPS"]
1805 pub const MASKASNOT: u32 = 0x02;
1806 #[doc = "AS OR PS"]
1807 pub const MERGEAS: u32 = 0x03;
1808 #[doc = "nAS OR PS"]
1809 pub const MERGENOTAS: u32 = 0x04;
1810 #[doc = "AS OR nPS"]
1811 pub const MERGEASNOT: u32 = 0x05;
1812 #[doc = "nAS"]
1813 pub const NOTCOPYAS: u32 = 0x06;
1814 #[doc = "nPS"]
1815 pub const NOT: u32 = 0x07;
1816 #[doc = "AS NAND PS"]
1817 pub const NOTMASKAS: u32 = 0x08;
1818 #[doc = "AS NOR PS"]
1819 pub const NOTMERGEAS: u32 = 0x09;
1820 #[doc = "AS XOR PS"]
1821 pub const XORAS: u32 = 0x0a;
1822 #[doc = "AS XNOR PS"]
1823 pub const NOTXORAS: u32 = 0x0b;
1824 }
1825 }
1826 #[doc = "Setting this bit to logic 0 will not alter the alpha value"]
1827 pub mod ALPHA_INVERT {
1828 pub const offset: u32 = 20;
1829 pub const mask: u32 = 0x01 << offset;
1830 pub mod R {}
1831 pub mod W {}
1832 pub mod RW {}
1833 }
1834}
1835#[doc = "Alpha Surface Buffer Pointer"]
1836pub mod AS_BUF {
1837 #[doc = "Address pointer for the alpha surface 0 buffer."]
1838 pub mod ADDR {
1839 pub const offset: u32 = 0;
1840 pub const mask: u32 = 0xffff_ffff << offset;
1841 pub mod R {}
1842 pub mod W {}
1843 pub mod RW {}
1844 }
1845}
1846#[doc = "Alpha Surface Pitch"]
1847pub mod AS_PITCH {
1848 #[doc = "Indicates the number of bytes in memory between two vertically adjacent pixels."]
1849 pub mod PITCH {
1850 pub const offset: u32 = 0;
1851 pub const mask: u32 = 0xffff << offset;
1852 pub mod R {}
1853 pub mod W {}
1854 pub mod RW {}
1855 }
1856}
1857#[doc = "Overlay Color Key Low"]
1858pub mod AS_CLRKEYLOW {
1859 #[doc = "Low range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable."]
1860 pub mod PIXEL {
1861 pub const offset: u32 = 0;
1862 pub const mask: u32 = 0x00ff_ffff << offset;
1863 pub mod R {}
1864 pub mod W {}
1865 pub mod RW {}
1866 }
1867}
1868#[doc = "Overlay Color Key High"]
1869pub mod AS_CLRKEYHIGH {
1870 #[doc = "High range of RGB color key applied to AS buffer. Each overlay has an independent colorkey enable."]
1871 pub mod PIXEL {
1872 pub const offset: u32 = 0;
1873 pub const mask: u32 = 0x00ff_ffff << offset;
1874 pub mod R {}
1875 pub mod W {}
1876 pub mod RW {}
1877 }
1878}
1879#[doc = "Color Space Conversion Coefficient Register 0"]
1880pub mod CSC1_COEF0 {
1881 #[doc = "Two's compliment amplitude offset implicit in the Y data"]
1882 pub mod Y_OFFSET {
1883 pub const offset: u32 = 0;
1884 pub const mask: u32 = 0x01ff << offset;
1885 pub mod R {}
1886 pub mod W {}
1887 pub mod RW {}
1888 }
1889 #[doc = "Two's compliment phase offset implicit for CbCr data"]
1890 pub mod UV_OFFSET {
1891 pub const offset: u32 = 9;
1892 pub const mask: u32 = 0x01ff << offset;
1893 pub mod R {}
1894 pub mod W {}
1895 pub mod RW {}
1896 }
1897 #[doc = "Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)"]
1898 pub mod C0 {
1899 pub const offset: u32 = 18;
1900 pub const mask: u32 = 0x07ff << offset;
1901 pub mod R {}
1902 pub mod W {}
1903 pub mod RW {}
1904 }
1905 #[doc = "Bypass the CSC unit in the scaling engine"]
1906 pub mod BYPASS {
1907 pub const offset: u32 = 30;
1908 pub const mask: u32 = 0x01 << offset;
1909 pub mod R {}
1910 pub mod W {}
1911 pub mod RW {}
1912 }
1913 #[doc = "Set to 1 when performing YCbCr conversion to RGB"]
1914 pub mod YCBCR_MODE {
1915 pub const offset: u32 = 31;
1916 pub const mask: u32 = 0x01 << offset;
1917 pub mod R {}
1918 pub mod W {}
1919 pub mod RW {}
1920 }
1921}
1922#[doc = "Color Space Conversion Coefficient Register 1"]
1923pub mod CSC1_COEF1 {
1924 #[doc = "Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)"]
1925 pub mod C4 {
1926 pub const offset: u32 = 0;
1927 pub const mask: u32 = 0x07ff << offset;
1928 pub mod R {}
1929 pub mod W {}
1930 pub mod RW {}
1931 }
1932 #[doc = "Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)"]
1933 pub mod C1 {
1934 pub const offset: u32 = 16;
1935 pub const mask: u32 = 0x07ff << offset;
1936 pub mod R {}
1937 pub mod W {}
1938 pub mod RW {}
1939 }
1940}
1941#[doc = "Color Space Conversion Coefficient Register 2"]
1942pub mod CSC1_COEF2 {
1943 #[doc = "Two's complement Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)"]
1944 pub mod C3 {
1945 pub const offset: u32 = 0;
1946 pub const mask: u32 = 0x07ff << offset;
1947 pub mod R {}
1948 pub mod W {}
1949 pub mod RW {}
1950 }
1951 #[doc = "Two's complement Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)"]
1952 pub mod C2 {
1953 pub const offset: u32 = 16;
1954 pub const mask: u32 = 0x07ff << offset;
1955 pub mod R {}
1956 pub mod W {}
1957 pub mod RW {}
1958 }
1959}
1960#[doc = "PXP Power Control Register"]
1961pub mod POWER {
1962 #[doc = "Select the low power state of the ROT memory."]
1963 pub mod ROT_MEM_LP_STATE {
1964 pub const offset: u32 = 9;
1965 pub const mask: u32 = 0x07 << offset;
1966 pub mod R {}
1967 pub mod W {}
1968 pub mod RW {
1969 #[doc = "Memory is not in low power state."]
1970 pub const NONE: u32 = 0;
1971 #[doc = "Light Sleep Mode. Low leakage mode, maintain memory contents."]
1972 pub const LS: u32 = 0x01;
1973 #[doc = "Deep Sleep Mode. Low leakage mode, maintain memory contents."]
1974 pub const DS: u32 = 0x02;
1975 #[doc = "Shut Down Mode. Shut Down periphery and core, no memory retention."]
1976 pub const SD: u32 = 0x04;
1977 }
1978 }
1979 #[doc = "Power control for the PXP."]
1980 pub mod CTRL {
1981 pub const offset: u32 = 12;
1982 pub const mask: u32 = 0x000f_ffff << offset;
1983 pub mod R {}
1984 pub mod W {}
1985 pub mod RW {}
1986 }
1987}
1988#[doc = "Next Frame Pointer"]
1989pub mod NEXT {
1990 #[doc = "Indicates that the \"next frame\" functionality has been enabled"]
1991 pub mod ENABLED {
1992 pub const offset: u32 = 0;
1993 pub const mask: u32 = 0x01 << offset;
1994 pub mod R {}
1995 pub mod W {}
1996 pub mod RW {}
1997 }
1998 #[doc = "A pointer to a data structure containing register values to be used when processing the next frame"]
1999 pub mod POINTER {
2000 pub const offset: u32 = 2;
2001 pub const mask: u32 = 0x3fff_ffff << offset;
2002 pub mod R {}
2003 pub mod W {}
2004 pub mod RW {}
2005 }
2006}
2007#[doc = "PXP Alpha Engine A Control Register."]
2008pub mod PORTER_DUFF_CTRL {
2009 #[doc = "poter_duff enable"]
2010 pub mod POTER_DUFF_ENABLE {
2011 pub const offset: u32 = 0;
2012 pub const mask: u32 = 0x01 << offset;
2013 pub mod R {}
2014 pub mod W {}
2015 pub mod RW {}
2016 }
2017 #[doc = "s0 to s1 factor mode"]
2018 pub mod S0_S1_FACTOR_MODE {
2019 pub const offset: u32 = 1;
2020 pub const mask: u32 = 0x03 << offset;
2021 pub mod R {}
2022 pub mod W {}
2023 pub mod RW {}
2024 }
2025 #[doc = "s0 global alpha mode"]
2026 pub mod S0_GLOBAL_ALPHA_MODE {
2027 pub const offset: u32 = 3;
2028 pub const mask: u32 = 0x03 << offset;
2029 pub mod R {}
2030 pub mod W {}
2031 pub mod RW {}
2032 }
2033 #[doc = "s0 alpha mode"]
2034 pub mod S0_ALPHA_MODE {
2035 pub const offset: u32 = 5;
2036 pub const mask: u32 = 0x01 << offset;
2037 pub mod R {}
2038 pub mod W {}
2039 pub mod RW {}
2040 }
2041 #[doc = "s0 color mode"]
2042 pub mod S0_COLOR_MODE {
2043 pub const offset: u32 = 6;
2044 pub const mask: u32 = 0x01 << offset;
2045 pub mod R {}
2046 pub mod W {}
2047 pub mod RW {}
2048 }
2049 #[doc = "s1 to s0 factor mode"]
2050 pub mod S1_S0_FACTOR_MODE {
2051 pub const offset: u32 = 8;
2052 pub const mask: u32 = 0x03 << offset;
2053 pub mod R {}
2054 pub mod W {}
2055 pub mod RW {}
2056 }
2057 #[doc = "s1 global alpha mode"]
2058 pub mod S1_GLOBAL_ALPHA_MODE {
2059 pub const offset: u32 = 10;
2060 pub const mask: u32 = 0x03 << offset;
2061 pub mod R {}
2062 pub mod W {}
2063 pub mod RW {}
2064 }
2065 #[doc = "s1 alpha mode"]
2066 pub mod S1_ALPHA_MODE {
2067 pub const offset: u32 = 12;
2068 pub const mask: u32 = 0x01 << offset;
2069 pub mod R {}
2070 pub mod W {}
2071 pub mod RW {}
2072 }
2073 #[doc = "s1 color mode"]
2074 pub mod S1_COLOR_MODE {
2075 pub const offset: u32 = 13;
2076 pub const mask: u32 = 0x01 << offset;
2077 pub mod R {}
2078 pub mod W {}
2079 pub mod RW {}
2080 }
2081 #[doc = "s0 global alpha"]
2082 pub mod S0_GLOBAL_ALPHA {
2083 pub const offset: u32 = 16;
2084 pub const mask: u32 = 0xff << offset;
2085 pub mod R {}
2086 pub mod W {}
2087 pub mod RW {}
2088 }
2089 #[doc = "s1 global alpha"]
2090 pub mod S1_GLOBAL_ALPHA {
2091 pub const offset: u32 = 24;
2092 pub const mask: u32 = 0xff << offset;
2093 pub mod R {}
2094 pub mod W {}
2095 pub mod RW {}
2096 }
2097}