Struct imxrt_ral::pwm::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub SM: [RegisterBlock; 4],
    pub OUTEN: RWRegister<u16>,
    pub MASK: RWRegister<u16>,
    pub SWCOUT: RWRegister<u16>,
    pub DTSRCSEL: RWRegister<u16>,
    pub MCTRL: RWRegister<u16>,
    pub MCTRL2: RWRegister<u16>,
    pub FCTRL0: RWRegister<u16>,
    pub FSTS0: RWRegister<u16>,
    pub FFILT0: RWRegister<u16>,
    pub FTST0: RWRegister<u16>,
    pub FCTRL20: RWRegister<u16>,
}

PWM

Fields

SM: [RegisterBlock; 4]

Cluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, SM?CTRL, SM?VAL0, SM?FRACVAL1, SM?VAL1, SM?FRACVAL2, SM?VAL2, SM?FRACVAL3, SM?VAL3, SM?FRACVAL4, SM?VAL4, SM?FRACVAL5, SM?VAL5, SM?FRCTRL, SM?OCTRL, SM?STS, SM?INTEN, SM?DMAEN, SM?TCTRL, SM?DISMAP0, SM?DISMAP1, SM?DTCNT0, SM?DTCNT1, SM?CAPTCTRLA, SM?CAPTCOMPA, SM?CAPTCTRLB, SM?CAPTCOMPB, SM?CAPTCTRLX, SM?CAPTCOMPX, SM?CVAL0, SM?CVAL0CYC, SM?CVAL1, SM?CVAL1CYC, SM?CVAL2, SM?CVAL2CYC, SM?CVAL3, SM?CVAL3CYC, SM?CVAL4, SM?CVAL4CYC, SM?CVAL5, SM?CVAL5CYC

OUTEN: RWRegister<u16>

Output Enable Register

MASK: RWRegister<u16>

Mask Register

SWCOUT: RWRegister<u16>

Software Controlled Output Register

DTSRCSEL: RWRegister<u16>

PWM Source Select Register

MCTRL: RWRegister<u16>

Master Control Register

MCTRL2: RWRegister<u16>

Master Control 2 Register

FCTRL0: RWRegister<u16>

Fault Control Register

FSTS0: RWRegister<u16>

Fault Status Register

FFILT0: RWRegister<u16>

Fault Filter Register

FTST0: RWRegister<u16>

Fault Test Register

FCTRL20: RWRegister<u16>

Fault Control 2 Register