Struct imxrt_ral::ccm_analog::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub PLL_ARM: RWRegister<u32>,
    pub PLL_ARM_SET: RWRegister<u32>,
    pub PLL_ARM_CLR: RWRegister<u32>,
    pub PLL_ARM_TOG: RWRegister<u32>,
    pub PLL_USB1: RWRegister<u32>,
    pub PLL_USB1_SET: RWRegister<u32>,
    pub PLL_USB1_CLR: RWRegister<u32>,
    pub PLL_USB1_TOG: RWRegister<u32>,
    pub PLL_USB2: RWRegister<u32>,
    pub PLL_USB2_SET: RWRegister<u32>,
    pub PLL_USB2_CLR: RWRegister<u32>,
    pub PLL_USB2_TOG: RWRegister<u32>,
    pub PLL_SYS: RWRegister<u32>,
    pub PLL_SYS_SET: RWRegister<u32>,
    pub PLL_SYS_CLR: RWRegister<u32>,
    pub PLL_SYS_TOG: RWRegister<u32>,
    pub PLL_SYS_SS: RWRegister<u32>,
    pub PLL_SYS_NUM: RWRegister<u32>,
    pub PLL_SYS_DENOM: RWRegister<u32>,
    pub PLL_AUDIO: RWRegister<u32>,
    pub PLL_AUDIO_SET: RWRegister<u32>,
    pub PLL_AUDIO_CLR: RWRegister<u32>,
    pub PLL_AUDIO_TOG: RWRegister<u32>,
    pub PLL_AUDIO_NUM: RWRegister<u32>,
    pub PLL_AUDIO_DENOM: RWRegister<u32>,
    pub PLL_VIDEO: RWRegister<u32>,
    pub PLL_VIDEO_SET: RWRegister<u32>,
    pub PLL_VIDEO_CLR: RWRegister<u32>,
    pub PLL_VIDEO_TOG: RWRegister<u32>,
    pub PLL_VIDEO_NUM: RWRegister<u32>,
    pub PLL_VIDEO_DENOM: RWRegister<u32>,
    pub PLL_ENET: RWRegister<u32>,
    pub PLL_ENET_SET: RWRegister<u32>,
    pub PLL_ENET_CLR: RWRegister<u32>,
    pub PLL_ENET_TOG: RWRegister<u32>,
    pub PFD_480: RWRegister<u32>,
    pub PFD_480_SET: RWRegister<u32>,
    pub PFD_480_CLR: RWRegister<u32>,
    pub PFD_480_TOG: RWRegister<u32>,
    pub PFD_528: RWRegister<u32>,
    pub PFD_528_SET: RWRegister<u32>,
    pub PFD_528_CLR: RWRegister<u32>,
    pub PFD_528_TOG: RWRegister<u32>,
    pub MISC0: RWRegister<u32>,
    pub MISC0_SET: RWRegister<u32>,
    pub MISC0_CLR: RWRegister<u32>,
    pub MISC0_TOG: RWRegister<u32>,
    pub MISC1: RWRegister<u32>,
    pub MISC1_SET: RWRegister<u32>,
    pub MISC1_CLR: RWRegister<u32>,
    pub MISC1_TOG: RWRegister<u32>,
    pub MISC2: RWRegister<u32>,
    pub MISC2_SET: RWRegister<u32>,
    pub MISC2_CLR: RWRegister<u32>,
    pub MISC2_TOG: RWRegister<u32>,
    /* private fields */
}

CCM_ANALOG

Fields

PLL_ARM: RWRegister<u32>

Analog ARM PLL control Register

PLL_ARM_SET: RWRegister<u32>

Analog ARM PLL control Register

PLL_ARM_CLR: RWRegister<u32>

Analog ARM PLL control Register

PLL_ARM_TOG: RWRegister<u32>

Analog ARM PLL control Register

PLL_USB1: RWRegister<u32>

Analog USB1 480MHz PLL Control Register

PLL_USB1_SET: RWRegister<u32>

Analog USB1 480MHz PLL Control Register

PLL_USB1_CLR: RWRegister<u32>

Analog USB1 480MHz PLL Control Register

PLL_USB1_TOG: RWRegister<u32>

Analog USB1 480MHz PLL Control Register

PLL_USB2: RWRegister<u32>

Analog USB2 480MHz PLL Control Register

PLL_USB2_SET: RWRegister<u32>

Analog USB2 480MHz PLL Control Register

PLL_USB2_CLR: RWRegister<u32>

Analog USB2 480MHz PLL Control Register

PLL_USB2_TOG: RWRegister<u32>

Analog USB2 480MHz PLL Control Register

PLL_SYS: RWRegister<u32>

Analog System PLL Control Register

PLL_SYS_SET: RWRegister<u32>

Analog System PLL Control Register

PLL_SYS_CLR: RWRegister<u32>

Analog System PLL Control Register

PLL_SYS_TOG: RWRegister<u32>

Analog System PLL Control Register

PLL_SYS_SS: RWRegister<u32>

528MHz System PLL Spread Spectrum Register

PLL_SYS_NUM: RWRegister<u32>

Numerator of 528MHz System PLL Fractional Loop Divider Register

PLL_SYS_DENOM: RWRegister<u32>

Denominator of 528MHz System PLL Fractional Loop Divider Register

PLL_AUDIO: RWRegister<u32>

Analog Audio PLL control Register

PLL_AUDIO_SET: RWRegister<u32>

Analog Audio PLL control Register

PLL_AUDIO_CLR: RWRegister<u32>

Analog Audio PLL control Register

PLL_AUDIO_TOG: RWRegister<u32>

Analog Audio PLL control Register

PLL_AUDIO_NUM: RWRegister<u32>

Numerator of Audio PLL Fractional Loop Divider Register

PLL_AUDIO_DENOM: RWRegister<u32>

Denominator of Audio PLL Fractional Loop Divider Register

PLL_VIDEO: RWRegister<u32>

Analog Video PLL control Register

PLL_VIDEO_SET: RWRegister<u32>

Analog Video PLL control Register

PLL_VIDEO_CLR: RWRegister<u32>

Analog Video PLL control Register

PLL_VIDEO_TOG: RWRegister<u32>

Analog Video PLL control Register

PLL_VIDEO_NUM: RWRegister<u32>

Numerator of Video PLL Fractional Loop Divider Register

PLL_VIDEO_DENOM: RWRegister<u32>

Denominator of Video PLL Fractional Loop Divider Register

PLL_ENET: RWRegister<u32>

Analog ENET PLL Control Register

PLL_ENET_SET: RWRegister<u32>

Analog ENET PLL Control Register

PLL_ENET_CLR: RWRegister<u32>

Analog ENET PLL Control Register

PLL_ENET_TOG: RWRegister<u32>

Analog ENET PLL Control Register

PFD_480: RWRegister<u32>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_480_SET: RWRegister<u32>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_480_CLR: RWRegister<u32>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_480_TOG: RWRegister<u32>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

PFD_528: RWRegister<u32>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

PFD_528_SET: RWRegister<u32>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

PFD_528_CLR: RWRegister<u32>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

PFD_528_TOG: RWRegister<u32>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

MISC0: RWRegister<u32>

Miscellaneous Register 0

MISC0_SET: RWRegister<u32>

Miscellaneous Register 0

MISC0_CLR: RWRegister<u32>

Miscellaneous Register 0

MISC0_TOG: RWRegister<u32>

Miscellaneous Register 0

MISC1: RWRegister<u32>

Miscellaneous Register 1

MISC1_SET: RWRegister<u32>

Miscellaneous Register 1

MISC1_CLR: RWRegister<u32>

Miscellaneous Register 1

MISC1_TOG: RWRegister<u32>

Miscellaneous Register 1

MISC2: RWRegister<u32>

Miscellaneous Register 2

MISC2_SET: RWRegister<u32>

Miscellaneous Register 2

MISC2_CLR: RWRegister<u32>

Miscellaneous Register 2

MISC2_TOG: RWRegister<u32>

Miscellaneous Register 2