1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574
#![allow(non_snake_case, non_upper_case_globals)] #![allow(non_camel_case_types)] //! I2S use crate::{RORegister, RWRegister}; #[cfg(not(feature = "nosync"))] use core::marker::PhantomData; /// Version ID Register pub mod VERID { /// Feature Specification Number pub mod FEATURE { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (16 bits: 0xffff << 0) pub const mask: u32 = 0xffff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0000000000000000: Standard feature set. pub const FEATURE_0: u32 = 0b0000000000000000; } } /// Minor Version Number pub mod MINOR { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (8 bits: 0xff << 16) pub const mask: u32 = 0xff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Major Version Number pub mod MAJOR { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (8 bits: 0xff << 24) pub const mask: u32 = 0xff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// Parameter Register pub mod PARAM { /// Number of Datalines pub mod DATALINE { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (4 bits: 0b1111 << 0) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// FIFO Size pub mod FIFO { /// Offset (8 bits) pub const offset: u32 = 8; /// Mask (4 bits: 0b1111 << 8) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Frame Size pub mod FRAME { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (4 bits: 0b1111 << 16) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Transmit Control Register pub mod TCSR { /// FIFO Request DMA Enable pub mod FRDE { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (1 bit: 1 << 0) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the DMA request. pub const FRDE_0: u32 = 0b0; /// 0b1: Enables the DMA request. pub const FRDE_1: u32 = 0b1; } } /// FIFO Warning DMA Enable pub mod FWDE { /// Offset (1 bits) pub const offset: u32 = 1; /// Mask (1 bit: 1 << 1) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the DMA request. pub const FWDE_0: u32 = 0b0; /// 0b1: Enables the DMA request. pub const FWDE_1: u32 = 0b1; } } /// FIFO Request Interrupt Enable pub mod FRIE { /// Offset (8 bits) pub const offset: u32 = 8; /// Mask (1 bit: 1 << 8) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the interrupt. pub const FRIE_0: u32 = 0b0; /// 0b1: Enables the interrupt. pub const FRIE_1: u32 = 0b1; } } /// FIFO Warning Interrupt Enable pub mod FWIE { /// Offset (9 bits) pub const offset: u32 = 9; /// Mask (1 bit: 1 << 9) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the interrupt. pub const FWIE_0: u32 = 0b0; /// 0b1: Enables the interrupt. pub const FWIE_1: u32 = 0b1; } } /// FIFO Error Interrupt Enable pub mod FEIE { /// Offset (10 bits) pub const offset: u32 = 10; /// Mask (1 bit: 1 << 10) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the interrupt. pub const FEIE_0: u32 = 0b0; /// 0b1: Enables the interrupt. pub const FEIE_1: u32 = 0b1; } } /// Sync Error Interrupt Enable pub mod SEIE { /// Offset (11 bits) pub const offset: u32 = 11; /// Mask (1 bit: 1 << 11) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables interrupt. pub const SEIE_0: u32 = 0b0; /// 0b1: Enables interrupt. pub const SEIE_1: u32 = 0b1; } } /// Word Start Interrupt Enable pub mod WSIE { /// Offset (12 bits) pub const offset: u32 = 12; /// Mask (1 bit: 1 << 12) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables interrupt. pub const WSIE_0: u32 = 0b0; /// 0b1: Enables interrupt. pub const WSIE_1: u32 = 0b1; } } /// FIFO Request Flag pub mod FRF { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (1 bit: 1 << 16) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Transmit FIFO watermark has not been reached. pub const FRF_0: u32 = 0b0; /// 0b1: Transmit FIFO watermark has been reached. pub const FRF_1: u32 = 0b1; } } /// FIFO Warning Flag pub mod FWF { /// Offset (17 bits) pub const offset: u32 = 17; /// Mask (1 bit: 1 << 17) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No enabled transmit FIFO is empty. pub const FWF_0: u32 = 0b0; /// 0b1: Enabled transmit FIFO is empty. pub const FWF_1: u32 = 0b1; } } /// FIFO Error Flag pub mod FEF { /// Offset (18 bits) pub const offset: u32 = 18; /// Mask (1 bit: 1 << 18) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Transmit underrun not detected. pub const FEF_0: u32 = 0b0; /// 0b1: Transmit underrun detected. pub const FEF_1: u32 = 0b1; } } /// Sync Error Flag pub mod SEF { /// Offset (19 bits) pub const offset: u32 = 19; /// Mask (1 bit: 1 << 19) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Sync error not detected. pub const SEF_0: u32 = 0b0; /// 0b1: Frame sync error detected. pub const SEF_1: u32 = 0b1; } } /// Word Start Flag pub mod WSF { /// Offset (20 bits) pub const offset: u32 = 20; /// Mask (1 bit: 1 << 20) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Start of word not detected. pub const WSF_0: u32 = 0b0; /// 0b1: Start of word detected. pub const WSF_1: u32 = 0b1; } } /// Software Reset pub mod SR { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (1 bit: 1 << 24) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const SR_0: u32 = 0b0; /// 0b1: Software reset. pub const SR_1: u32 = 0b1; } } /// FIFO Reset pub mod FR { /// Offset (25 bits) pub const offset: u32 = 25; /// Mask (1 bit: 1 << 25) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const FR_0: u32 = 0b0; /// 0b1: FIFO reset. pub const FR_1: u32 = 0b1; } } /// Bit Clock Enable pub mod BCE { /// Offset (28 bits) pub const offset: u32 = 28; /// Mask (1 bit: 1 << 28) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Transmit bit clock is disabled. pub const BCE_0: u32 = 0b0; /// 0b1: Transmit bit clock is enabled. pub const BCE_1: u32 = 0b1; } } /// Debug Enable pub mod DBGE { /// Offset (29 bits) pub const offset: u32 = 29; /// Mask (1 bit: 1 << 29) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Transmitter is disabled in Debug mode, after completing the current frame. pub const DBGE_0: u32 = 0b0; /// 0b1: Transmitter is enabled in Debug mode. pub const DBGE_1: u32 = 0b1; } } /// Stop Enable pub mod STOPE { /// Offset (30 bits) pub const offset: u32 = 30; /// Mask (1 bit: 1 << 30) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Transmitter disabled in Stop mode. pub const STOPE_0: u32 = 0b0; /// 0b1: Transmitter enabled in Stop mode. pub const STOPE_1: u32 = 0b1; } } /// Transmitter Enable pub mod TE { /// Offset (31 bits) pub const offset: u32 = 31; /// Mask (1 bit: 1 << 31) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Transmitter is disabled. pub const TE_0: u32 = 0b0; /// 0b1: Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. pub const TE_1: u32 = 0b1; } } } /// SAI Transmit Configuration 1 Register pub mod TCR1 { /// Transmit FIFO Watermark pub mod TFW { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (5 bits: 0b11111 << 0) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Transmit Configuration 2 Register pub mod TCR2 { /// Bit Clock Divide pub mod DIV { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (8 bits: 0xff << 0) pub const mask: u32 = 0xff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Bit Clock Direction pub mod BCD { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (1 bit: 1 << 24) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Bit clock is generated externally in Slave mode. pub const BCD_0: u32 = 0b0; /// 0b1: Bit clock is generated internally in Master mode. pub const BCD_1: u32 = 0b1; } } /// Bit Clock Polarity pub mod BCP { /// Offset (25 bits) pub const offset: u32 = 25; /// Mask (1 bit: 1 << 25) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. pub const BCP_0: u32 = 0b0; /// 0b1: Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. pub const BCP_1: u32 = 0b1; } } /// MCLK Select pub mod MSEL { /// Offset (26 bits) pub const offset: u32 = 26; /// Mask (2 bits: 0b11 << 26) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: Bus Clock selected. pub const MSEL_0: u32 = 0b00; /// 0b01: Master Clock (MCLK) 1 option selected. pub const MSEL_1: u32 = 0b01; /// 0b10: Master Clock (MCLK) 2 option selected. pub const MSEL_2: u32 = 0b10; /// 0b11: Master Clock (MCLK) 3 option selected. pub const MSEL_3: u32 = 0b11; } } /// Bit Clock Input pub mod BCI { /// Offset (28 bits) pub const offset: u32 = 28; /// Mask (1 bit: 1 << 28) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const BCI_0: u32 = 0b0; /// 0b1: Internal logic is clocked as if bit clock was externally generated. pub const BCI_1: u32 = 0b1; } } /// Bit Clock Swap pub mod BCS { /// Offset (29 bits) pub const offset: u32 = 29; /// Mask (1 bit: 1 << 29) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Use the normal bit clock source. pub const BCS_0: u32 = 0b0; /// 0b1: Swap the bit clock source. pub const BCS_1: u32 = 0b1; } } /// Synchronous Mode pub mod SYNC { /// Offset (30 bits) pub const offset: u32 = 30; /// Mask (2 bits: 0b11 << 30) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: Asynchronous mode. pub const SYNC_0: u32 = 0b00; /// 0b01: Synchronous with receiver. pub const SYNC_1: u32 = 0b01; } } } /// SAI Transmit Configuration 3 Register pub mod TCR3 { /// Word Flag Configuration pub mod WDFL { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (5 bits: 0b11111 << 0) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Transmit Channel Enable pub mod TCE { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (4 bits: 0b1111 << 16) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Channel FIFO Reset pub mod CFR { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (4 bits: 0b1111 << 24) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Transmit Configuration 4 Register pub mod TCR4 { /// Frame Sync Direction pub mod FSD { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (1 bit: 1 << 0) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Frame sync is generated externally in Slave mode. pub const FSD_0: u32 = 0b0; /// 0b1: Frame sync is generated internally in Master mode. pub const FSD_1: u32 = 0b1; } } /// Frame Sync Polarity pub mod FSP { /// Offset (1 bits) pub const offset: u32 = 1; /// Mask (1 bit: 1 << 1) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Frame sync is active high. pub const FSP_0: u32 = 0b0; /// 0b1: Frame sync is active low. pub const FSP_1: u32 = 0b1; } } /// On Demand Mode pub mod ONDEM { /// Offset (2 bits) pub const offset: u32 = 2; /// Mask (1 bit: 1 << 2) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Internal frame sync is generated continuously. pub const ONDEM_0: u32 = 0b0; /// 0b1: Internal frame sync is generated when the FIFO warning flag is clear. pub const ONDEM_1: u32 = 0b1; } } /// Frame Sync Early pub mod FSE { /// Offset (3 bits) pub const offset: u32 = 3; /// Mask (1 bit: 1 << 3) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Frame sync asserts with the first bit of the frame. pub const FSE_0: u32 = 0b0; /// 0b1: Frame sync asserts one bit before the first bit of the frame. pub const FSE_1: u32 = 0b1; } } /// MSB First pub mod MF { /// Offset (4 bits) pub const offset: u32 = 4; /// Mask (1 bit: 1 << 4) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: LSB is transmitted first. pub const MF_0: u32 = 0b0; /// 0b1: MSB is transmitted first. pub const MF_1: u32 = 0b1; } } /// Channel Mode pub mod CHMOD { /// Offset (5 bits) pub const offset: u32 = 5; /// Mask (1 bit: 1 << 5) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. pub const CHMOD_0: u32 = 0b0; /// 0b1: Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. pub const CHMOD_1: u32 = 0b1; } } /// Sync Width pub mod SYWD { /// Offset (8 bits) pub const offset: u32 = 8; /// Mask (5 bits: 0b11111 << 8) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Frame size pub mod FRSZ { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (5 bits: 0b11111 << 16) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// FIFO Packing Mode pub mod FPACK { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (2 bits: 0b11 << 24) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: FIFO packing is disabled pub const FPACK_0: u32 = 0b00; /// 0b10: 8-bit FIFO packing is enabled pub const FPACK_2: u32 = 0b10; /// 0b11: 16-bit FIFO packing is enabled pub const FPACK_3: u32 = 0b11; } } /// FIFO Combine Mode pub mod FCOMB { /// Offset (26 bits) pub const offset: u32 = 26; /// Mask (2 bits: 0b11 << 26) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: FIFO combine mode disabled. pub const FCOMB_0: u32 = 0b00; /// 0b01: FIFO combine mode enabled on FIFO reads (from transmit shift registers). pub const FCOMB_1: u32 = 0b01; /// 0b10: FIFO combine mode enabled on FIFO writes (by software). pub const FCOMB_2: u32 = 0b10; /// 0b11: FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). pub const FCOMB_3: u32 = 0b11; } } /// FIFO Continue on Error pub mod FCONT { /// Offset (28 bits) pub const offset: u32 = 28; /// Mask (1 bit: 1 << 28) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. pub const FCONT_0: u32 = 0b0; /// 0b1: On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. pub const FCONT_1: u32 = 0b1; } } } /// SAI Transmit Configuration 5 Register pub mod TCR5 { /// First Bit Shifted pub mod FBT { /// Offset (8 bits) pub const offset: u32 = 8; /// Mask (5 bits: 0b11111 << 8) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Word 0 Width pub mod W0W { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (5 bits: 0b11111 << 16) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Word N Width pub mod WNW { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (5 bits: 0b11111 << 24) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Transmit Data Register pub mod TDR0 { /// Transmit Data Register pub mod TDR { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (32 bits: 0xffffffff << 0) pub const mask: u32 = 0xffffffff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Transmit Data Register pub mod TDR1 { pub use super::TDR0::TDR; } /// SAI Transmit Data Register pub mod TDR2 { pub use super::TDR0::TDR; } /// SAI Transmit Data Register pub mod TDR3 { pub use super::TDR0::TDR; } /// SAI Transmit FIFO Register pub mod TFR0 { /// Read FIFO Pointer pub mod RFP { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (6 bits: 0x3f << 0) pub const mask: u32 = 0x3f << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Write FIFO Pointer pub mod WFP { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (6 bits: 0x3f << 16) pub const mask: u32 = 0x3f << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Write Channel Pointer pub mod WCP { /// Offset (31 bits) pub const offset: u32 = 31; /// Mask (1 bit: 1 << 31) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const WCP_0: u32 = 0b0; /// 0b1: FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. pub const WCP_1: u32 = 0b1; } } } /// SAI Transmit FIFO Register pub mod TFR1 { pub use super::TFR0::RFP; pub use super::TFR0::WCP; pub use super::TFR0::WFP; } /// SAI Transmit FIFO Register pub mod TFR2 { pub use super::TFR0::RFP; pub use super::TFR0::WCP; pub use super::TFR0::WFP; } /// SAI Transmit FIFO Register pub mod TFR3 { pub use super::TFR0::RFP; pub use super::TFR0::WCP; pub use super::TFR0::WFP; } /// SAI Transmit Mask Register pub mod TMR { /// Transmit Word Mask pub mod TWM { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (32 bits: 0xffffffff << 0) pub const mask: u32 = 0xffffffff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00000000000000000000000000000000: Word N is enabled. pub const TWM_0: u32 = 0b00000000000000000000000000000000; /// 0b00000000000000000000000000000001: Word N is masked. The transmit data pins are tri-stated or drive zero when masked. pub const TWM_1: u32 = 0b00000000000000000000000000000001; } } } /// SAI Receive Control Register pub mod RCSR { /// FIFO Request DMA Enable pub mod FRDE { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (1 bit: 1 << 0) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the DMA request. pub const FRDE_0: u32 = 0b0; /// 0b1: Enables the DMA request. pub const FRDE_1: u32 = 0b1; } } /// FIFO Warning DMA Enable pub mod FWDE { /// Offset (1 bits) pub const offset: u32 = 1; /// Mask (1 bit: 1 << 1) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the DMA request. pub const FWDE_0: u32 = 0b0; /// 0b1: Enables the DMA request. pub const FWDE_1: u32 = 0b1; } } /// FIFO Request Interrupt Enable pub mod FRIE { /// Offset (8 bits) pub const offset: u32 = 8; /// Mask (1 bit: 1 << 8) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the interrupt. pub const FRIE_0: u32 = 0b0; /// 0b1: Enables the interrupt. pub const FRIE_1: u32 = 0b1; } } /// FIFO Warning Interrupt Enable pub mod FWIE { /// Offset (9 bits) pub const offset: u32 = 9; /// Mask (1 bit: 1 << 9) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the interrupt. pub const FWIE_0: u32 = 0b0; /// 0b1: Enables the interrupt. pub const FWIE_1: u32 = 0b1; } } /// FIFO Error Interrupt Enable pub mod FEIE { /// Offset (10 bits) pub const offset: u32 = 10; /// Mask (1 bit: 1 << 10) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables the interrupt. pub const FEIE_0: u32 = 0b0; /// 0b1: Enables the interrupt. pub const FEIE_1: u32 = 0b1; } } /// Sync Error Interrupt Enable pub mod SEIE { /// Offset (11 bits) pub const offset: u32 = 11; /// Mask (1 bit: 1 << 11) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables interrupt. pub const SEIE_0: u32 = 0b0; /// 0b1: Enables interrupt. pub const SEIE_1: u32 = 0b1; } } /// Word Start Interrupt Enable pub mod WSIE { /// Offset (12 bits) pub const offset: u32 = 12; /// Mask (1 bit: 1 << 12) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Disables interrupt. pub const WSIE_0: u32 = 0b0; /// 0b1: Enables interrupt. pub const WSIE_1: u32 = 0b1; } } /// FIFO Request Flag pub mod FRF { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (1 bit: 1 << 16) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Receive FIFO watermark not reached. pub const FRF_0: u32 = 0b0; /// 0b1: Receive FIFO watermark has been reached. pub const FRF_1: u32 = 0b1; } } /// FIFO Warning Flag pub mod FWF { /// Offset (17 bits) pub const offset: u32 = 17; /// Mask (1 bit: 1 << 17) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No enabled receive FIFO is full. pub const FWF_0: u32 = 0b0; /// 0b1: Enabled receive FIFO is full. pub const FWF_1: u32 = 0b1; } } /// FIFO Error Flag pub mod FEF { /// Offset (18 bits) pub const offset: u32 = 18; /// Mask (1 bit: 1 << 18) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Receive overflow not detected. pub const FEF_0: u32 = 0b0; /// 0b1: Receive overflow detected. pub const FEF_1: u32 = 0b1; } } /// Sync Error Flag pub mod SEF { /// Offset (19 bits) pub const offset: u32 = 19; /// Mask (1 bit: 1 << 19) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Sync error not detected. pub const SEF_0: u32 = 0b0; /// 0b1: Frame sync error detected. pub const SEF_1: u32 = 0b1; } } /// Word Start Flag pub mod WSF { /// Offset (20 bits) pub const offset: u32 = 20; /// Mask (1 bit: 1 << 20) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Start of word not detected. pub const WSF_0: u32 = 0b0; /// 0b1: Start of word detected. pub const WSF_1: u32 = 0b1; } } /// Software Reset pub mod SR { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (1 bit: 1 << 24) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const SR_0: u32 = 0b0; /// 0b1: Software reset. pub const SR_1: u32 = 0b1; } } /// FIFO Reset pub mod FR { /// Offset (25 bits) pub const offset: u32 = 25; /// Mask (1 bit: 1 << 25) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const FR_0: u32 = 0b0; /// 0b1: FIFO reset. pub const FR_1: u32 = 0b1; } } /// Bit Clock Enable pub mod BCE { /// Offset (28 bits) pub const offset: u32 = 28; /// Mask (1 bit: 1 << 28) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Receive bit clock is disabled. pub const BCE_0: u32 = 0b0; /// 0b1: Receive bit clock is enabled. pub const BCE_1: u32 = 0b1; } } /// Debug Enable pub mod DBGE { /// Offset (29 bits) pub const offset: u32 = 29; /// Mask (1 bit: 1 << 29) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Receiver is disabled in Debug mode, after completing the current frame. pub const DBGE_0: u32 = 0b0; /// 0b1: Receiver is enabled in Debug mode. pub const DBGE_1: u32 = 0b1; } } /// Stop Enable pub mod STOPE { /// Offset (30 bits) pub const offset: u32 = 30; /// Mask (1 bit: 1 << 30) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Receiver disabled in Stop mode. pub const STOPE_0: u32 = 0b0; /// 0b1: Receiver enabled in Stop mode. pub const STOPE_1: u32 = 0b1; } } /// Receiver Enable pub mod RE { /// Offset (31 bits) pub const offset: u32 = 31; /// Mask (1 bit: 1 << 31) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Receiver is disabled. pub const RE_0: u32 = 0b0; /// 0b1: Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. pub const RE_1: u32 = 0b1; } } } /// SAI Receive Configuration 1 Register pub mod RCR1 { /// Receive FIFO Watermark pub mod RFW { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (5 bits: 0b11111 << 0) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Receive Configuration 2 Register pub mod RCR2 { /// Bit Clock Divide pub mod DIV { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (8 bits: 0xff << 0) pub const mask: u32 = 0xff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Bit Clock Direction pub mod BCD { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (1 bit: 1 << 24) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Bit clock is generated externally in Slave mode. pub const BCD_0: u32 = 0b0; /// 0b1: Bit clock is generated internally in Master mode. pub const BCD_1: u32 = 0b1; } } /// Bit Clock Polarity pub mod BCP { /// Offset (25 bits) pub const offset: u32 = 25; /// Mask (1 bit: 1 << 25) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. pub const BCP_0: u32 = 0b0; /// 0b1: Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. pub const BCP_1: u32 = 0b1; } } /// MCLK Select pub mod MSEL { /// Offset (26 bits) pub const offset: u32 = 26; /// Mask (2 bits: 0b11 << 26) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: Bus Clock selected. pub const MSEL_0: u32 = 0b00; /// 0b01: Master Clock (MCLK) 1 option selected. pub const MSEL_1: u32 = 0b01; /// 0b10: Master Clock (MCLK) 2 option selected. pub const MSEL_2: u32 = 0b10; /// 0b11: Master Clock (MCLK) 3 option selected. pub const MSEL_3: u32 = 0b11; } } /// Bit Clock Input pub mod BCI { /// Offset (28 bits) pub const offset: u32 = 28; /// Mask (1 bit: 1 << 28) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const BCI_0: u32 = 0b0; /// 0b1: Internal logic is clocked as if bit clock was externally generated. pub const BCI_1: u32 = 0b1; } } /// Bit Clock Swap pub mod BCS { /// Offset (29 bits) pub const offset: u32 = 29; /// Mask (1 bit: 1 << 29) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Use the normal bit clock source. pub const BCS_0: u32 = 0b0; /// 0b1: Swap the bit clock source. pub const BCS_1: u32 = 0b1; } } /// Synchronous Mode pub mod SYNC { /// Offset (30 bits) pub const offset: u32 = 30; /// Mask (2 bits: 0b11 << 30) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: Asynchronous mode. pub const SYNC_0: u32 = 0b00; /// 0b01: Synchronous with transmitter. pub const SYNC_1: u32 = 0b01; } } } /// SAI Receive Configuration 3 Register pub mod RCR3 { /// Word Flag Configuration pub mod WDFL { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (5 bits: 0b11111 << 0) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Receive Channel Enable pub mod RCE { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (4 bits: 0b1111 << 16) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Channel FIFO Reset pub mod CFR { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (4 bits: 0b1111 << 24) pub const mask: u32 = 0b1111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Receive Configuration 4 Register pub mod RCR4 { /// Frame Sync Direction pub mod FSD { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (1 bit: 1 << 0) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Frame Sync is generated externally in Slave mode. pub const FSD_0: u32 = 0b0; /// 0b1: Frame Sync is generated internally in Master mode. pub const FSD_1: u32 = 0b1; } } /// Frame Sync Polarity pub mod FSP { /// Offset (1 bits) pub const offset: u32 = 1; /// Mask (1 bit: 1 << 1) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Frame sync is active high. pub const FSP_0: u32 = 0b0; /// 0b1: Frame sync is active low. pub const FSP_1: u32 = 0b1; } } /// On Demand Mode pub mod ONDEM { /// Offset (2 bits) pub const offset: u32 = 2; /// Mask (1 bit: 1 << 2) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Internal frame sync is generated continuously. pub const ONDEM_0: u32 = 0b0; /// 0b1: Internal frame sync is generated when the FIFO warning flag is clear. pub const ONDEM_1: u32 = 0b1; } } /// Frame Sync Early pub mod FSE { /// Offset (3 bits) pub const offset: u32 = 3; /// Mask (1 bit: 1 << 3) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: Frame sync asserts with the first bit of the frame. pub const FSE_0: u32 = 0b0; /// 0b1: Frame sync asserts one bit before the first bit of the frame. pub const FSE_1: u32 = 0b1; } } /// MSB First pub mod MF { /// Offset (4 bits) pub const offset: u32 = 4; /// Mask (1 bit: 1 << 4) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: LSB is received first. pub const MF_0: u32 = 0b0; /// 0b1: MSB is received first. pub const MF_1: u32 = 0b1; } } /// Sync Width pub mod SYWD { /// Offset (8 bits) pub const offset: u32 = 8; /// Mask (5 bits: 0b11111 << 8) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Frame Size pub mod FRSZ { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (5 bits: 0b11111 << 16) pub const mask: u32 = 0b11111 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// FIFO Packing Mode pub mod FPACK { /// Offset (24 bits) pub const offset: u32 = 24; /// Mask (2 bits: 0b11 << 24) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: FIFO packing is disabled pub const FPACK_0: u32 = 0b00; /// 0b10: 8-bit FIFO packing is enabled pub const FPACK_2: u32 = 0b10; /// 0b11: 16-bit FIFO packing is enabled pub const FPACK_3: u32 = 0b11; } } /// FIFO Combine Mode pub mod FCOMB { /// Offset (26 bits) pub const offset: u32 = 26; /// Mask (2 bits: 0b11 << 26) pub const mask: u32 = 0b11 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00: FIFO combine mode disabled. pub const FCOMB_0: u32 = 0b00; /// 0b01: FIFO combine mode enabled on FIFO writes (from receive shift registers). pub const FCOMB_1: u32 = 0b01; /// 0b10: FIFO combine mode enabled on FIFO reads (by software). pub const FCOMB_2: u32 = 0b10; /// 0b11: FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). pub const FCOMB_3: u32 = 0b11; } } /// FIFO Continue on Error pub mod FCONT { /// Offset (28 bits) pub const offset: u32 = 28; /// Mask (1 bit: 1 << 28) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. pub const FCONT_0: u32 = 0b0; /// 0b1: On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. pub const FCONT_1: u32 = 0b1; } } } /// SAI Receive Configuration 5 Register pub mod RCR5 { pub use super::TCR5::FBT; pub use super::TCR5::W0W; pub use super::TCR5::WNW; } /// SAI Receive Data Register pub mod RDR0 { /// Receive Data Register pub mod RDR { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (32 bits: 0xffffffff << 0) pub const mask: u32 = 0xffffffff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Receive Data Register pub mod RDR1 { pub use super::RDR0::RDR; } /// SAI Receive Data Register pub mod RDR2 { pub use super::RDR0::RDR; } /// SAI Receive Data Register pub mod RDR3 { pub use super::RDR0::RDR; } /// SAI Receive FIFO Register pub mod RFR0 { /// Read FIFO Pointer pub mod RFP { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (6 bits: 0x3f << 0) pub const mask: u32 = 0x3f << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } /// Receive Channel Pointer pub mod RCP { /// Offset (15 bits) pub const offset: u32 = 15; /// Mask (1 bit: 1 << 15) pub const mask: u32 = 1 << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b0: No effect. pub const RCP_0: u32 = 0b0; /// 0b1: FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. pub const RCP_1: u32 = 0b1; } } /// Write FIFO Pointer pub mod WFP { /// Offset (16 bits) pub const offset: u32 = 16; /// Mask (6 bits: 0x3f << 16) pub const mask: u32 = 0x3f << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values (empty) pub mod RW {} } } /// SAI Receive FIFO Register pub mod RFR1 { pub use super::RFR0::RCP; pub use super::RFR0::RFP; pub use super::RFR0::WFP; } /// SAI Receive FIFO Register pub mod RFR2 { pub use super::RFR0::RCP; pub use super::RFR0::RFP; pub use super::RFR0::WFP; } /// SAI Receive FIFO Register pub mod RFR3 { pub use super::RFR0::RCP; pub use super::RFR0::RFP; pub use super::RFR0::WFP; } /// SAI Receive Mask Register pub mod RMR { /// Receive Word Mask pub mod RWM { /// Offset (0 bits) pub const offset: u32 = 0; /// Mask (32 bits: 0xffffffff << 0) pub const mask: u32 = 0xffffffff << offset; /// Read-only values (empty) pub mod R {} /// Write-only values (empty) pub mod W {} /// Read-write values pub mod RW { /// 0b00000000000000000000000000000000: Word N is enabled. pub const RWM_0: u32 = 0b00000000000000000000000000000000; /// 0b00000000000000000000000000000001: Word N is masked. pub const RWM_1: u32 = 0b00000000000000000000000000000001; } } } #[repr(C)] pub struct RegisterBlock { /// Version ID Register pub VERID: RORegister<u32>, /// Parameter Register pub PARAM: RORegister<u32>, /// SAI Transmit Control Register pub TCSR: RWRegister<u32>, /// SAI Transmit Configuration 1 Register pub TCR1: RWRegister<u32>, /// SAI Transmit Configuration 2 Register pub TCR2: RWRegister<u32>, /// SAI Transmit Configuration 3 Register pub TCR3: RWRegister<u32>, /// SAI Transmit Configuration 4 Register pub TCR4: RWRegister<u32>, /// SAI Transmit Configuration 5 Register pub TCR5: RWRegister<u32>, /// SAI Transmit Data Register pub TDR0: RWRegister<u32>, /// SAI Transmit Data Register pub TDR1: RWRegister<u32>, /// SAI Transmit Data Register pub TDR2: RWRegister<u32>, /// SAI Transmit Data Register pub TDR3: RWRegister<u32>, _reserved1: [u32; 4], /// SAI Transmit FIFO Register pub TFR0: RORegister<u32>, /// SAI Transmit FIFO Register pub TFR1: RORegister<u32>, /// SAI Transmit FIFO Register pub TFR2: RORegister<u32>, /// SAI Transmit FIFO Register pub TFR3: RORegister<u32>, _reserved2: [u32; 4], /// SAI Transmit Mask Register pub TMR: RWRegister<u32>, _reserved3: [u32; 9], /// SAI Receive Control Register pub RCSR: RWRegister<u32>, /// SAI Receive Configuration 1 Register pub RCR1: RWRegister<u32>, /// SAI Receive Configuration 2 Register pub RCR2: RWRegister<u32>, /// SAI Receive Configuration 3 Register pub RCR3: RWRegister<u32>, /// SAI Receive Configuration 4 Register pub RCR4: RWRegister<u32>, /// SAI Receive Configuration 5 Register pub RCR5: RWRegister<u32>, /// SAI Receive Data Register pub RDR0: RORegister<u32>, /// SAI Receive Data Register pub RDR1: RORegister<u32>, /// SAI Receive Data Register pub RDR2: RORegister<u32>, /// SAI Receive Data Register pub RDR3: RORegister<u32>, _reserved4: [u32; 4], /// SAI Receive FIFO Register pub RFR0: RORegister<u32>, /// SAI Receive FIFO Register pub RFR1: RORegister<u32>, /// SAI Receive FIFO Register pub RFR2: RORegister<u32>, /// SAI Receive FIFO Register pub RFR3: RORegister<u32>, _reserved5: [u32; 4], /// SAI Receive Mask Register pub RMR: RWRegister<u32>, } pub struct ResetValues { pub VERID: u32, pub PARAM: u32, pub TCSR: u32, pub TCR1: u32, pub TCR2: u32, pub TCR3: u32, pub TCR4: u32, pub TCR5: u32, pub TDR0: u32, pub TDR1: u32, pub TDR2: u32, pub TDR3: u32, pub TFR0: u32, pub TFR1: u32, pub TFR2: u32, pub TFR3: u32, pub TMR: u32, pub RCSR: u32, pub RCR1: u32, pub RCR2: u32, pub RCR3: u32, pub RCR4: u32, pub RCR5: u32, pub RDR0: u32, pub RDR1: u32, pub RDR2: u32, pub RDR3: u32, pub RFR0: u32, pub RFR1: u32, pub RFR2: u32, pub RFR3: u32, pub RMR: u32, } #[cfg(not(feature = "nosync"))] pub struct Instance { pub(crate) addr: u32, pub(crate) _marker: PhantomData<*const RegisterBlock>, } #[cfg(not(feature = "nosync"))] impl ::core::ops::Deref for Instance { type Target = RegisterBlock; #[inline(always)] fn deref(&self) -> &RegisterBlock { unsafe { &*(self.addr as *const _) } } } unsafe impl Send for Instance {} /// Access functions for the SAI1 peripheral instance pub mod SAI1 { use super::ResetValues; #[cfg(not(feature = "nosync"))] use super::Instance; #[cfg(not(feature = "nosync"))] const INSTANCE: Instance = Instance { addr: 0x40384000, _marker: ::core::marker::PhantomData, }; /// Reset values for each field in SAI1 pub const reset: ResetValues = ResetValues { VERID: 0x03000000, PARAM: 0x00050504, TCSR: 0x00000000, TCR1: 0x00000000, TCR2: 0x00000000, TCR3: 0x00000000, TCR4: 0x00000000, TCR5: 0x00000000, TDR0: 0x00000000, TDR1: 0x00000000, TDR2: 0x00000000, TDR3: 0x00000000, TFR0: 0x00000000, TFR1: 0x00000000, TFR2: 0x00000000, TFR3: 0x00000000, TMR: 0x00000000, RCSR: 0x00000000, RCR1: 0x00000000, RCR2: 0x00000000, RCR3: 0x00000000, RCR4: 0x00000000, RCR5: 0x00000000, RDR0: 0x00000000, RDR1: 0x00000000, RDR2: 0x00000000, RDR3: 0x00000000, RFR0: 0x00000000, RFR1: 0x00000000, RFR2: 0x00000000, RFR3: 0x00000000, RMR: 0x00000000, }; #[cfg(not(feature = "nosync"))] #[allow(renamed_and_removed_lints)] #[allow(private_no_mangle_statics)] #[no_mangle] static mut SAI1_TAKEN: bool = false; /// Safe access to SAI1 /// /// This function returns `Some(Instance)` if this instance is not /// currently taken, and `None` if it is. This ensures that if you /// do get `Some(Instance)`, you are ensured unique access to /// the peripheral and there cannot be data races (unless other /// code uses `unsafe`, of course). You can then pass the /// `Instance` around to other functions as required. When you're /// done with it, you can call `release(instance)` to return it. /// /// `Instance` itself dereferences to a `RegisterBlock`, which /// provides access to the peripheral's registers. #[cfg(not(feature = "nosync"))] #[inline] pub fn take() -> Option<Instance> { external_cortex_m::interrupt::free(|_| unsafe { if SAI1_TAKEN { None } else { SAI1_TAKEN = true; Some(INSTANCE) } }) } /// Release exclusive access to SAI1 /// /// This function allows you to return an `Instance` so that it /// is available to `take()` again. This function will panic if /// you return a different `Instance` or if this instance is not /// already taken. #[cfg(not(feature = "nosync"))] #[inline] pub fn release(inst: Instance) { external_cortex_m::interrupt::free(|_| unsafe { if SAI1_TAKEN && inst.addr == INSTANCE.addr { SAI1_TAKEN = false; } else { panic!("Released a peripheral which was not taken"); } }); } /// Unsafely steal SAI1 /// /// This function is similar to take() but forcibly takes the /// Instance, marking it as taken irregardless of its previous /// state. #[cfg(not(feature = "nosync"))] #[inline] pub unsafe fn steal() -> Instance { SAI1_TAKEN = true; INSTANCE } } /// Raw pointer to SAI1 /// /// Dereferencing this is unsafe because you are not ensured unique /// access to the peripheral, so you may encounter data races with /// other users of this peripheral. It is up to you to ensure you /// will not cause data races. /// /// This constant is provided for ease of use in unsafe code: you can /// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`. pub const SAI1: *const RegisterBlock = 0x40384000 as *const _; /// Access functions for the SAI2 peripheral instance pub mod SAI2 { use super::ResetValues; #[cfg(not(feature = "nosync"))] use super::Instance; #[cfg(not(feature = "nosync"))] const INSTANCE: Instance = Instance { addr: 0x40388000, _marker: ::core::marker::PhantomData, }; /// Reset values for each field in SAI2 pub const reset: ResetValues = ResetValues { VERID: 0x03000000, PARAM: 0x00050504, TCSR: 0x00000000, TCR1: 0x00000000, TCR2: 0x00000000, TCR3: 0x00000000, TCR4: 0x00000000, TCR5: 0x00000000, TDR0: 0x00000000, TDR1: 0x00000000, TDR2: 0x00000000, TDR3: 0x00000000, TFR0: 0x00000000, TFR1: 0x00000000, TFR2: 0x00000000, TFR3: 0x00000000, TMR: 0x00000000, RCSR: 0x00000000, RCR1: 0x00000000, RCR2: 0x00000000, RCR3: 0x00000000, RCR4: 0x00000000, RCR5: 0x00000000, RDR0: 0x00000000, RDR1: 0x00000000, RDR2: 0x00000000, RDR3: 0x00000000, RFR0: 0x00000000, RFR1: 0x00000000, RFR2: 0x00000000, RFR3: 0x00000000, RMR: 0x00000000, }; #[cfg(not(feature = "nosync"))] #[allow(renamed_and_removed_lints)] #[allow(private_no_mangle_statics)] #[no_mangle] static mut SAI2_TAKEN: bool = false; /// Safe access to SAI2 /// /// This function returns `Some(Instance)` if this instance is not /// currently taken, and `None` if it is. This ensures that if you /// do get `Some(Instance)`, you are ensured unique access to /// the peripheral and there cannot be data races (unless other /// code uses `unsafe`, of course). You can then pass the /// `Instance` around to other functions as required. When you're /// done with it, you can call `release(instance)` to return it. /// /// `Instance` itself dereferences to a `RegisterBlock`, which /// provides access to the peripheral's registers. #[cfg(not(feature = "nosync"))] #[inline] pub fn take() -> Option<Instance> { external_cortex_m::interrupt::free(|_| unsafe { if SAI2_TAKEN { None } else { SAI2_TAKEN = true; Some(INSTANCE) } }) } /// Release exclusive access to SAI2 /// /// This function allows you to return an `Instance` so that it /// is available to `take()` again. This function will panic if /// you return a different `Instance` or if this instance is not /// already taken. #[cfg(not(feature = "nosync"))] #[inline] pub fn release(inst: Instance) { external_cortex_m::interrupt::free(|_| unsafe { if SAI2_TAKEN && inst.addr == INSTANCE.addr { SAI2_TAKEN = false; } else { panic!("Released a peripheral which was not taken"); } }); } /// Unsafely steal SAI2 /// /// This function is similar to take() but forcibly takes the /// Instance, marking it as taken irregardless of its previous /// state. #[cfg(not(feature = "nosync"))] #[inline] pub unsafe fn steal() -> Instance { SAI2_TAKEN = true; INSTANCE } } /// Raw pointer to SAI2 /// /// Dereferencing this is unsafe because you are not ensured unique /// access to the peripheral, so you may encounter data races with /// other users of this peripheral. It is up to you to ensure you /// will not cause data races. /// /// This constant is provided for ease of use in unsafe code: you can /// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`. pub const SAI2: *const RegisterBlock = 0x40388000 as *const _; /// Access functions for the SAI3 peripheral instance pub mod SAI3 { use super::ResetValues; #[cfg(not(feature = "nosync"))] use super::Instance; #[cfg(not(feature = "nosync"))] const INSTANCE: Instance = Instance { addr: 0x4038c000, _marker: ::core::marker::PhantomData, }; /// Reset values for each field in SAI3 pub const reset: ResetValues = ResetValues { VERID: 0x03000000, PARAM: 0x00050504, TCSR: 0x00000000, TCR1: 0x00000000, TCR2: 0x00000000, TCR3: 0x00000000, TCR4: 0x00000000, TCR5: 0x00000000, TDR0: 0x00000000, TDR1: 0x00000000, TDR2: 0x00000000, TDR3: 0x00000000, TFR0: 0x00000000, TFR1: 0x00000000, TFR2: 0x00000000, TFR3: 0x00000000, TMR: 0x00000000, RCSR: 0x00000000, RCR1: 0x00000000, RCR2: 0x00000000, RCR3: 0x00000000, RCR4: 0x00000000, RCR5: 0x00000000, RDR0: 0x00000000, RDR1: 0x00000000, RDR2: 0x00000000, RDR3: 0x00000000, RFR0: 0x00000000, RFR1: 0x00000000, RFR2: 0x00000000, RFR3: 0x00000000, RMR: 0x00000000, }; #[cfg(not(feature = "nosync"))] #[allow(renamed_and_removed_lints)] #[allow(private_no_mangle_statics)] #[no_mangle] static mut SAI3_TAKEN: bool = false; /// Safe access to SAI3 /// /// This function returns `Some(Instance)` if this instance is not /// currently taken, and `None` if it is. This ensures that if you /// do get `Some(Instance)`, you are ensured unique access to /// the peripheral and there cannot be data races (unless other /// code uses `unsafe`, of course). You can then pass the /// `Instance` around to other functions as required. When you're /// done with it, you can call `release(instance)` to return it. /// /// `Instance` itself dereferences to a `RegisterBlock`, which /// provides access to the peripheral's registers. #[cfg(not(feature = "nosync"))] #[inline] pub fn take() -> Option<Instance> { external_cortex_m::interrupt::free(|_| unsafe { if SAI3_TAKEN { None } else { SAI3_TAKEN = true; Some(INSTANCE) } }) } /// Release exclusive access to SAI3 /// /// This function allows you to return an `Instance` so that it /// is available to `take()` again. This function will panic if /// you return a different `Instance` or if this instance is not /// already taken. #[cfg(not(feature = "nosync"))] #[inline] pub fn release(inst: Instance) { external_cortex_m::interrupt::free(|_| unsafe { if SAI3_TAKEN && inst.addr == INSTANCE.addr { SAI3_TAKEN = false; } else { panic!("Released a peripheral which was not taken"); } }); } /// Unsafely steal SAI3 /// /// This function is similar to take() but forcibly takes the /// Instance, marking it as taken irregardless of its previous /// state. #[cfg(not(feature = "nosync"))] #[inline] pub unsafe fn steal() -> Instance { SAI3_TAKEN = true; INSTANCE } } /// Raw pointer to SAI3 /// /// Dereferencing this is unsafe because you are not ensured unique /// access to the peripheral, so you may encounter data races with /// other users of this peripheral. It is up to you to ensure you /// will not cause data races. /// /// This constant is provided for ease of use in unsafe code: you can /// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`. pub const SAI3: *const RegisterBlock = 0x4038c000 as *const _;